[deliverable/linux.git] / include / linux / mfd / rc5t583.h

/*
 * Core driver interface to access RICOH_RC5T583 power management chip.
 *
 * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
 * Author: Laxman dewangan <ldewangan@nvidia.com>
 *
 * Based on code
 *      Copyright (C) 2011 RICOH COMPANY,LTD
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 */

#ifndef __LINUX_MFD_RC5T583_H
#define __LINUX_MFD_RC5T583_H

#include <linux/mutex.h>
#include <linux/types.h>
#include <linux/regmap.h>

#define RC5T583_MAX_REGS		0xF8

/* Maximum number of main interrupts */
#define MAX_MAIN_INTERRUPT		5
#define RC5T583_MAX_GPEDGE_REG		2
#define RC5T583_MAX_INTERRUPT_MASK_REGS	9

/* Interrupt enable register */
#define RC5T583_INT_EN_SYS1	0x19
#define RC5T583_INT_EN_SYS2	0x1D
#define RC5T583_INT_EN_DCDC	0x41
#define RC5T583_INT_EN_RTC	0xED
#define RC5T583_INT_EN_ADC1	0x90
#define RC5T583_INT_EN_ADC2	0x91
#define RC5T583_INT_EN_ADC3	0x92

/* Interrupt status registers (monitor regs in Ricoh)*/
#define RC5T583_INTC_INTPOL	0xAD
#define RC5T583_INTC_INTEN	0xAE
#define RC5T583_INTC_INTMON	0xAF

#define RC5T583_INT_MON_GRP	0xAF
#define RC5T583_INT_MON_SYS1	0x1B
#define RC5T583_INT_MON_SYS2	0x1F
#define RC5T583_INT_MON_DCDC	0x43
#define RC5T583_INT_MON_RTC	0xEE

/* Interrupt clearing registers */
#define RC5T583_INT_IR_SYS1	0x1A
#define RC5T583_INT_IR_SYS2	0x1E
#define RC5T583_INT_IR_DCDC	0x42
#define RC5T583_INT_IR_RTC	0xEE
#define RC5T583_INT_IR_ADCL	0x94
#define RC5T583_INT_IR_ADCH	0x95
#define RC5T583_INT_IR_ADCEND	0x96
#define RC5T583_INT_IR_GPIOR	0xA9
#define RC5T583_INT_IR_GPIOF	0xAA

/* Sleep sequence registers */
#define RC5T583_SLPSEQ1		0x21
#define RC5T583_SLPSEQ2		0x22
#define RC5T583_SLPSEQ3		0x23
#define RC5T583_SLPSEQ4		0x24
#define RC5T583_SLPSEQ5		0x25
#define RC5T583_SLPSEQ6		0x26
#define RC5T583_SLPSEQ7		0x27
#define RC5T583_SLPSEQ8		0x28
#define RC5T583_SLPSEQ9		0x29
#define RC5T583_SLPSEQ10	0x2A
#define RC5T583_SLPSEQ11	0x2B

/* Regulator registers */
#define RC5T583_REG_DC0CTL	0x30
#define RC5T583_REG_DC0DAC	0x31
#define RC5T583_REG_DC0LATCTL	0x32
#define RC5T583_REG_SR0CTL	0x33

#define RC5T583_REG_DC1CTL	0x34
#define RC5T583_REG_DC1DAC	0x35
#define RC5T583_REG_DC1LATCTL	0x36
#define RC5T583_REG_SR1CTL	0x37

#define RC5T583_REG_DC2CTL	0x38
#define RC5T583_REG_DC2DAC	0x39
#define RC5T583_REG_DC2LATCTL	0x3A
#define RC5T583_REG_SR2CTL	0x3B

#define RC5T583_REG_DC3CTL	0x3C
#define RC5T583_REG_DC3DAC	0x3D
#define RC5T583_REG_DC3LATCTL	0x3E
#define RC5T583_REG_SR3CTL	0x3F


#define RC5T583_REG_LDOEN1	0x50
#define RC5T583_REG_LDOEN2	0x51
#define RC5T583_REG_LDODIS1	0x52
#define RC5T583_REG_LDODIS2	0x53

#define RC5T583_REG_LDO0DAC	0x54
#define RC5T583_REG_LDO1DAC	0x55
#define RC5T583_REG_LDO2DAC	0x56
#define RC5T583_REG_LDO3DAC	0x57
#define RC5T583_REG_LDO4DAC	0x58
#define RC5T583_REG_LDO5DAC	0x59
#define RC5T583_REG_LDO6DAC	0x5A
#define RC5T583_REG_LDO7DAC	0x5B
#define RC5T583_REG_LDO8DAC	0x5C
#define RC5T583_REG_LDO9DAC	0x5D

#define RC5T583_REG_DC0DAC_DS	0x60
#define RC5T583_REG_DC1DAC_DS	0x61
#define RC5T583_REG_DC2DAC_DS	0x62
#define RC5T583_REG_DC3DAC_DS	0x63

#define RC5T583_REG_LDO0DAC_DS	0x64
#define RC5T583_REG_LDO1DAC_DS	0x65
#define RC5T583_REG_LDO2DAC_DS	0x66
#define RC5T583_REG_LDO3DAC_DS	0x67
#define RC5T583_REG_LDO4DAC_DS	0x68
#define RC5T583_REG_LDO5DAC_DS	0x69
#define RC5T583_REG_LDO6DAC_DS	0x6A
#define RC5T583_REG_LDO7DAC_DS	0x6B
#define RC5T583_REG_LDO8DAC_DS	0x6C
#define RC5T583_REG_LDO9DAC_DS	0x6D

/* GPIO register base address */
#define RC5T583_GPIO_IOSEL	0xA0
#define RC5T583_GPIO_PDEN	0xA1
#define RC5T583_GPIO_IOOUT	0xA2
#define RC5T583_GPIO_PGSEL	0xA3
#define RC5T583_GPIO_GPINV	0xA4
#define RC5T583_GPIO_GPDEB	0xA5
#define RC5T583_GPIO_GPEDGE1	0xA6
#define RC5T583_GPIO_GPEDGE2	0xA7
#define RC5T583_GPIO_EN_INT	0xA8
#define RC5T583_GPIO_MON_IOIN	0xAB
#define RC5T583_GPIO_GPOFUNC	0xAC

/* RICOH_RC5T583 IRQ definitions */
enum {
	RC5T583_IRQ_ONKEY,
	RC5T583_IRQ_ACOK,
	RC5T583_IRQ_LIDOPEN,
	RC5T583_IRQ_PREOT,
	RC5T583_IRQ_CLKSTP,
	RC5T583_IRQ_ONKEY_OFF,
	RC5T583_IRQ_WD,
	RC5T583_IRQ_EN_PWRREQ1,
	RC5T583_IRQ_EN_PWRREQ2,
	RC5T583_IRQ_PRE_VINDET,

	RC5T583_IRQ_DC0LIM,
	RC5T583_IRQ_DC1LIM,
	RC5T583_IRQ_DC2LIM,
	RC5T583_IRQ_DC3LIM,

	RC5T583_IRQ_CTC,
	RC5T583_IRQ_YALE,
	RC5T583_IRQ_DALE,
	RC5T583_IRQ_WALE,

	RC5T583_IRQ_AIN1L,
	RC5T583_IRQ_AIN2L,
	RC5T583_IRQ_AIN3L,
	RC5T583_IRQ_VBATL,
	RC5T583_IRQ_VIN3L,
	RC5T583_IRQ_VIN8L,
	RC5T583_IRQ_AIN1H,
	RC5T583_IRQ_AIN2H,
	RC5T583_IRQ_AIN3H,
	RC5T583_IRQ_VBATH,
	RC5T583_IRQ_VIN3H,
	RC5T583_IRQ_VIN8H,
	RC5T583_IRQ_ADCEND,

	RC5T583_IRQ_GPIO0,
	RC5T583_IRQ_GPIO1,
	RC5T583_IRQ_GPIO2,
	RC5T583_IRQ_GPIO3,
	RC5T583_IRQ_GPIO4,
	RC5T583_IRQ_GPIO5,
	RC5T583_IRQ_GPIO6,
	RC5T583_IRQ_GPIO7,

	/* Should be last entry */
	RC5T583_MAX_IRQS,
};

/* Ricoh583 gpio definitions */
enum {
	RC5T583_GPIO0,
	RC5T583_GPIO1,
	RC5T583_GPIO2,
	RC5T583_GPIO3,
	RC5T583_GPIO4,
	RC5T583_GPIO5,
	RC5T583_GPIO6,
	RC5T583_GPIO7,

	/* Should be last entry */
	RC5T583_MAX_GPIO,
};

enum {
	RC5T583_DS_NONE,
	RC5T583_DS_DC0,
	RC5T583_DS_DC1,
	RC5T583_DS_DC2,
	RC5T583_DS_DC3,
	RC5T583_DS_LDO0,
	RC5T583_DS_LDO1,
	RC5T583_DS_LDO2,
	RC5T583_DS_LDO3,
	RC5T583_DS_LDO4,
	RC5T583_DS_LDO5,
	RC5T583_DS_LDO6,
	RC5T583_DS_LDO7,
	RC5T583_DS_LDO8,
	RC5T583_DS_LDO9,
	RC5T583_DS_PSO0,
	RC5T583_DS_PSO1,
	RC5T583_DS_PSO2,
	RC5T583_DS_PSO3,
	RC5T583_DS_PSO4,
	RC5T583_DS_PSO5,
	RC5T583_DS_PSO6,
	RC5T583_DS_PSO7,

	/* Should be last entry */
	RC5T583_DS_MAX,
};

/*
 * Ricoh pmic RC5T583 supports sleep through two external controls.
 * The output of gpios and regulator can be enable/disable through
 * this external signals.
 */
enum {
	RC5T583_EXT_PWRREQ1_CONTROL = 0x1,
	RC5T583_EXT_PWRREQ2_CONTROL = 0x2,
};

enum {
	RC5T583_REGULATOR_DC0,
	RC5T583_REGULATOR_DC1,
	RC5T583_REGULATOR_DC2,
	RC5T583_REGULATOR_DC3,
	RC5T583_REGULATOR_LDO0,
	RC5T583_REGULATOR_LDO1,
	RC5T583_REGULATOR_LDO2,
	RC5T583_REGULATOR_LDO3,
	RC5T583_REGULATOR_LDO4,
	RC5T583_REGULATOR_LDO5,
	RC5T583_REGULATOR_LDO6,
	RC5T583_REGULATOR_LDO7,
	RC5T583_REGULATOR_LDO8,
	RC5T583_REGULATOR_LDO9,

	/* Should be last entry */
	RC5T583_REGULATOR_MAX,
};

struct rc5t583 {
	struct device	*dev;
	struct regmap	*regmap;
	int		chip_irq;
	int		irq_base;
	struct mutex	irq_lock;
	unsigned long	group_irq_en[MAX_MAIN_INTERRUPT];

	/* For main interrupt bits in INTC */
	uint8_t		intc_inten_reg;

	/* For group interrupt bits and address */
	uint8_t		irq_en_reg[RC5T583_MAX_INTERRUPT_MASK_REGS];

	/* For gpio edge */
	uint8_t		gpedge_reg[RC5T583_MAX_GPEDGE_REG];
};

/*
 * rc5t583_platform_data: Platform data for ricoh rc5t583 pmu.
 * The board specific data is provided through this structure.
 * @irq_base: Irq base number on which this device registers their interrupts.
 * @gpio_base: GPIO base from which gpio of this device will start.
 * @enable_shutdown: Enable shutdown through the input pin "shutdown".
 * @regulator_deepsleep_slot: The slot number on which device goes to sleep
 *		in device sleep mode.
 * @regulator_ext_pwr_control: External power request regulator control. The
 *		regulator output enable/disable is controlled by the external
 *		power request input state.
 * @reg_init_data: Regulator init data.
 */

struct rc5t583_platform_data {
	int		irq_base;
	int		gpio_base;
	bool		enable_shutdown;
	int		regulator_deepsleep_slot[RC5T583_REGULATOR_MAX];
	unsigned long	regulator_ext_pwr_control[RC5T583_REGULATOR_MAX];
	struct regulator_init_data *reg_init_data[RC5T583_REGULATOR_MAX];
};

static inline int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val)
{
	struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
	return regmap_write(rc5t583->regmap, reg, val);
}

static inline int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val)
{
	struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
	unsigned int ival;
	int ret;
	ret = regmap_read(rc5t583->regmap, reg, &ival);
	if (!ret)
		*val = (uint8_t)ival;
	return ret;
}

static inline int rc5t583_set_bits(struct device *dev, unsigned int reg,
			unsigned int bit_mask)
{
	struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
	return regmap_update_bits(rc5t583->regmap, reg, bit_mask, bit_mask);
}

static inline int rc5t583_clear_bits(struct device *dev, unsigned int reg,
			unsigned int bit_mask)
{
	struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
	return regmap_update_bits(rc5t583->regmap, reg, bit_mask, 0);
}

static inline int rc5t583_update(struct device *dev, unsigned int reg,
		unsigned int val, unsigned int mask)
{
	struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
	return regmap_update_bits(rc5t583->regmap, reg, mask, val);
}

int rc5t583_ext_power_req_config(struct device *dev, int deepsleep_id,
	int ext_pwr_req, int deepsleep_slot_nr);
int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base);
int rc5t583_irq_exit(struct rc5t583 *rc5t583);

#endif
Commit	Line	Data
1b1247dd LD	1	/*
	2	* Core driver interface to access RICOH_RC5T583 power management chip.
	3	*
	4	* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
	5	* Author: Laxman dewangan <ldewangan@nvidia.com>
	6	*
	7	* Based on code
	8	* Copyright (C) 2011 RICOH COMPANY,LTD
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms and conditions of the GNU General Public License,
	12	* version 2, as published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope it will be useful, but WITHOUT
	15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	17	* more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	21	*
	22	*/
	23
	24	#ifndef __LINUX_MFD_RC5T583_H
	25	#define __LINUX_MFD_RC5T583_H
	26
	27	#include <linux/mutex.h>
	28	#include <linux/types.h>
82ea267f	29	#include <linux/regmap.h>
1b1247dd LD	30
	31	#define RC5T583_MAX_REGS 0xF8
	32
	33	/* Maximum number of main interrupts */
	34	#define MAX_MAIN_INTERRUPT 5
	35	#define RC5T583_MAX_GPEDGE_REG 2
	36	#define RC5T583_MAX_INTERRUPT_MASK_REGS 9
	37
	38	/* Interrupt enable register */
	39	#define RC5T583_INT_EN_SYS1 0x19
	40	#define RC5T583_INT_EN_SYS2 0x1D
	41	#define RC5T583_INT_EN_DCDC 0x41
	42	#define RC5T583_INT_EN_RTC 0xED
	43	#define RC5T583_INT_EN_ADC1 0x90
	44	#define RC5T583_INT_EN_ADC2 0x91
	45	#define RC5T583_INT_EN_ADC3 0x92
	46
	47	/* Interrupt status registers (monitor regs in Ricoh)*/
	48	#define RC5T583_INTC_INTPOL 0xAD
	49	#define RC5T583_INTC_INTEN 0xAE
	50	#define RC5T583_INTC_INTMON 0xAF
	51
	52	#define RC5T583_INT_MON_GRP 0xAF
	53	#define RC5T583_INT_MON_SYS1 0x1B
	54	#define RC5T583_INT_MON_SYS2 0x1F
	55	#define RC5T583_INT_MON_DCDC 0x43
	56	#define RC5T583_INT_MON_RTC 0xEE
	57
	58	/* Interrupt clearing registers */
	59	#define RC5T583_INT_IR_SYS1 0x1A
	60	#define RC5T583_INT_IR_SYS2 0x1E
	61	#define RC5T583_INT_IR_DCDC 0x42
	62	#define RC5T583_INT_IR_RTC 0xEE
	63	#define RC5T583_INT_IR_ADCL 0x94
	64	#define RC5T583_INT_IR_ADCH 0x95
	65	#define RC5T583_INT_IR_ADCEND 0x96
	66	#define RC5T583_INT_IR_GPIOR 0xA9
	67	#define RC5T583_INT_IR_GPIOF 0xAA
	68
	69	/* Sleep sequence registers */
	70	#define RC5T583_SLPSEQ1 0x21
	71	#define RC5T583_SLPSEQ2 0x22
	72	#define RC5T583_SLPSEQ3 0x23
	73	#define RC5T583_SLPSEQ4 0x24
	74	#define RC5T583_SLPSEQ5 0x25
	75	#define RC5T583_SLPSEQ6 0x26
	76	#define RC5T583_SLPSEQ7 0x27
	77	#define RC5T583_SLPSEQ8 0x28
	78	#define RC5T583_SLPSEQ9 0x29
	79	#define RC5T583_SLPSEQ10 0x2A
	80	#define RC5T583_SLPSEQ11 0x2B
	81
	82	/* Regulator registers */
	83	#define RC5T583_REG_DC0CTL 0x30
	84	#define RC5T583_REG_DC0DAC 0x31
	85	#define RC5T583_REG_DC0LATCTL 0x32
	86	#define RC5T583_REG_SR0CTL 0x33
	87
	88	#define RC5T583_REG_DC1CTL 0x34
	89	#define RC5T583_REG_DC1DAC 0x35
	90	#define RC5T583_REG_DC1LATCTL 0x36
	91	#define RC5T583_REG_SR1CTL 0x37
	92
	93	#define RC5T583_REG_DC2CTL 0x38
94	#define RC5T583_REG_DC2DAC 0x39
95	#define RC5T583_REG_DC2LATCTL 0x3A
96	#define RC5T583_REG_SR2CTL 0x3B
97
98	#define RC5T583_REG_DC3CTL 0x3C
99	#define RC5T583_REG_DC3DAC 0x3D
100	#define RC5T583_REG_DC3LATCTL 0x3E
101	#define RC5T583_REG_SR3CTL 0x3F
102
103
104	#define RC5T583_REG_LDOEN1 0x50
105	#define RC5T583_REG_LDOEN2 0x51
106	#define RC5T583_REG_LDODIS1 0x52
107	#define RC5T583_REG_LDODIS2 0x53
108
109	#define RC5T583_REG_LDO0DAC 0x54
110	#define RC5T583_REG_LDO1DAC 0x55
111	#define RC5T583_REG_LDO2DAC 0x56
112	#define RC5T583_REG_LDO3DAC 0x57
113	#define RC5T583_REG_LDO4DAC 0x58
114	#define RC5T583_REG_LDO5DAC 0x59
115	#define RC5T583_REG_LDO6DAC 0x5A
116	#define RC5T583_REG_LDO7DAC 0x5B
117	#define RC5T583_REG_LDO8DAC 0x5C
118	#define RC5T583_REG_LDO9DAC 0x5D
119
120	#define RC5T583_REG_DC0DAC_DS 0x60
121	#define RC5T583_REG_DC1DAC_DS 0x61
122	#define RC5T583_REG_DC2DAC_DS 0x62
123	#define RC5T583_REG_DC3DAC_DS 0x63
124
125	#define RC5T583_REG_LDO0DAC_DS 0x64
126	#define RC5T583_REG_LDO1DAC_DS 0x65
127	#define RC5T583_REG_LDO2DAC_DS 0x66
128	#define RC5T583_REG_LDO3DAC_DS 0x67
129	#define RC5T583_REG_LDO4DAC_DS 0x68
130	#define RC5T583_REG_LDO5DAC_DS 0x69
131	#define RC5T583_REG_LDO6DAC_DS 0x6A
132	#define RC5T583_REG_LDO7DAC_DS 0x6B
133	#define RC5T583_REG_LDO8DAC_DS 0x6C
134	#define RC5T583_REG_LDO9DAC_DS 0x6D
135
136	/* GPIO register base address */
137	#define RC5T583_GPIO_IOSEL 0xA0
138	#define RC5T583_GPIO_PDEN 0xA1
139	#define RC5T583_GPIO_IOOUT 0xA2
140	#define RC5T583_GPIO_PGSEL 0xA3
141	#define RC5T583_GPIO_GPINV 0xA4
142	#define RC5T583_GPIO_GPDEB 0xA5
143	#define RC5T583_GPIO_GPEDGE1 0xA6
144	#define RC5T583_GPIO_GPEDGE2 0xA7
145	#define RC5T583_GPIO_EN_INT 0xA8
146	#define RC5T583_GPIO_MON_IOIN 0xAB
147	#define RC5T583_GPIO_GPOFUNC 0xAC
148
149	/* RICOH_RC5T583 IRQ definitions */
150	enum {
151	RC5T583_IRQ_ONKEY,
152	RC5T583_IRQ_ACOK,
153	RC5T583_IRQ_LIDOPEN,
154	RC5T583_IRQ_PREOT,
155	RC5T583_IRQ_CLKSTP,
156	RC5T583_IRQ_ONKEY_OFF,
157	RC5T583_IRQ_WD,
158	RC5T583_IRQ_EN_PWRREQ1,
159	RC5T583_IRQ_EN_PWRREQ2,
160	RC5T583_IRQ_PRE_VINDET,
161
162	RC5T583_IRQ_DC0LIM,
163	RC5T583_IRQ_DC1LIM,
164	RC5T583_IRQ_DC2LIM,
165	RC5T583_IRQ_DC3LIM,
166
167	RC5T583_IRQ_CTC,
168	RC5T583_IRQ_YALE,
169	RC5T583_IRQ_DALE,
170	RC5T583_IRQ_WALE,
171
172	RC5T583_IRQ_AIN1L,
173	RC5T583_IRQ_AIN2L,
174	RC5T583_IRQ_AIN3L,
175	RC5T583_IRQ_VBATL,
176	RC5T583_IRQ_VIN3L,
177	RC5T583_IRQ_VIN8L,
178	RC5T583_IRQ_AIN1H,
179	RC5T583_IRQ_AIN2H,
180	RC5T583_IRQ_AIN3H,
181	RC5T583_IRQ_VBATH,
182	RC5T583_IRQ_VIN3H,
183	RC5T583_IRQ_VIN8H,
184	RC5T583_IRQ_ADCEND,
185
186	RC5T583_IRQ_GPIO0,
187	RC5T583_IRQ_GPIO1,
188	RC5T583_IRQ_GPIO2,
189	RC5T583_IRQ_GPIO3,
190	RC5T583_IRQ_GPIO4,
191	RC5T583_IRQ_GPIO5,
192	RC5T583_IRQ_GPIO6,
193	RC5T583_IRQ_GPIO7,
194
195	/* Should be last entry */
196	RC5T583_MAX_IRQS,
197	};
198
199	/* Ricoh583 gpio definitions */
200	enum {
201	RC5T583_GPIO0,
202	RC5T583_GPIO1,
203	RC5T583_GPIO2,
204	RC5T583_GPIO3,
205	RC5T583_GPIO4,
206	RC5T583_GPIO5,
207	RC5T583_GPIO6,
208	RC5T583_GPIO7,
209
210	/* Should be last entry */
211	RC5T583_MAX_GPIO,
212	};
213
214	enum {
215	RC5T583_DS_NONE,
216	RC5T583_DS_DC0,
217	RC5T583_DS_DC1,
218	RC5T583_DS_DC2,
219	RC5T583_DS_DC3,
220	RC5T583_DS_LDO0,
221	RC5T583_DS_LDO1,
222	RC5T583_DS_LDO2,
223	RC5T583_DS_LDO3,
224	RC5T583_DS_LDO4,
225	RC5T583_DS_LDO5,
226	RC5T583_DS_LDO6,
227	RC5T583_DS_LDO7,
228	RC5T583_DS_LDO8,
229	RC5T583_DS_LDO9,
230	RC5T583_DS_PSO0,
231	RC5T583_DS_PSO1,
232	RC5T583_DS_PSO2,
233	RC5T583_DS_PSO3,
234	RC5T583_DS_PSO4,
235	RC5T583_DS_PSO5,
236	RC5T583_DS_PSO6,
237	RC5T583_DS_PSO7,
238
239	/* Should be last entry */
240	RC5T583_DS_MAX,
241	};
242
243	/*
244	* Ricoh pmic RC5T583 supports sleep through two external controls.
245	* The output of gpios and regulator can be enable/disable through
246	* this external signals.
247	*/
248	enum {
249	RC5T583_EXT_PWRREQ1_CONTROL = 0x1,
250	RC5T583_EXT_PWRREQ2_CONTROL = 0x2,
251	};
252
6ffc3270 LD	253	enum {
	254	RC5T583_REGULATOR_DC0,
	255	RC5T583_REGULATOR_DC1,
	256	RC5T583_REGULATOR_DC2,
	257	RC5T583_REGULATOR_DC3,
	258	RC5T583_REGULATOR_LDO0,
	259	RC5T583_REGULATOR_LDO1,
	260	RC5T583_REGULATOR_LDO2,
	261	RC5T583_REGULATOR_LDO3,
	262	RC5T583_REGULATOR_LDO4,
	263	RC5T583_REGULATOR_LDO5,
	264	RC5T583_REGULATOR_LDO6,
	265	RC5T583_REGULATOR_LDO7,
	266	RC5T583_REGULATOR_LDO8,
	267	RC5T583_REGULATOR_LDO9,
	268
	269	/* Should be last entry */
	270	RC5T583_REGULATOR_MAX,
	271	};
	272
1b1247dd LD	273	struct rc5t583 {
	274	struct device *dev;
	275	struct regmap *regmap;
	276	int chip_irq;
	277	int irq_base;
	278	struct mutex irq_lock;
	279	unsigned long group_irq_en[MAX_MAIN_INTERRUPT];
	280
	281	/* For main interrupt bits in INTC */
	282	uint8_t intc_inten_reg;
	283
	284	/* For group interrupt bits and address */
	285	uint8_t irq_en_reg[RC5T583_MAX_INTERRUPT_MASK_REGS];
	286
	287	/* For gpio edge */
	288	uint8_t gpedge_reg[RC5T583_MAX_GPEDGE_REG];
	289	};
	290
	291	/*
	292	* rc5t583_platform_data: Platform data for ricoh rc5t583 pmu.
	293	* The board specific data is provided through this structure.
	294	* @irq_base: Irq base number on which this device registers their interrupts.
e9fe32bc	295	* @gpio_base: GPIO base from which gpio of this device will start.
1b1247dd	296	* @enable_shutdown: Enable shutdown through the input pin "shutdown".
6ffc3270 LD	297	* @regulator_deepsleep_slot: The slot number on which device goes to sleep
	298	* in device sleep mode.
	299	* @regulator_ext_pwr_control: External power request regulator control. The
	300	* regulator output enable/disable is controlled by the external
	301	* power request input state.
	302	* @reg_init_data: Regulator init data.
1b1247dd LD	303	*/
	304
	305	struct rc5t583_platform_data {
	306	int irq_base;
e9fe32bc	307	int gpio_base;
1b1247dd	308	bool enable_shutdown;
6ffc3270 LD	309	int regulator_deepsleep_slot[RC5T583_REGULATOR_MAX];
	310	unsigned long regulator_ext_pwr_control[RC5T583_REGULATOR_MAX];
	311	struct regulator_init_data *reg_init_data[RC5T583_REGULATOR_MAX];
1b1247dd LD	312	};
1b1247dd LD	313
82ea267f PG	314	static inline int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val)
	315	{
	316	struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
	317	return regmap_write(rc5t583->regmap, reg, val);
	318	}
	319
	320	static inline int rc5t583_read(struct device dev, uint8_t reg, uint8_t val)
	321	{
	322	struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
	323	unsigned int ival;
	324	int ret;
	325	ret = regmap_read(rc5t583->regmap, reg, &ival);
	326	if (!ret)
	327	*val = (uint8_t)ival;
	328	return ret;
	329	}
	330
	331	static inline int rc5t583_set_bits(struct device *dev, unsigned int reg,
	332	unsigned int bit_mask)
	333	{
	334	struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
	335	return regmap_update_bits(rc5t583->regmap, reg, bit_mask, bit_mask);
	336	}
	337
	338	static inline int rc5t583_clear_bits(struct device *dev, unsigned int reg,
	339	unsigned int bit_mask)
	340	{
	341	struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
	342	return regmap_update_bits(rc5t583->regmap, reg, bit_mask, 0);
	343	}
	344
	345	static inline int rc5t583_update(struct device *dev, unsigned int reg,
	346	unsigned int val, unsigned int mask)
	347	{
	348	struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
	349	return regmap_update_bits(rc5t583->regmap, reg, mask, val);
	350	}
	351
1b1247dd LD	352	int rc5t583_ext_power_req_config(struct device *dev, int deepsleep_id,
	353	int ext_pwr_req, int deepsleep_slot_nr);
	354	int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base);
	355	int rc5t583_irq_exit(struct rc5t583 *rc5t583);
	356
	357	#endif