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35bdd290 AR |
1 | /* |
2 | * Copyright (c) 2009-2011 Wind River Systems, Inc. | |
3 | * Copyright (c) 2011 ST Microelectronics (Alessandro Rubini) | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | |
12 | * See the GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | * | |
18 | * The STMicroelectronics ConneXt (STA2X11) chip has several unrelated | |
19 | * functions in one PCI endpoint functions. This driver simply | |
20 | * registers the platform devices in this iomemregion and exports a few | |
21 | * functions to access common registers | |
22 | */ | |
23 | ||
24 | #ifndef __STA2X11_MFD_H | |
25 | #define __STA2X11_MFD_H | |
26 | #include <linux/types.h> | |
27 | #include <linux/pci.h> | |
28 | ||
1950c716 DC |
29 | enum sta2x11_mfd_plat_dev { |
30 | sta2x11_sctl = 0, | |
31 | sta2x11_gpio, | |
32 | sta2x11_scr, | |
33 | sta2x11_time, | |
34 | sta2x11_apbreg, | |
35 | sta2x11_apb_soc_regs, | |
36 | sta2x11_vic, | |
37 | sta2x11_n_mfd_plat_devs, | |
38 | }; | |
39 | ||
b18adafc DC |
40 | #define STA2X11_MFD_SCTL_NAME "sta2x11-sctl" |
41 | #define STA2X11_MFD_GPIO_NAME "sta2x11-gpio" | |
42 | #define STA2X11_MFD_SCR_NAME "sta2x11-scr" | |
43 | #define STA2X11_MFD_TIME_NAME "sta2x11-time" | |
44 | #define STA2X11_MFD_APBREG_NAME "sta2x11-apbreg" | |
45 | #define STA2X11_MFD_APB_SOC_REGS_NAME "sta2x11-apb-soc-regs" | |
46 | #define STA2X11_MFD_VIC_NAME "sta2x11-vic" | |
47 | ||
1950c716 DC |
48 | extern u32 |
49 | __sta2x11_mfd_mask(struct pci_dev *, u32, u32, u32, enum sta2x11_mfd_plat_dev); | |
50 | ||
35bdd290 AR |
51 | /* |
52 | * The MFD PCI block includes the GPIO peripherals and other register blocks. | |
53 | * For GPIO, we have 32*4 bits (I use "gsta" for "gpio sta2x11".) | |
54 | */ | |
55 | #define GSTA_GPIO_PER_BLOCK 32 | |
56 | #define GSTA_NR_BLOCKS 4 | |
57 | #define GSTA_NR_GPIO (GSTA_GPIO_PER_BLOCK * GSTA_NR_BLOCKS) | |
58 | ||
59 | /* Pinconfig is set by the board definition: altfunc, pull-up, pull-down */ | |
60 | struct sta2x11_gpio_pdata { | |
61 | unsigned pinconfig[GSTA_NR_GPIO]; | |
62 | }; | |
63 | ||
64 | /* Macros below lifted from sh_pfc.h, with minor differences */ | |
65 | #define PINMUX_TYPE_NONE 0 | |
66 | #define PINMUX_TYPE_FUNCTION 1 | |
67 | #define PINMUX_TYPE_OUTPUT_LOW 2 | |
68 | #define PINMUX_TYPE_OUTPUT_HIGH 3 | |
69 | #define PINMUX_TYPE_INPUT 4 | |
70 | #define PINMUX_TYPE_INPUT_PULLUP 5 | |
71 | #define PINMUX_TYPE_INPUT_PULLDOWN 6 | |
72 | ||
73 | /* Give names to GPIO pins, like PXA does, taken from the manual */ | |
74 | #define STA2X11_GPIO0 0 | |
75 | #define STA2X11_GPIO1 1 | |
76 | #define STA2X11_GPIO2 2 | |
77 | #define STA2X11_GPIO3 3 | |
78 | #define STA2X11_GPIO4 4 | |
79 | #define STA2X11_GPIO5 5 | |
80 | #define STA2X11_GPIO6 6 | |
81 | #define STA2X11_GPIO7 7 | |
82 | #define STA2X11_GPIO8_RGBOUT_RED7 8 | |
83 | #define STA2X11_GPIO9_RGBOUT_RED6 9 | |
84 | #define STA2X11_GPIO10_RGBOUT_RED5 10 | |
85 | #define STA2X11_GPIO11_RGBOUT_RED4 11 | |
86 | #define STA2X11_GPIO12_RGBOUT_RED3 12 | |
87 | #define STA2X11_GPIO13_RGBOUT_RED2 13 | |
88 | #define STA2X11_GPIO14_RGBOUT_RED1 14 | |
89 | #define STA2X11_GPIO15_RGBOUT_RED0 15 | |
90 | #define STA2X11_GPIO16_RGBOUT_GREEN7 16 | |
91 | #define STA2X11_GPIO17_RGBOUT_GREEN6 17 | |
92 | #define STA2X11_GPIO18_RGBOUT_GREEN5 18 | |
93 | #define STA2X11_GPIO19_RGBOUT_GREEN4 19 | |
94 | #define STA2X11_GPIO20_RGBOUT_GREEN3 20 | |
95 | #define STA2X11_GPIO21_RGBOUT_GREEN2 21 | |
96 | #define STA2X11_GPIO22_RGBOUT_GREEN1 22 | |
97 | #define STA2X11_GPIO23_RGBOUT_GREEN0 23 | |
98 | #define STA2X11_GPIO24_RGBOUT_BLUE7 24 | |
99 | #define STA2X11_GPIO25_RGBOUT_BLUE6 25 | |
100 | #define STA2X11_GPIO26_RGBOUT_BLUE5 26 | |
101 | #define STA2X11_GPIO27_RGBOUT_BLUE4 27 | |
102 | #define STA2X11_GPIO28_RGBOUT_BLUE3 28 | |
103 | #define STA2X11_GPIO29_RGBOUT_BLUE2 29 | |
104 | #define STA2X11_GPIO30_RGBOUT_BLUE1 30 | |
105 | #define STA2X11_GPIO31_RGBOUT_BLUE0 31 | |
106 | #define STA2X11_GPIO32_RGBOUT_VSYNCH 32 | |
107 | #define STA2X11_GPIO33_RGBOUT_HSYNCH 33 | |
108 | #define STA2X11_GPIO34_RGBOUT_DEN 34 | |
109 | #define STA2X11_GPIO35_ETH_CRS_DV 35 | |
110 | #define STA2X11_GPIO36_ETH_TXD1 36 | |
111 | #define STA2X11_GPIO37_ETH_TXD0 37 | |
112 | #define STA2X11_GPIO38_ETH_TX_EN 38 | |
113 | #define STA2X11_GPIO39_MDIO 39 | |
114 | #define STA2X11_GPIO40_ETH_REF_CLK 40 | |
115 | #define STA2X11_GPIO41_ETH_RXD1 41 | |
116 | #define STA2X11_GPIO42_ETH_RXD0 42 | |
117 | #define STA2X11_GPIO43_MDC 43 | |
118 | #define STA2X11_GPIO44_CAN_TX 44 | |
119 | #define STA2X11_GPIO45_CAN_RX 45 | |
120 | #define STA2X11_GPIO46_MLB_DAT 46 | |
121 | #define STA2X11_GPIO47_MLB_SIG 47 | |
122 | #define STA2X11_GPIO48_SPI0_CLK 48 | |
123 | #define STA2X11_GPIO49_SPI0_TXD 49 | |
124 | #define STA2X11_GPIO50_SPI0_RXD 50 | |
125 | #define STA2X11_GPIO51_SPI0_FRM 51 | |
126 | #define STA2X11_GPIO52_SPI1_CLK 52 | |
127 | #define STA2X11_GPIO53_SPI1_TXD 53 | |
128 | #define STA2X11_GPIO54_SPI1_RXD 54 | |
129 | #define STA2X11_GPIO55_SPI1_FRM 55 | |
130 | #define STA2X11_GPIO56_SPI2_CLK 56 | |
131 | #define STA2X11_GPIO57_SPI2_TXD 57 | |
132 | #define STA2X11_GPIO58_SPI2_RXD 58 | |
133 | #define STA2X11_GPIO59_SPI2_FRM 59 | |
134 | #define STA2X11_GPIO60_I2C0_SCL 60 | |
135 | #define STA2X11_GPIO61_I2C0_SDA 61 | |
136 | #define STA2X11_GPIO62_I2C1_SCL 62 | |
137 | #define STA2X11_GPIO63_I2C1_SDA 63 | |
138 | #define STA2X11_GPIO64_I2C2_SCL 64 | |
139 | #define STA2X11_GPIO65_I2C2_SDA 65 | |
140 | #define STA2X11_GPIO66_I2C3_SCL 66 | |
141 | #define STA2X11_GPIO67_I2C3_SDA 67 | |
142 | #define STA2X11_GPIO68_MSP0_RCK 68 | |
143 | #define STA2X11_GPIO69_MSP0_RXD 69 | |
144 | #define STA2X11_GPIO70_MSP0_RFS 70 | |
145 | #define STA2X11_GPIO71_MSP0_TCK 71 | |
146 | #define STA2X11_GPIO72_MSP0_TXD 72 | |
147 | #define STA2X11_GPIO73_MSP0_TFS 73 | |
148 | #define STA2X11_GPIO74_MSP0_SCK 74 | |
149 | #define STA2X11_GPIO75_MSP1_CK 75 | |
150 | #define STA2X11_GPIO76_MSP1_RXD 76 | |
151 | #define STA2X11_GPIO77_MSP1_FS 77 | |
152 | #define STA2X11_GPIO78_MSP1_TXD 78 | |
153 | #define STA2X11_GPIO79_MSP2_CK 79 | |
154 | #define STA2X11_GPIO80_MSP2_RXD 80 | |
155 | #define STA2X11_GPIO81_MSP2_FS 81 | |
156 | #define STA2X11_GPIO82_MSP2_TXD 82 | |
157 | #define STA2X11_GPIO83_MSP3_CK 83 | |
158 | #define STA2X11_GPIO84_MSP3_RXD 84 | |
159 | #define STA2X11_GPIO85_MSP3_FS 85 | |
160 | #define STA2X11_GPIO86_MSP3_TXD 86 | |
161 | #define STA2X11_GPIO87_MSP4_CK 87 | |
162 | #define STA2X11_GPIO88_MSP4_RXD 88 | |
163 | #define STA2X11_GPIO89_MSP4_FS 89 | |
164 | #define STA2X11_GPIO90_MSP4_TXD 90 | |
165 | #define STA2X11_GPIO91_MSP5_CK 91 | |
166 | #define STA2X11_GPIO92_MSP5_RXD 92 | |
167 | #define STA2X11_GPIO93_MSP5_FS 93 | |
168 | #define STA2X11_GPIO94_MSP5_TXD 94 | |
169 | #define STA2X11_GPIO95_SDIO3_DAT3 95 | |
170 | #define STA2X11_GPIO96_SDIO3_DAT2 96 | |
171 | #define STA2X11_GPIO97_SDIO3_DAT1 97 | |
172 | #define STA2X11_GPIO98_SDIO3_DAT0 98 | |
173 | #define STA2X11_GPIO99_SDIO3_CLK 99 | |
174 | #define STA2X11_GPIO100_SDIO3_CMD 100 | |
175 | #define STA2X11_GPIO101 101 | |
176 | #define STA2X11_GPIO102 102 | |
177 | #define STA2X11_GPIO103 103 | |
178 | #define STA2X11_GPIO104 104 | |
179 | #define STA2X11_GPIO105_SDIO2_DAT3 105 | |
180 | #define STA2X11_GPIO106_SDIO2_DAT2 106 | |
181 | #define STA2X11_GPIO107_SDIO2_DAT1 107 | |
182 | #define STA2X11_GPIO108_SDIO2_DAT0 108 | |
183 | #define STA2X11_GPIO109_SDIO2_CLK 109 | |
184 | #define STA2X11_GPIO110_SDIO2_CMD 110 | |
185 | #define STA2X11_GPIO111 111 | |
186 | #define STA2X11_GPIO112 112 | |
187 | #define STA2X11_GPIO113 113 | |
188 | #define STA2X11_GPIO114 114 | |
189 | #define STA2X11_GPIO115_SDIO1_DAT3 115 | |
190 | #define STA2X11_GPIO116_SDIO1_DAT2 116 | |
191 | #define STA2X11_GPIO117_SDIO1_DAT1 117 | |
192 | #define STA2X11_GPIO118_SDIO1_DAT0 118 | |
193 | #define STA2X11_GPIO119_SDIO1_CLK 119 | |
194 | #define STA2X11_GPIO120_SDIO1_CMD 120 | |
195 | #define STA2X11_GPIO121 121 | |
196 | #define STA2X11_GPIO122 122 | |
197 | #define STA2X11_GPIO123 123 | |
198 | #define STA2X11_GPIO124 124 | |
199 | #define STA2X11_GPIO125_UART2_TXD 125 | |
200 | #define STA2X11_GPIO126_UART2_RXD 126 | |
201 | #define STA2X11_GPIO127_UART3_TXD 127 | |
202 | ||
203 | /* | |
204 | * The APB bridge has its own registers, needed by our users as well. | |
205 | * They are accessed with the following read/mask/write function. | |
206 | */ | |
1950c716 DC |
207 | static inline u32 |
208 | sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val) | |
209 | { | |
210 | return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apbreg); | |
211 | } | |
35bdd290 AR |
212 | |
213 | /* CAN and MLB */ | |
214 | #define APBREG_BSR 0x00 /* Bridge Status Reg */ | |
215 | #define APBREG_PAER 0x08 /* Peripherals Address Error Reg */ | |
216 | #define APBREG_PWAC 0x20 /* Peripheral Write Access Control reg */ | |
217 | #define APBREG_PRAC 0x40 /* Peripheral Read Access Control reg */ | |
218 | #define APBREG_PCG 0x60 /* Peripheral Clock Gating Reg */ | |
219 | #define APBREG_PUR 0x80 /* Peripheral Under Reset Reg */ | |
220 | #define APBREG_EMU_PCG 0xA0 /* Emulator Peripheral Clock Gating Reg */ | |
221 | ||
222 | #define APBREG_CAN (1 << 1) | |
223 | #define APBREG_MLB (1 << 3) | |
224 | ||
225 | /* SARAC */ | |
226 | #define APBREG_BSR_SARAC 0x100 /* Bridge Status Reg */ | |
227 | #define APBREG_PAER_SARAC 0x108 /* Peripherals Address Error Reg */ | |
228 | #define APBREG_PWAC_SARAC 0x120 /* Peripheral Write Access Control reg */ | |
229 | #define APBREG_PRAC_SARAC 0x140 /* Peripheral Read Access Control reg */ | |
230 | #define APBREG_PCG_SARAC 0x160 /* Peripheral Clock Gating Reg */ | |
231 | #define APBREG_PUR_SARAC 0x180 /* Peripheral Under Reset Reg */ | |
232 | #define APBREG_EMU_PCG_SARAC 0x1A0 /* Emulator Peripheral Clock Gating Reg */ | |
233 | ||
234 | #define APBREG_SARAC (1 << 2) | |
235 | ||
236 | /* | |
237 | * The system controller has its own registers. Some of these are accessed | |
238 | * by out users as well, using the following read/mask/write/function | |
239 | */ | |
1950c716 DC |
240 | static inline |
241 | u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val) | |
242 | { | |
243 | return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_sctl); | |
244 | } | |
35bdd290 AR |
245 | |
246 | #define SCTL_SCCTL 0x00 /* System controller control register */ | |
247 | #define SCTL_ARMCFG 0x04 /* ARM configuration register */ | |
248 | #define SCTL_SCPLLCTL 0x08 /* PLL control status register */ | |
818b5c25 DC |
249 | |
250 | #define SCTL_SCPLLCTL_AUDIO_PLL_PD BIT(1) | |
251 | #define SCTL_SCPLLCTL_FRAC_CONTROL BIT(3) | |
252 | #define SCTL_SCPLLCTL_STRB_BYPASS BIT(6) | |
253 | #define SCTL_SCPLLCTL_STRB_INPUT BIT(8) | |
254 | ||
35bdd290 | 255 | #define SCTL_SCPLLFCTRL 0x0c /* PLL frequency control register */ |
818b5c25 DC |
256 | |
257 | #define SCTL_SCPLLFCTRL_AUDIO_PLL_NDIV_MASK 0xff | |
258 | #define SCTL_SCPLLFCTRL_AUDIO_PLL_NDIV_SHIFT 10 | |
259 | #define SCTL_SCPLLFCTRL_AUDIO_PLL_IDF_MASK 7 | |
260 | #define SCTL_SCPLLFCTRL_AUDIO_PLL_IDF_SHIFT 21 | |
261 | #define SCTL_SCPLLFCTRL_AUDIO_PLL_ODF_MASK 7 | |
262 | #define SCTL_SCPLLFCTRL_AUDIO_PLL_ODF_SHIFT 18 | |
263 | #define SCTL_SCPLLFCTRL_DITHER_DISABLE_MASK 0x03 | |
264 | #define SCTL_SCPLLFCTRL_DITHER_DISABLE_SHIFT 4 | |
265 | ||
266 | ||
35bdd290 | 267 | #define SCTL_SCRESFRACT 0x10 /* PLL fractional input register */ |
818b5c25 DC |
268 | |
269 | #define SCTL_SCRESFRACT_MASK 0x0000ffff | |
270 | ||
271 | ||
35bdd290 AR |
272 | #define SCTL_SCRESCTRL1 0x14 /* Peripheral reset control 1 */ |
273 | #define SCTL_SCRESXTRL2 0x18 /* Peripheral reset control 2 */ | |
274 | #define SCTL_SCPEREN0 0x1c /* Peripheral clock enable register 0 */ | |
275 | #define SCTL_SCPEREN1 0x20 /* Peripheral clock enable register 1 */ | |
276 | #define SCTL_SCPEREN2 0x24 /* Peripheral clock enable register 2 */ | |
277 | #define SCTL_SCGRST 0x28 /* Peripheral global reset */ | |
d94e2553 | 278 | #define SCTL_SCPCIECSBRST 0x2c /* PCIe PAB CSB reset status register */ |
35bdd290 AR |
279 | #define SCTL_SCPCIPMCR1 0x30 /* PCI power management control 1 */ |
280 | #define SCTL_SCPCIPMCR2 0x34 /* PCI power management control 2 */ | |
281 | #define SCTL_SCPCIPMSR1 0x38 /* PCI power management status 1 */ | |
282 | #define SCTL_SCPCIPMSR2 0x3c /* PCI power management status 2 */ | |
283 | #define SCTL_SCPCIPMSR3 0x40 /* PCI power management status 3 */ | |
284 | #define SCTL_SCINTREN 0x44 /* Interrupt enable */ | |
285 | #define SCTL_SCRISR 0x48 /* RAW interrupt status */ | |
286 | #define SCTL_SCCLKSTAT0 0x4c /* Peripheral clocks status 0 */ | |
287 | #define SCTL_SCCLKSTAT1 0x50 /* Peripheral clocks status 1 */ | |
288 | #define SCTL_SCCLKSTAT2 0x54 /* Peripheral clocks status 2 */ | |
289 | #define SCTL_SCRSTSTA 0x58 /* Reset status register */ | |
290 | ||
291 | #define SCTL_SCRESCTRL1_USB_PHY_POR (1 << 0) | |
292 | #define SCTL_SCRESCTRL1_USB_OTG (1 << 1) | |
293 | #define SCTL_SCRESCTRL1_USB_HRST (1 << 2) | |
294 | #define SCTL_SCRESCTRL1_USB_PHY_HOST (1 << 3) | |
295 | #define SCTL_SCRESCTRL1_SATAII (1 << 4) | |
296 | #define SCTL_SCRESCTRL1_VIP (1 << 5) | |
297 | #define SCTL_SCRESCTRL1_PER_MMC0 (1 << 6) | |
298 | #define SCTL_SCRESCTRL1_PER_MMC1 (1 << 7) | |
299 | #define SCTL_SCRESCTRL1_PER_GPIO0 (1 << 8) | |
300 | #define SCTL_SCRESCTRL1_PER_GPIO1 (1 << 9) | |
301 | #define SCTL_SCRESCTRL1_PER_GPIO2 (1 << 10) | |
302 | #define SCTL_SCRESCTRL1_PER_GPIO3 (1 << 11) | |
303 | #define SCTL_SCRESCTRL1_PER_MTU0 (1 << 12) | |
304 | #define SCTL_SCRESCTRL1_KER_SPI0 (1 << 13) | |
305 | #define SCTL_SCRESCTRL1_KER_SPI1 (1 << 14) | |
306 | #define SCTL_SCRESCTRL1_KER_SPI2 (1 << 15) | |
307 | #define SCTL_SCRESCTRL1_KER_MCI0 (1 << 16) | |
308 | #define SCTL_SCRESCTRL1_KER_MCI1 (1 << 17) | |
309 | #define SCTL_SCRESCTRL1_PRE_HSI2C0 (1 << 18) | |
310 | #define SCTL_SCRESCTRL1_PER_HSI2C1 (1 << 19) | |
311 | #define SCTL_SCRESCTRL1_PER_HSI2C2 (1 << 20) | |
312 | #define SCTL_SCRESCTRL1_PER_HSI2C3 (1 << 21) | |
313 | #define SCTL_SCRESCTRL1_PER_MSP0 (1 << 22) | |
314 | #define SCTL_SCRESCTRL1_PER_MSP1 (1 << 23) | |
315 | #define SCTL_SCRESCTRL1_PER_MSP2 (1 << 24) | |
316 | #define SCTL_SCRESCTRL1_PER_MSP3 (1 << 25) | |
317 | #define SCTL_SCRESCTRL1_PER_MSP4 (1 << 26) | |
318 | #define SCTL_SCRESCTRL1_PER_MSP5 (1 << 27) | |
319 | #define SCTL_SCRESCTRL1_PER_MMC (1 << 28) | |
320 | #define SCTL_SCRESCTRL1_KER_MSP0 (1 << 29) | |
321 | #define SCTL_SCRESCTRL1_KER_MSP1 (1 << 30) | |
322 | #define SCTL_SCRESCTRL1_KER_MSP2 (1 << 31) | |
323 | ||
324 | #define SCTL_SCPEREN0_UART0 (1 << 0) | |
325 | #define SCTL_SCPEREN0_UART1 (1 << 1) | |
326 | #define SCTL_SCPEREN0_UART2 (1 << 2) | |
327 | #define SCTL_SCPEREN0_UART3 (1 << 3) | |
328 | #define SCTL_SCPEREN0_MSP0 (1 << 4) | |
329 | #define SCTL_SCPEREN0_MSP1 (1 << 5) | |
330 | #define SCTL_SCPEREN0_MSP2 (1 << 6) | |
331 | #define SCTL_SCPEREN0_MSP3 (1 << 7) | |
332 | #define SCTL_SCPEREN0_MSP4 (1 << 8) | |
333 | #define SCTL_SCPEREN0_MSP5 (1 << 9) | |
334 | #define SCTL_SCPEREN0_SPI0 (1 << 10) | |
335 | #define SCTL_SCPEREN0_SPI1 (1 << 11) | |
336 | #define SCTL_SCPEREN0_SPI2 (1 << 12) | |
337 | #define SCTL_SCPEREN0_I2C0 (1 << 13) | |
338 | #define SCTL_SCPEREN0_I2C1 (1 << 14) | |
339 | #define SCTL_SCPEREN0_I2C2 (1 << 15) | |
340 | #define SCTL_SCPEREN0_I2C3 (1 << 16) | |
341 | #define SCTL_SCPEREN0_SVDO_LVDS (1 << 17) | |
342 | #define SCTL_SCPEREN0_USB_HOST (1 << 18) | |
343 | #define SCTL_SCPEREN0_USB_OTG (1 << 19) | |
344 | #define SCTL_SCPEREN0_MCI0 (1 << 20) | |
345 | #define SCTL_SCPEREN0_MCI1 (1 << 21) | |
346 | #define SCTL_SCPEREN0_MCI2 (1 << 22) | |
347 | #define SCTL_SCPEREN0_MCI3 (1 << 23) | |
348 | #define SCTL_SCPEREN0_SATA (1 << 24) | |
349 | #define SCTL_SCPEREN0_ETHERNET (1 << 25) | |
350 | #define SCTL_SCPEREN0_VIC (1 << 26) | |
351 | #define SCTL_SCPEREN0_DMA_AUDIO (1 << 27) | |
352 | #define SCTL_SCPEREN0_DMA_SOC (1 << 28) | |
353 | #define SCTL_SCPEREN0_RAM (1 << 29) | |
354 | #define SCTL_SCPEREN0_VIP (1 << 30) | |
355 | #define SCTL_SCPEREN0_ARM (1 << 31) | |
356 | ||
357 | #define SCTL_SCPEREN1_UART0 (1 << 0) | |
358 | #define SCTL_SCPEREN1_UART1 (1 << 1) | |
359 | #define SCTL_SCPEREN1_UART2 (1 << 2) | |
360 | #define SCTL_SCPEREN1_UART3 (1 << 3) | |
361 | #define SCTL_SCPEREN1_MSP0 (1 << 4) | |
362 | #define SCTL_SCPEREN1_MSP1 (1 << 5) | |
363 | #define SCTL_SCPEREN1_MSP2 (1 << 6) | |
364 | #define SCTL_SCPEREN1_MSP3 (1 << 7) | |
365 | #define SCTL_SCPEREN1_MSP4 (1 << 8) | |
366 | #define SCTL_SCPEREN1_MSP5 (1 << 9) | |
367 | #define SCTL_SCPEREN1_SPI0 (1 << 10) | |
368 | #define SCTL_SCPEREN1_SPI1 (1 << 11) | |
369 | #define SCTL_SCPEREN1_SPI2 (1 << 12) | |
370 | #define SCTL_SCPEREN1_I2C0 (1 << 13) | |
371 | #define SCTL_SCPEREN1_I2C1 (1 << 14) | |
372 | #define SCTL_SCPEREN1_I2C2 (1 << 15) | |
373 | #define SCTL_SCPEREN1_I2C3 (1 << 16) | |
374 | #define SCTL_SCPEREN1_USB_PHY (1 << 17) | |
375 | ||
1950c716 DC |
376 | /* |
377 | * APB-SOC registers | |
378 | */ | |
379 | static inline | |
380 | u32 sta2x11_apb_soc_regs_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val) | |
381 | { | |
382 | return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apb_soc_regs); | |
383 | } | |
384 | ||
385 | #define PCIE_EP1_FUNC3_0_INTR_REG 0x000 | |
386 | #define PCIE_EP1_FUNC7_4_INTR_REG 0x004 | |
387 | #define PCIE_EP2_FUNC3_0_INTR_REG 0x008 | |
388 | #define PCIE_EP2_FUNC7_4_INTR_REG 0x00c | |
389 | #define PCIE_EP3_FUNC3_0_INTR_REG 0x010 | |
390 | #define PCIE_EP3_FUNC7_4_INTR_REG 0x014 | |
391 | #define PCIE_EP4_FUNC3_0_INTR_REG 0x018 | |
392 | #define PCIE_EP4_FUNC7_4_INTR_REG 0x01c | |
393 | #define PCIE_INTR_ENABLE0_REG 0x020 | |
394 | #define PCIE_INTR_ENABLE1_REG 0x024 | |
395 | #define PCIE_EP1_FUNC_TC_REG 0x028 | |
396 | #define PCIE_EP2_FUNC_TC_REG 0x02c | |
397 | #define PCIE_EP3_FUNC_TC_REG 0x030 | |
398 | #define PCIE_EP4_FUNC_TC_REG 0x034 | |
399 | #define PCIE_EP1_FUNC_F_REG 0x038 | |
400 | #define PCIE_EP2_FUNC_F_REG 0x03c | |
401 | #define PCIE_EP3_FUNC_F_REG 0x040 | |
402 | #define PCIE_EP4_FUNC_F_REG 0x044 | |
403 | #define PCIE_PAB_AMBA_SW_RST_REG 0x048 | |
404 | #define PCIE_PM_STATUS_0_PORT_0_4 0x04c | |
405 | #define PCIE_PM_STATUS_7_0_EP1 0x050 | |
406 | #define PCIE_PM_STATUS_7_0_EP2 0x054 | |
407 | #define PCIE_PM_STATUS_7_0_EP3 0x058 | |
408 | #define PCIE_PM_STATUS_7_0_EP4 0x05c | |
409 | #define PCIE_DEV_ID_0_EP1_REG 0x060 | |
410 | #define PCIE_CC_REV_ID_0_EP1_REG 0x064 | |
411 | #define PCIE_DEV_ID_1_EP1_REG 0x068 | |
412 | #define PCIE_CC_REV_ID_1_EP1_REG 0x06c | |
413 | #define PCIE_DEV_ID_2_EP1_REG 0x070 | |
414 | #define PCIE_CC_REV_ID_2_EP1_REG 0x074 | |
415 | #define PCIE_DEV_ID_3_EP1_REG 0x078 | |
416 | #define PCIE_CC_REV_ID_3_EP1_REG 0x07c | |
417 | #define PCIE_DEV_ID_4_EP1_REG 0x080 | |
418 | #define PCIE_CC_REV_ID_4_EP1_REG 0x084 | |
419 | #define PCIE_DEV_ID_5_EP1_REG 0x088 | |
420 | #define PCIE_CC_REV_ID_5_EP1_REG 0x08c | |
421 | #define PCIE_DEV_ID_6_EP1_REG 0x090 | |
422 | #define PCIE_CC_REV_ID_6_EP1_REG 0x094 | |
423 | #define PCIE_DEV_ID_7_EP1_REG 0x098 | |
424 | #define PCIE_CC_REV_ID_7_EP1_REG 0x09c | |
425 | #define PCIE_DEV_ID_0_EP2_REG 0x0a0 | |
426 | #define PCIE_CC_REV_ID_0_EP2_REG 0x0a4 | |
427 | #define PCIE_DEV_ID_1_EP2_REG 0x0a8 | |
428 | #define PCIE_CC_REV_ID_1_EP2_REG 0x0ac | |
429 | #define PCIE_DEV_ID_2_EP2_REG 0x0b0 | |
430 | #define PCIE_CC_REV_ID_2_EP2_REG 0x0b4 | |
431 | #define PCIE_DEV_ID_3_EP2_REG 0x0b8 | |
432 | #define PCIE_CC_REV_ID_3_EP2_REG 0x0bc | |
433 | #define PCIE_DEV_ID_4_EP2_REG 0x0c0 | |
434 | #define PCIE_CC_REV_ID_4_EP2_REG 0x0c4 | |
435 | #define PCIE_DEV_ID_5_EP2_REG 0x0c8 | |
436 | #define PCIE_CC_REV_ID_5_EP2_REG 0x0cc | |
437 | #define PCIE_DEV_ID_6_EP2_REG 0x0d0 | |
438 | #define PCIE_CC_REV_ID_6_EP2_REG 0x0d4 | |
439 | #define PCIE_DEV_ID_7_EP2_REG 0x0d8 | |
440 | #define PCIE_CC_REV_ID_7_EP2_REG 0x0dC | |
441 | #define PCIE_DEV_ID_0_EP3_REG 0x0e0 | |
442 | #define PCIE_CC_REV_ID_0_EP3_REG 0x0e4 | |
443 | #define PCIE_DEV_ID_1_EP3_REG 0x0e8 | |
444 | #define PCIE_CC_REV_ID_1_EP3_REG 0x0ec | |
445 | #define PCIE_DEV_ID_2_EP3_REG 0x0f0 | |
446 | #define PCIE_CC_REV_ID_2_EP3_REG 0x0f4 | |
447 | #define PCIE_DEV_ID_3_EP3_REG 0x0f8 | |
448 | #define PCIE_CC_REV_ID_3_EP3_REG 0x0fc | |
449 | #define PCIE_DEV_ID_4_EP3_REG 0x100 | |
450 | #define PCIE_CC_REV_ID_4_EP3_REG 0x104 | |
451 | #define PCIE_DEV_ID_5_EP3_REG 0x108 | |
452 | #define PCIE_CC_REV_ID_5_EP3_REG 0x10c | |
453 | #define PCIE_DEV_ID_6_EP3_REG 0x110 | |
454 | #define PCIE_CC_REV_ID_6_EP3_REG 0x114 | |
455 | #define PCIE_DEV_ID_7_EP3_REG 0x118 | |
456 | #define PCIE_CC_REV_ID_7_EP3_REG 0x11c | |
457 | #define PCIE_DEV_ID_0_EP4_REG 0x120 | |
458 | #define PCIE_CC_REV_ID_0_EP4_REG 0x124 | |
459 | #define PCIE_DEV_ID_1_EP4_REG 0x128 | |
460 | #define PCIE_CC_REV_ID_1_EP4_REG 0x12c | |
461 | #define PCIE_DEV_ID_2_EP4_REG 0x130 | |
462 | #define PCIE_CC_REV_ID_2_EP4_REG 0x134 | |
463 | #define PCIE_DEV_ID_3_EP4_REG 0x138 | |
464 | #define PCIE_CC_REV_ID_3_EP4_REG 0x13c | |
465 | #define PCIE_DEV_ID_4_EP4_REG 0x140 | |
466 | #define PCIE_CC_REV_ID_4_EP4_REG 0x144 | |
467 | #define PCIE_DEV_ID_5_EP4_REG 0x148 | |
468 | #define PCIE_CC_REV_ID_5_EP4_REG 0x14c | |
469 | #define PCIE_DEV_ID_6_EP4_REG 0x150 | |
470 | #define PCIE_CC_REV_ID_6_EP4_REG 0x154 | |
471 | #define PCIE_DEV_ID_7_EP4_REG 0x158 | |
472 | #define PCIE_CC_REV_ID_7_EP4_REG 0x15c | |
473 | #define PCIE_SUBSYS_VEN_ID_REG 0x160 | |
474 | #define PCIE_COMMON_CLOCK_CONFIG_0_4_0 0x164 | |
475 | #define PCIE_MIPHYP_SSC_EN_REG 0x168 | |
476 | #define PCIE_MIPHYP_ADDR_REG 0x16c | |
477 | #define PCIE_L1_ASPM_READY_REG 0x170 | |
478 | #define PCIE_EXT_CFG_RDY_REG 0x174 | |
479 | #define PCIE_SoC_INT_ROUTER_STATUS0_REG 0x178 | |
480 | #define PCIE_SoC_INT_ROUTER_STATUS1_REG 0x17c | |
481 | #define PCIE_SoC_INT_ROUTER_STATUS2_REG 0x180 | |
482 | #define PCIE_SoC_INT_ROUTER_STATUS3_REG 0x184 | |
483 | #define DMA_IP_CTRL_REG 0x324 | |
484 | #define DISP_BRIDGE_PU_PD_CTRL_REG 0x328 | |
485 | #define VIP_PU_PD_CTRL_REG 0x32c | |
486 | #define USB_MLB_PU_PD_CTRL_REG 0x330 | |
487 | #define SDIO_PU_PD_MISCFUNC_CTRL_REG1 0x334 | |
488 | #define SDIO_PU_PD_MISCFUNC_CTRL_REG2 0x338 | |
489 | #define UART_PU_PD_CTRL_REG 0x33c | |
490 | #define ARM_Lock 0x340 | |
491 | #define SYS_IO_CHAR_REG1 0x344 | |
492 | #define SYS_IO_CHAR_REG2 0x348 | |
493 | #define SATA_CORE_ID_REG 0x34c | |
494 | #define SATA_CTRL_REG 0x350 | |
495 | #define I2C_HSFIX_MISC_REG 0x354 | |
496 | #define SPARE2_RESERVED 0x358 | |
497 | #define SPARE3_RESERVED 0x35c | |
498 | #define MASTER_LOCK_REG 0x368 | |
499 | #define SYSTEM_CONFIG_STATUS_REG 0x36c | |
500 | #define MSP_CLK_CTRL_REG 0x39c | |
501 | #define COMPENSATION_REG1 0x3c4 | |
502 | #define COMPENSATION_REG2 0x3c8 | |
503 | #define COMPENSATION_REG3 0x3cc | |
504 | #define TEST_CTL_REG 0x3d0 | |
505 | ||
dba6c1ae DC |
506 | /* |
507 | * SECR (OTP) registers | |
508 | */ | |
509 | #define STA2X11_SECR_CR 0x00 | |
510 | #define STA2X11_SECR_FVR0 0x10 | |
511 | #define STA2X11_SECR_FVR1 0x14 | |
512 | ||
29f5b5a3 DC |
513 | extern int sta2x11_mfd_get_regs_data(struct platform_device *pdev, |
514 | enum sta2x11_mfd_plat_dev index, | |
515 | void __iomem **regs, | |
516 | spinlock_t **lock); | |
517 | ||
35bdd290 | 518 | #endif /* __STA2X11_MFD_H */ |