[deliverable/linux.git] / include / linux / mfd / wm831x / core.h

/*
 * include/linux/mfd/wm831x/core.h -- Core interface for WM831x
 *
 * Copyright 2009 Wolfson Microelectronics PLC.
 *
 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 */

#ifndef __MFD_WM831X_CORE_H__
#define __MFD_WM831X_CORE_H__

#include <linux/completion.h>
#include <linux/interrupt.h>

/*
 * Register values.
 */
#define WM831X_RESET_ID                         0x00
#define WM831X_REVISION                         0x01
#define WM831X_PARENT_ID                        0x4000
#define WM831X_SYSVDD_CONTROL                   0x4001
#define WM831X_THERMAL_MONITORING               0x4002
#define WM831X_POWER_STATE                      0x4003
#define WM831X_WATCHDOG                         0x4004
#define WM831X_ON_PIN_CONTROL                   0x4005
#define WM831X_RESET_CONTROL                    0x4006
#define WM831X_CONTROL_INTERFACE                0x4007
#define WM831X_SECURITY_KEY                     0x4008
#define WM831X_SOFTWARE_SCRATCH                 0x4009
#define WM831X_OTP_CONTROL                      0x400A
#define WM831X_GPIO_LEVEL                       0x400C
#define WM831X_SYSTEM_STATUS                    0x400D
#define WM831X_ON_SOURCE                        0x400E
#define WM831X_OFF_SOURCE                       0x400F
#define WM831X_SYSTEM_INTERRUPTS                0x4010
#define WM831X_INTERRUPT_STATUS_1               0x4011
#define WM831X_INTERRUPT_STATUS_2               0x4012
#define WM831X_INTERRUPT_STATUS_3               0x4013
#define WM831X_INTERRUPT_STATUS_4               0x4014
#define WM831X_INTERRUPT_STATUS_5               0x4015
#define WM831X_IRQ_CONFIG                       0x4017
#define WM831X_SYSTEM_INTERRUPTS_MASK           0x4018
#define WM831X_INTERRUPT_STATUS_1_MASK          0x4019
#define WM831X_INTERRUPT_STATUS_2_MASK          0x401A
#define WM831X_INTERRUPT_STATUS_3_MASK          0x401B
#define WM831X_INTERRUPT_STATUS_4_MASK          0x401C
#define WM831X_INTERRUPT_STATUS_5_MASK          0x401D
#define WM831X_RTC_WRITE_COUNTER                0x4020
#define WM831X_RTC_TIME_1                       0x4021
#define WM831X_RTC_TIME_2                       0x4022
#define WM831X_RTC_ALARM_1                      0x4023
#define WM831X_RTC_ALARM_2                      0x4024
#define WM831X_RTC_CONTROL                      0x4025
#define WM831X_RTC_TRIM                         0x4026
#define WM831X_TOUCH_CONTROL_1                  0x4028
#define WM831X_TOUCH_CONTROL_2                  0x4029
#define WM831X_TOUCH_DATA_X                     0x402A
#define WM831X_TOUCH_DATA_Y                     0x402B
#define WM831X_TOUCH_DATA_Z                     0x402C
#define WM831X_AUXADC_DATA                      0x402D
#define WM831X_AUXADC_CONTROL                   0x402E
#define WM831X_AUXADC_SOURCE                    0x402F
#define WM831X_COMPARATOR_CONTROL               0x4030
#define WM831X_COMPARATOR_1                     0x4031
#define WM831X_COMPARATOR_2                     0x4032
#define WM831X_COMPARATOR_3                     0x4033
#define WM831X_COMPARATOR_4                     0x4034
#define WM831X_GPIO1_CONTROL                    0x4038
#define WM831X_GPIO2_CONTROL                    0x4039
#define WM831X_GPIO3_CONTROL                    0x403A
#define WM831X_GPIO4_CONTROL                    0x403B
#define WM831X_GPIO5_CONTROL                    0x403C
#define WM831X_GPIO6_CONTROL                    0x403D
#define WM831X_GPIO7_CONTROL                    0x403E
#define WM831X_GPIO8_CONTROL                    0x403F
#define WM831X_GPIO9_CONTROL                    0x4040
#define WM831X_GPIO10_CONTROL                   0x4041
#define WM831X_GPIO11_CONTROL                   0x4042
#define WM831X_GPIO12_CONTROL                   0x4043
#define WM831X_GPIO13_CONTROL                   0x4044
#define WM831X_GPIO14_CONTROL                   0x4045
#define WM831X_GPIO15_CONTROL                   0x4046
#define WM831X_GPIO16_CONTROL                   0x4047
#define WM831X_CHARGER_CONTROL_1                0x4048
#define WM831X_CHARGER_CONTROL_2                0x4049
#define WM831X_CHARGER_STATUS                   0x404A
#define WM831X_BACKUP_CHARGER_CONTROL           0x404B
#define WM831X_STATUS_LED_1                     0x404C
#define WM831X_STATUS_LED_2                     0x404D
#define WM831X_CURRENT_SINK_1                   0x404E
#define WM831X_CURRENT_SINK_2                   0x404F
#define WM831X_DCDC_ENABLE                      0x4050
#define WM831X_LDO_ENABLE                       0x4051
#define WM831X_DCDC_STATUS                      0x4052
#define WM831X_LDO_STATUS                       0x4053
#define WM831X_DCDC_UV_STATUS                   0x4054
#define WM831X_LDO_UV_STATUS                    0x4055
#define WM831X_DC1_CONTROL_1                    0x4056
#define WM831X_DC1_CONTROL_2                    0x4057
#define WM831X_DC1_ON_CONFIG                    0x4058
#define WM831X_DC1_SLEEP_CONTROL                0x4059
#define WM831X_DC1_DVS_CONTROL                  0x405A
#define WM831X_DC2_CONTROL_1                    0x405B
#define WM831X_DC2_CONTROL_2                    0x405C
#define WM831X_DC2_ON_CONFIG                    0x405D
#define WM831X_DC2_SLEEP_CONTROL                0x405E
#define WM831X_DC2_DVS_CONTROL                  0x405F
#define WM831X_DC3_CONTROL_1                    0x4060
#define WM831X_DC3_CONTROL_2                    0x4061
#define WM831X_DC3_ON_CONFIG                    0x4062
#define WM831X_DC3_SLEEP_CONTROL                0x4063
#define WM831X_DC4_CONTROL                      0x4064
#define WM831X_DC4_SLEEP_CONTROL                0x4065
#define WM832X_DC4_SLEEP_CONTROL                0x4067
#define WM831X_EPE1_CONTROL                     0x4066
#define WM831X_EPE2_CONTROL                     0x4067
#define WM831X_LDO1_CONTROL                     0x4068
#define WM831X_LDO1_ON_CONTROL                  0x4069
#define WM831X_LDO1_SLEEP_CONTROL               0x406A
#define WM831X_LDO2_CONTROL                     0x406B
#define WM831X_LDO2_ON_CONTROL                  0x406C
#define WM831X_LDO2_SLEEP_CONTROL               0x406D
#define WM831X_LDO3_CONTROL                     0x406E
#define WM831X_LDO3_ON_CONTROL                  0x406F
#define WM831X_LDO3_SLEEP_CONTROL               0x4070
#define WM831X_LDO4_CONTROL                     0x4071
#define WM831X_LDO4_ON_CONTROL                  0x4072
#define WM831X_LDO4_SLEEP_CONTROL               0x4073
#define WM831X_LDO5_CONTROL                     0x4074
#define WM831X_LDO5_ON_CONTROL                  0x4075
#define WM831X_LDO5_SLEEP_CONTROL               0x4076
#define WM831X_LDO6_CONTROL                     0x4077
#define WM831X_LDO6_ON_CONTROL                  0x4078
#define WM831X_LDO6_SLEEP_CONTROL               0x4079
#define WM831X_LDO7_CONTROL                     0x407A
#define WM831X_LDO7_ON_CONTROL                  0x407B
#define WM831X_LDO7_SLEEP_CONTROL               0x407C
#define WM831X_LDO8_CONTROL                     0x407D
#define WM831X_LDO8_ON_CONTROL                  0x407E
#define WM831X_LDO8_SLEEP_CONTROL               0x407F
#define WM831X_LDO9_CONTROL                     0x4080
#define WM831X_LDO9_ON_CONTROL                  0x4081
#define WM831X_LDO9_SLEEP_CONTROL               0x4082
#define WM831X_LDO10_CONTROL                    0x4083
#define WM831X_LDO10_ON_CONTROL                 0x4084
#define WM831X_LDO10_SLEEP_CONTROL              0x4085
#define WM831X_LDO11_ON_CONTROL                 0x4087
#define WM831X_LDO11_SLEEP_CONTROL              0x4088
#define WM831X_POWER_GOOD_SOURCE_1              0x408E
#define WM831X_POWER_GOOD_SOURCE_2              0x408F
#define WM831X_CLOCK_CONTROL_1                  0x4090
#define WM831X_CLOCK_CONTROL_2                  0x4091
#define WM831X_FLL_CONTROL_1                    0x4092
#define WM831X_FLL_CONTROL_2                    0x4093
#define WM831X_FLL_CONTROL_3                    0x4094
#define WM831X_FLL_CONTROL_4                    0x4095
#define WM831X_FLL_CONTROL_5                    0x4096
#define WM831X_UNIQUE_ID_1                      0x7800
#define WM831X_UNIQUE_ID_2                      0x7801
#define WM831X_UNIQUE_ID_3                      0x7802
#define WM831X_UNIQUE_ID_4                      0x7803
#define WM831X_UNIQUE_ID_5                      0x7804
#define WM831X_UNIQUE_ID_6                      0x7805
#define WM831X_UNIQUE_ID_7                      0x7806
#define WM831X_UNIQUE_ID_8                      0x7807
#define WM831X_FACTORY_OTP_ID                   0x7808
#define WM831X_FACTORY_OTP_1                    0x7809
#define WM831X_FACTORY_OTP_2                    0x780A
#define WM831X_FACTORY_OTP_3                    0x780B
#define WM831X_FACTORY_OTP_4                    0x780C
#define WM831X_FACTORY_OTP_5                    0x780D
#define WM831X_CUSTOMER_OTP_ID                  0x7810
#define WM831X_DC1_OTP_CONTROL                  0x7811
#define WM831X_DC2_OTP_CONTROL                  0x7812
#define WM831X_DC3_OTP_CONTROL                  0x7813
#define WM831X_LDO1_2_OTP_CONTROL               0x7814
#define WM831X_LDO3_4_OTP_CONTROL               0x7815
#define WM831X_LDO5_6_OTP_CONTROL               0x7816
#define WM831X_LDO7_8_OTP_CONTROL               0x7817
#define WM831X_LDO9_10_OTP_CONTROL              0x7818
#define WM831X_LDO11_EPE_CONTROL                0x7819
#define WM831X_GPIO1_OTP_CONTROL                0x781A
#define WM831X_GPIO2_OTP_CONTROL                0x781B
#define WM831X_GPIO3_OTP_CONTROL                0x781C
#define WM831X_GPIO4_OTP_CONTROL                0x781D
#define WM831X_GPIO5_OTP_CONTROL                0x781E
#define WM831X_GPIO6_OTP_CONTROL                0x781F
#define WM831X_DBE_CHECK_DATA                   0x7827

/*
 * R0 (0x00) - Reset ID
 */
#define WM831X_CHIP_ID_MASK                     0xFFFF  /* CHIP_ID - [15:0] */
#define WM831X_CHIP_ID_SHIFT                         0  /* CHIP_ID - [15:0] */
#define WM831X_CHIP_ID_WIDTH                        16  /* CHIP_ID - [15:0] */

/*
 * R1 (0x01) - Revision
 */
#define WM831X_PARENT_REV_MASK                  0xFF00  /* PARENT_REV - [15:8] */
#define WM831X_PARENT_REV_SHIFT                      8  /* PARENT_REV - [15:8] */
#define WM831X_PARENT_REV_WIDTH                      8  /* PARENT_REV - [15:8] */
#define WM831X_CHILD_REV_MASK                   0x00FF  /* CHILD_REV - [7:0] */
#define WM831X_CHILD_REV_SHIFT                       0  /* CHILD_REV - [7:0] */
#define WM831X_CHILD_REV_WIDTH                       8  /* CHILD_REV - [7:0] */

/*
 * R16384 (0x4000) - Parent ID
 */
#define WM831X_PARENT_ID_MASK                   0xFFFF  /* PARENT_ID - [15:0] */
#define WM831X_PARENT_ID_SHIFT                       0  /* PARENT_ID - [15:0] */
#define WM831X_PARENT_ID_WIDTH                      16  /* PARENT_ID - [15:0] */

/*
 * R16389 (0x4005) - ON Pin Control
 */
#define WM831X_ON_PIN_SECACT_MASK               0x0300  /* ON_PIN_SECACT - [9:8] */
#define WM831X_ON_PIN_SECACT_SHIFT                   8  /* ON_PIN_SECACT - [9:8] */
#define WM831X_ON_PIN_SECACT_WIDTH                   2  /* ON_PIN_SECACT - [9:8] */
#define WM831X_ON_PIN_PRIMACT_MASK              0x0030  /* ON_PIN_PRIMACT - [5:4] */
#define WM831X_ON_PIN_PRIMACT_SHIFT                  4  /* ON_PIN_PRIMACT - [5:4] */
#define WM831X_ON_PIN_PRIMACT_WIDTH                  2  /* ON_PIN_PRIMACT - [5:4] */
#define WM831X_ON_PIN_STS                       0x0008  /* ON_PIN_STS */
#define WM831X_ON_PIN_STS_MASK                  0x0008  /* ON_PIN_STS */
#define WM831X_ON_PIN_STS_SHIFT                      3  /* ON_PIN_STS */
#define WM831X_ON_PIN_STS_WIDTH                      1  /* ON_PIN_STS */
#define WM831X_ON_PIN_TO_MASK                   0x0003  /* ON_PIN_TO - [1:0] */
#define WM831X_ON_PIN_TO_SHIFT                       0  /* ON_PIN_TO - [1:0] */
#define WM831X_ON_PIN_TO_WIDTH                       2  /* ON_PIN_TO - [1:0] */

struct regulator_dev;

#define WM831X_NUM_IRQ_REGS 5

enum wm831x_parent {
	WM8310 = 0x8310,
	WM8311 = 0x8311,
	WM8312 = 0x8312,
	WM8320 = 0x8320,
	WM8321 = 0x8321,
	WM8325 = 0x8325,
	WM8326 = 0x8326,
};

struct wm831x {
	struct mutex io_lock;

	struct device *dev;
	int (*read_dev)(struct wm831x *wm831x, unsigned short reg,
			int bytes, void *dest);
	int (*write_dev)(struct wm831x *wm831x, unsigned short reg,
			 int bytes, void *src);

	void *control_data;

	int irq;  /* Our chip IRQ */
	struct mutex irq_lock;
	unsigned int irq_base;
	int irq_masks_cur[WM831X_NUM_IRQ_REGS];   /* Currently active value */
	int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */

	/* Chip revision based flags */
	unsigned has_gpio_ena:1;         /* Has GPIO enable bit */
	unsigned has_cs_sts:1;           /* Has current sink status bit */
	unsigned charger_irq_wake:1;     /* Are charger IRQs a wake source? */

	int num_gpio;

	struct mutex auxadc_lock;
	struct completion auxadc_done;

	/* The WM831x has a security key blocking access to certain
	 * registers.  The mutex is taken by the accessors for locking
	 * and unlocking the security key, locked is used to fail
	 * writes if the lock is held.
	 */
	struct mutex key_lock;
	unsigned int locked:1;
};

/* Device I/O API */
int wm831x_reg_read(struct wm831x *wm831x, unsigned short reg);
int wm831x_reg_write(struct wm831x *wm831x, unsigned short reg,
		 unsigned short val);
void wm831x_reg_lock(struct wm831x *wm831x);
int wm831x_reg_unlock(struct wm831x *wm831x);
int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg,
		    unsigned short mask, unsigned short val);
int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
		     int count, u16 *buf);

int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq);
void wm831x_device_exit(struct wm831x *wm831x);
int wm831x_device_suspend(struct wm831x *wm831x);
int wm831x_irq_init(struct wm831x *wm831x, int irq);
void wm831x_irq_exit(struct wm831x *wm831x);

#endif
Commit	Line	Data
d2bedfe7 MB	1	/*
	2	* include/linux/mfd/wm831x/core.h -- Core interface for WM831x
	3	*
	4	* Copyright 2009 Wolfson Microelectronics PLC.
	5	*
	6	* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	*/
	14
	15	#ifndef __MFD_WM831X_CORE_H__
	16	#define __MFD_WM831X_CORE_H__
	17
473fe736	18	#include <linux/completion.h>
7d4d0a3e	19	#include <linux/interrupt.h>
7d4d0a3e	20
d2bedfe7 MB	21	/*
	22	* Register values.
	23	*/
	24	#define WM831X_RESET_ID 0x00
	25	#define WM831X_REVISION 0x01
	26	#define WM831X_PARENT_ID 0x4000
	27	#define WM831X_SYSVDD_CONTROL 0x4001
	28	#define WM831X_THERMAL_MONITORING 0x4002
	29	#define WM831X_POWER_STATE 0x4003
	30	#define WM831X_WATCHDOG 0x4004
	31	#define WM831X_ON_PIN_CONTROL 0x4005
	32	#define WM831X_RESET_CONTROL 0x4006
	33	#define WM831X_CONTROL_INTERFACE 0x4007
	34	#define WM831X_SECURITY_KEY 0x4008
	35	#define WM831X_SOFTWARE_SCRATCH 0x4009
	36	#define WM831X_OTP_CONTROL 0x400A
	37	#define WM831X_GPIO_LEVEL 0x400C
	38	#define WM831X_SYSTEM_STATUS 0x400D
	39	#define WM831X_ON_SOURCE 0x400E
	40	#define WM831X_OFF_SOURCE 0x400F
	41	#define WM831X_SYSTEM_INTERRUPTS 0x4010
	42	#define WM831X_INTERRUPT_STATUS_1 0x4011
	43	#define WM831X_INTERRUPT_STATUS_2 0x4012
	44	#define WM831X_INTERRUPT_STATUS_3 0x4013
	45	#define WM831X_INTERRUPT_STATUS_4 0x4014
	46	#define WM831X_INTERRUPT_STATUS_5 0x4015
	47	#define WM831X_IRQ_CONFIG 0x4017
	48	#define WM831X_SYSTEM_INTERRUPTS_MASK 0x4018
	49	#define WM831X_INTERRUPT_STATUS_1_MASK 0x4019
	50	#define WM831X_INTERRUPT_STATUS_2_MASK 0x401A
	51	#define WM831X_INTERRUPT_STATUS_3_MASK 0x401B
	52	#define WM831X_INTERRUPT_STATUS_4_MASK 0x401C
	53	#define WM831X_INTERRUPT_STATUS_5_MASK 0x401D
	54	#define WM831X_RTC_WRITE_COUNTER 0x4020
	55	#define WM831X_RTC_TIME_1 0x4021
	56	#define WM831X_RTC_TIME_2 0x4022
	57	#define WM831X_RTC_ALARM_1 0x4023
	58	#define WM831X_RTC_ALARM_2 0x4024
	59	#define WM831X_RTC_CONTROL 0x4025
	60	#define WM831X_RTC_TRIM 0x4026
	61	#define WM831X_TOUCH_CONTROL_1 0x4028
	62	#define WM831X_TOUCH_CONTROL_2 0x4029
	63	#define WM831X_TOUCH_DATA_X 0x402A
	64	#define WM831X_TOUCH_DATA_Y 0x402B
	65	#define WM831X_TOUCH_DATA_Z 0x402C
	66	#define WM831X_AUXADC_DATA 0x402D
	67	#define WM831X_AUXADC_CONTROL 0x402E
	68	#define WM831X_AUXADC_SOURCE 0x402F
	69	#define WM831X_COMPARATOR_CONTROL 0x4030
	70	#define WM831X_COMPARATOR_1 0x4031
	71	#define WM831X_COMPARATOR_2 0x4032
	72	#define WM831X_COMPARATOR_3 0x4033
	73	#define WM831X_COMPARATOR_4 0x4034
	74	#define WM831X_GPIO1_CONTROL 0x4038
	75	#define WM831X_GPIO2_CONTROL 0x4039
	76	#define WM831X_GPIO3_CONTROL 0x403A
	77	#define WM831X_GPIO4_CONTROL 0x403B
	78	#define WM831X_GPIO5_CONTROL 0x403C
	79	#define WM831X_GPIO6_CONTROL 0x403D
	80	#define WM831X_GPIO7_CONTROL 0x403E
	81	#define WM831X_GPIO8_CONTROL 0x403F
	82	#define WM831X_GPIO9_CONTROL 0x4040
	83	#define WM831X_GPIO10_CONTROL 0x4041
	84	#define WM831X_GPIO11_CONTROL 0x4042
85	#define WM831X_GPIO12_CONTROL 0x4043
86	#define WM831X_GPIO13_CONTROL 0x4044
87	#define WM831X_GPIO14_CONTROL 0x4045
88	#define WM831X_GPIO15_CONTROL 0x4046
89	#define WM831X_GPIO16_CONTROL 0x4047
90	#define WM831X_CHARGER_CONTROL_1 0x4048
91	#define WM831X_CHARGER_CONTROL_2 0x4049
92	#define WM831X_CHARGER_STATUS 0x404A
93	#define WM831X_BACKUP_CHARGER_CONTROL 0x404B
94	#define WM831X_STATUS_LED_1 0x404C
95	#define WM831X_STATUS_LED_2 0x404D
96	#define WM831X_CURRENT_SINK_1 0x404E
97	#define WM831X_CURRENT_SINK_2 0x404F
98	#define WM831X_DCDC_ENABLE 0x4050
99	#define WM831X_LDO_ENABLE 0x4051
100	#define WM831X_DCDC_STATUS 0x4052
101	#define WM831X_LDO_STATUS 0x4053
102	#define WM831X_DCDC_UV_STATUS 0x4054
103	#define WM831X_LDO_UV_STATUS 0x4055
104	#define WM831X_DC1_CONTROL_1 0x4056
105	#define WM831X_DC1_CONTROL_2 0x4057
106	#define WM831X_DC1_ON_CONFIG 0x4058
107	#define WM831X_DC1_SLEEP_CONTROL 0x4059
108	#define WM831X_DC1_DVS_CONTROL 0x405A
109	#define WM831X_DC2_CONTROL_1 0x405B
110	#define WM831X_DC2_CONTROL_2 0x405C
111	#define WM831X_DC2_ON_CONFIG 0x405D
112	#define WM831X_DC2_SLEEP_CONTROL 0x405E
113	#define WM831X_DC2_DVS_CONTROL 0x405F
114	#define WM831X_DC3_CONTROL_1 0x4060
115	#define WM831X_DC3_CONTROL_2 0x4061
116	#define WM831X_DC3_ON_CONFIG 0x4062
117	#define WM831X_DC3_SLEEP_CONTROL 0x4063
118	#define WM831X_DC4_CONTROL 0x4064
119	#define WM831X_DC4_SLEEP_CONTROL 0x4065
d4e0a89e	120	#define WM832X_DC4_SLEEP_CONTROL 0x4067
d2bedfe7 MB	121	#define WM831X_EPE1_CONTROL 0x4066
	122	#define WM831X_EPE2_CONTROL 0x4067
	123	#define WM831X_LDO1_CONTROL 0x4068
	124	#define WM831X_LDO1_ON_CONTROL 0x4069
	125	#define WM831X_LDO1_SLEEP_CONTROL 0x406A
	126	#define WM831X_LDO2_CONTROL 0x406B
	127	#define WM831X_LDO2_ON_CONTROL 0x406C
	128	#define WM831X_LDO2_SLEEP_CONTROL 0x406D
	129	#define WM831X_LDO3_CONTROL 0x406E
	130	#define WM831X_LDO3_ON_CONTROL 0x406F
	131	#define WM831X_LDO3_SLEEP_CONTROL 0x4070
	132	#define WM831X_LDO4_CONTROL 0x4071
	133	#define WM831X_LDO4_ON_CONTROL 0x4072
	134	#define WM831X_LDO4_SLEEP_CONTROL 0x4073
	135	#define WM831X_LDO5_CONTROL 0x4074
	136	#define WM831X_LDO5_ON_CONTROL 0x4075
	137	#define WM831X_LDO5_SLEEP_CONTROL 0x4076
	138	#define WM831X_LDO6_CONTROL 0x4077
	139	#define WM831X_LDO6_ON_CONTROL 0x4078
	140	#define WM831X_LDO6_SLEEP_CONTROL 0x4079
	141	#define WM831X_LDO7_CONTROL 0x407A
	142	#define WM831X_LDO7_ON_CONTROL 0x407B
	143	#define WM831X_LDO7_SLEEP_CONTROL 0x407C
	144	#define WM831X_LDO8_CONTROL 0x407D
	145	#define WM831X_LDO8_ON_CONTROL 0x407E
	146	#define WM831X_LDO8_SLEEP_CONTROL 0x407F
	147	#define WM831X_LDO9_CONTROL 0x4080
	148	#define WM831X_LDO9_ON_CONTROL 0x4081
	149	#define WM831X_LDO9_SLEEP_CONTROL 0x4082
	150	#define WM831X_LDO10_CONTROL 0x4083
	151	#define WM831X_LDO10_ON_CONTROL 0x4084
	152	#define WM831X_LDO10_SLEEP_CONTROL 0x4085
	153	#define WM831X_LDO11_ON_CONTROL 0x4087
	154	#define WM831X_LDO11_SLEEP_CONTROL 0x4088
	155	#define WM831X_POWER_GOOD_SOURCE_1 0x408E
	156	#define WM831X_POWER_GOOD_SOURCE_2 0x408F
	157	#define WM831X_CLOCK_CONTROL_1 0x4090
	158	#define WM831X_CLOCK_CONTROL_2 0x4091
	159	#define WM831X_FLL_CONTROL_1 0x4092
	160	#define WM831X_FLL_CONTROL_2 0x4093
	161	#define WM831X_FLL_CONTROL_3 0x4094
	162	#define WM831X_FLL_CONTROL_4 0x4095
	163	#define WM831X_FLL_CONTROL_5 0x4096
	164	#define WM831X_UNIQUE_ID_1 0x7800
	165	#define WM831X_UNIQUE_ID_2 0x7801
	166	#define WM831X_UNIQUE_ID_3 0x7802
	167	#define WM831X_UNIQUE_ID_4 0x7803
	168	#define WM831X_UNIQUE_ID_5 0x7804
	169	#define WM831X_UNIQUE_ID_6 0x7805
	170	#define WM831X_UNIQUE_ID_7 0x7806
	171	#define WM831X_UNIQUE_ID_8 0x7807
	172	#define WM831X_FACTORY_OTP_ID 0x7808
	173	#define WM831X_FACTORY_OTP_1 0x7809
	174	#define WM831X_FACTORY_OTP_2 0x780A
	175	#define WM831X_FACTORY_OTP_3 0x780B
	176	#define WM831X_FACTORY_OTP_4 0x780C
	177	#define WM831X_FACTORY_OTP_5 0x780D
	178	#define WM831X_CUSTOMER_OTP_ID 0x7810
	179	#define WM831X_DC1_OTP_CONTROL 0x7811
	180	#define WM831X_DC2_OTP_CONTROL 0x7812
	181	#define WM831X_DC3_OTP_CONTROL 0x7813
	182	#define WM831X_LDO1_2_OTP_CONTROL 0x7814
	183	#define WM831X_LDO3_4_OTP_CONTROL 0x7815
	184	#define WM831X_LDO5_6_OTP_CONTROL 0x7816
185	#define WM831X_LDO7_8_OTP_CONTROL 0x7817
186	#define WM831X_LDO9_10_OTP_CONTROL 0x7818
187	#define WM831X_LDO11_EPE_CONTROL 0x7819
188	#define WM831X_GPIO1_OTP_CONTROL 0x781A
189	#define WM831X_GPIO2_OTP_CONTROL 0x781B
190	#define WM831X_GPIO3_OTP_CONTROL 0x781C
191	#define WM831X_GPIO4_OTP_CONTROL 0x781D
192	#define WM831X_GPIO5_OTP_CONTROL 0x781E
193	#define WM831X_GPIO6_OTP_CONTROL 0x781F
194	#define WM831X_DBE_CHECK_DATA 0x7827
195
196	/*
197	* R0 (0x00) - Reset ID
198	*/
199	#define WM831X_CHIP_ID_MASK 0xFFFF /* CHIP_ID - [15:0] */
200	#define WM831X_CHIP_ID_SHIFT 0 /* CHIP_ID - [15:0] */
201	#define WM831X_CHIP_ID_WIDTH 16 /* CHIP_ID - [15:0] */
202
203	/*
204	* R1 (0x01) - Revision
205	*/
206	#define WM831X_PARENT_REV_MASK 0xFF00 /* PARENT_REV - [15:8] */
207	#define WM831X_PARENT_REV_SHIFT 8 /* PARENT_REV - [15:8] */
208	#define WM831X_PARENT_REV_WIDTH 8 /* PARENT_REV - [15:8] */
209	#define WM831X_CHILD_REV_MASK 0x00FF /* CHILD_REV - [7:0] */
210	#define WM831X_CHILD_REV_SHIFT 0 /* CHILD_REV - [7:0] */
211	#define WM831X_CHILD_REV_WIDTH 8 /* CHILD_REV - [7:0] */
212
213	/*
214	* R16384 (0x4000) - Parent ID
215	*/
216	#define WM831X_PARENT_ID_MASK 0xFFFF /* PARENT_ID - [15:0] */
217	#define WM831X_PARENT_ID_SHIFT 0 /* PARENT_ID - [15:0] */
218	#define WM831X_PARENT_ID_WIDTH 16 /* PARENT_ID - [15:0] */
219
0c73b992 MB	220	/*
	221	* R16389 (0x4005) - ON Pin Control
	222	*/
	223	#define WM831X_ON_PIN_SECACT_MASK 0x0300 /* ON_PIN_SECACT - [9:8] */
	224	#define WM831X_ON_PIN_SECACT_SHIFT 8 /* ON_PIN_SECACT - [9:8] */
	225	#define WM831X_ON_PIN_SECACT_WIDTH 2 /* ON_PIN_SECACT - [9:8] */
	226	#define WM831X_ON_PIN_PRIMACT_MASK 0x0030 /* ON_PIN_PRIMACT - [5:4] */
	227	#define WM831X_ON_PIN_PRIMACT_SHIFT 4 /* ON_PIN_PRIMACT - [5:4] */
	228	#define WM831X_ON_PIN_PRIMACT_WIDTH 2 /* ON_PIN_PRIMACT - [5:4] */
	229	#define WM831X_ON_PIN_STS 0x0008 /* ON_PIN_STS */
	230	#define WM831X_ON_PIN_STS_MASK 0x0008 /* ON_PIN_STS */
	231	#define WM831X_ON_PIN_STS_SHIFT 3 /* ON_PIN_STS */
	232	#define WM831X_ON_PIN_STS_WIDTH 1 /* ON_PIN_STS */
	233	#define WM831X_ON_PIN_TO_MASK 0x0003 /* ON_PIN_TO - [1:0] */
	234	#define WM831X_ON_PIN_TO_SHIFT 0 /* ON_PIN_TO - [1:0] */
	235	#define WM831X_ON_PIN_TO_WIDTH 2 /* ON_PIN_TO - [1:0] */
	236
	237	struct regulator_dev;
	238
5fb4d38b MB	239	#define WM831X_NUM_IRQ_REGS 5
5fb4d38b MB	240
e5b48684 MB	241	enum wm831x_parent {
	242	WM8310 = 0x8310,
	243	WM8311 = 0x8311,
	244	WM8312 = 0x8312,
	245	WM8320 = 0x8320,
	246	WM8321 = 0x8321,
	247	WM8325 = 0x8325,
412dc11d	248	WM8326 = 0x8326,
e5b48684 MB	249	};
e5b48684 MB	250
d2bedfe7 MB	251	struct wm831x {
	252	struct mutex io_lock;
	253
	254	struct device *dev;
	255	int (read_dev)(struct wm831x wm831x, unsigned short reg,
	256	int bytes, void *dest);
	257	int (write_dev)(struct wm831x wm831x, unsigned short reg,
	258	int bytes, void *src);
	259
	260	void *control_data;
	261
7d4d0a3e MB	262	int irq; /* Our chip IRQ */
7d4d0a3e MB	263	struct mutex irq_lock;
7d4d0a3e	264	unsigned int irq_base;
5fb4d38b MB	265	int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */
5fb4d38b MB	266	int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */
7d4d0a3e	267
f92e8f81	268	/* Chip revision based flags */
b03b4d7c MB	269	unsigned has_gpio_ena:1; /* Has GPIO enable bit */
	270	unsigned has_cs_sts:1; /* Has current sink status bit */
	271	unsigned charger_irq_wake:1; /* Are charger IRQs a wake source? */
f92e8f81	272
6f2ecaae MB	273	int num_gpio;
6f2ecaae MB	274
7e9f9fd4	275	struct mutex auxadc_lock;
473fe736	276	struct completion auxadc_done;
7e9f9fd4	277
d2bedfe7 MB	278	/* The WM831x has a security key blocking access to certain
	279	* registers. The mutex is taken by the accessors for locking
	280	* and unlocking the security key, locked is used to fail
	281	* writes if the lock is held.
	282	*/
	283	struct mutex key_lock;
	284	unsigned int locked:1;
	285	};
	286
	287	/* Device I/O API */
	288	int wm831x_reg_read(struct wm831x *wm831x, unsigned short reg);
	289	int wm831x_reg_write(struct wm831x *wm831x, unsigned short reg,
	290	unsigned short val);
	291	void wm831x_reg_lock(struct wm831x *wm831x);
	292	int wm831x_reg_unlock(struct wm831x *wm831x);
	293	int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg,
	294	unsigned short mask, unsigned short val);
	295	int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
	296	int count, u16 *buf);
	297
e5b48684 MB	298	int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq);
	299	void wm831x_device_exit(struct wm831x *wm831x);
	300	int wm831x_device_suspend(struct wm831x *wm831x);
7d4d0a3e MB	301	int wm831x_irq_init(struct wm831x *wm831x, int irq);
	302	void wm831x_irq_exit(struct wm831x *wm831x);
	303
d2bedfe7	304	#endif