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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX4_DEVICE_H | |
34 | #define MLX4_DEVICE_H | |
35 | ||
574e2af7 | 36 | #include <linux/if_ether.h> |
225c7b1f RD |
37 | #include <linux/pci.h> |
38 | #include <linux/completion.h> | |
39 | #include <linux/radix-tree.h> | |
d9236c3f | 40 | #include <linux/cpu_rmap.h> |
225c7b1f | 41 | |
60063497 | 42 | #include <linux/atomic.h> |
225c7b1f | 43 | |
ec693d47 AV |
44 | #include <linux/clocksource.h> |
45 | ||
0b7ca5a9 YP |
46 | #define MAX_MSIX_P_PORT 17 |
47 | #define MAX_MSIX 64 | |
48 | #define MSIX_LEGACY_SZ 4 | |
49 | #define MIN_MSIX_P_PORT 5 | |
50 | ||
225c7b1f RD |
51 | enum { |
52 | MLX4_FLAG_MSI_X = 1 << 0, | |
5ae2a7a8 | 53 | MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, |
623ed84b JM |
54 | MLX4_FLAG_MASTER = 1 << 2, |
55 | MLX4_FLAG_SLAVE = 1 << 3, | |
56 | MLX4_FLAG_SRIOV = 1 << 4, | |
acddd5dd | 57 | MLX4_FLAG_OLD_REG_MAC = 1 << 6, |
225c7b1f RD |
58 | }; |
59 | ||
efcd235d JM |
60 | enum { |
61 | MLX4_PORT_CAP_IS_SM = 1 << 1, | |
62 | MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, | |
63 | }; | |
64 | ||
225c7b1f | 65 | enum { |
fc06573d JM |
66 | MLX4_MAX_PORTS = 2, |
67 | MLX4_MAX_PORT_PKEYS = 128 | |
225c7b1f RD |
68 | }; |
69 | ||
396f2feb JM |
70 | /* base qkey for use in sriov tunnel-qp/proxy-qp communication. |
71 | * These qkeys must not be allowed for general use. This is a 64k range, | |
72 | * and to test for violation, we use the mask (protect against future chg). | |
73 | */ | |
74 | #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) | |
75 | #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) | |
76 | ||
cd9281d8 JM |
77 | enum { |
78 | MLX4_BOARD_ID_LEN = 64 | |
79 | }; | |
80 | ||
623ed84b JM |
81 | enum { |
82 | MLX4_MAX_NUM_PF = 16, | |
83 | MLX4_MAX_NUM_VF = 64, | |
84 | MLX4_MFUNC_MAX = 80, | |
3fc929e2 | 85 | MLX4_MAX_EQ_NUM = 1024, |
623ed84b JM |
86 | MLX4_MFUNC_EQ_NUM = 4, |
87 | MLX4_MFUNC_MAX_EQES = 8, | |
88 | MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) | |
89 | }; | |
90 | ||
0ff1fb65 HHZ |
91 | /* Driver supports 3 diffrent device methods to manage traffic steering: |
92 | * -device managed - High level API for ib and eth flow steering. FW is | |
93 | * managing flow steering tables. | |
c96d97f4 HHZ |
94 | * - B0 steering mode - Common low level API for ib and (if supported) eth. |
95 | * - A0 steering mode - Limited low level API for eth. In case of IB, | |
96 | * B0 mode is in use. | |
97 | */ | |
98 | enum { | |
99 | MLX4_STEERING_MODE_A0, | |
0ff1fb65 HHZ |
100 | MLX4_STEERING_MODE_B0, |
101 | MLX4_STEERING_MODE_DEVICE_MANAGED | |
c96d97f4 HHZ |
102 | }; |
103 | ||
104 | static inline const char *mlx4_steering_mode_str(int steering_mode) | |
105 | { | |
106 | switch (steering_mode) { | |
107 | case MLX4_STEERING_MODE_A0: | |
108 | return "A0 steering"; | |
109 | ||
110 | case MLX4_STEERING_MODE_B0: | |
111 | return "B0 steering"; | |
0ff1fb65 HHZ |
112 | |
113 | case MLX4_STEERING_MODE_DEVICE_MANAGED: | |
114 | return "Device managed flow steering"; | |
115 | ||
c96d97f4 HHZ |
116 | default: |
117 | return "Unrecognize steering mode"; | |
118 | } | |
119 | } | |
120 | ||
225c7b1f | 121 | enum { |
52eafc68 OG |
122 | MLX4_DEV_CAP_FLAG_RC = 1LL << 0, |
123 | MLX4_DEV_CAP_FLAG_UC = 1LL << 1, | |
124 | MLX4_DEV_CAP_FLAG_UD = 1LL << 2, | |
012a8ff5 | 125 | MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, |
52eafc68 OG |
126 | MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, |
127 | MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, | |
128 | MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, | |
129 | MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, | |
130 | MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, | |
131 | MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, | |
132 | MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, | |
133 | MLX4_DEV_CAP_FLAG_APM = 1LL << 17, | |
134 | MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, | |
135 | MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, | |
136 | MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, | |
137 | MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, | |
ccf86321 OG |
138 | MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, |
139 | MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, | |
f3a9d1f2 | 140 | MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, |
559a9f1d OD |
141 | MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, |
142 | MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, | |
ccf86321 OG |
143 | MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, |
144 | MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, | |
f2a3f6a3 | 145 | MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, |
58a60168 | 146 | MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, |
540b3a39 | 147 | MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, |
00f5ce99 JM |
148 | MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, |
149 | MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, | |
08ff3235 OG |
150 | MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, |
151 | MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 | |
225c7b1f RD |
152 | }; |
153 | ||
b3416f44 SP |
154 | enum { |
155 | MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, | |
156 | MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, | |
0ff1fb65 | 157 | MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, |
955154fa | 158 | MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, |
5930e8d0 | 159 | MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, |
3f7fb021 | 160 | MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, |
e6b6a231 | 161 | MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, |
b01978ca JM |
162 | MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, |
163 | MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8 | |
b3416f44 SP |
164 | }; |
165 | ||
08ff3235 OG |
166 | enum { |
167 | MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, | |
168 | MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1 | |
169 | }; | |
170 | ||
171 | enum { | |
172 | MLX4_USER_DEV_CAP_64B_CQE = 1L << 0 | |
173 | }; | |
174 | ||
175 | enum { | |
176 | MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0 | |
177 | }; | |
178 | ||
179 | ||
97285b78 MA |
180 | #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) |
181 | ||
95d04f07 | 182 | enum { |
804d6a89 | 183 | MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, |
95d04f07 RD |
184 | MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, |
185 | MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, | |
186 | MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, | |
187 | MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, | |
188 | MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, | |
189 | }; | |
190 | ||
225c7b1f RD |
191 | enum mlx4_event { |
192 | MLX4_EVENT_TYPE_COMP = 0x00, | |
193 | MLX4_EVENT_TYPE_PATH_MIG = 0x01, | |
194 | MLX4_EVENT_TYPE_COMM_EST = 0x02, | |
195 | MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, | |
196 | MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, | |
197 | MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, | |
198 | MLX4_EVENT_TYPE_CQ_ERROR = 0x04, | |
199 | MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
200 | MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, | |
201 | MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, | |
202 | MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | |
203 | MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | |
204 | MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | |
205 | MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, | |
206 | MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, | |
207 | MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, | |
208 | MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, | |
623ed84b JM |
209 | MLX4_EVENT_TYPE_CMD = 0x0a, |
210 | MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, | |
211 | MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, | |
fe6f700d | 212 | MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, |
5984be90 | 213 | MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, |
623ed84b | 214 | MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, |
00f5ce99 | 215 | MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, |
623ed84b | 216 | MLX4_EVENT_TYPE_NONE = 0xff, |
225c7b1f RD |
217 | }; |
218 | ||
219 | enum { | |
220 | MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, | |
221 | MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 | |
222 | }; | |
223 | ||
5984be90 JM |
224 | enum { |
225 | MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, | |
226 | }; | |
227 | ||
993c401e JM |
228 | enum slave_port_state { |
229 | SLAVE_PORT_DOWN = 0, | |
230 | SLAVE_PENDING_UP, | |
231 | SLAVE_PORT_UP, | |
232 | }; | |
233 | ||
234 | enum slave_port_gen_event { | |
235 | SLAVE_PORT_GEN_EVENT_DOWN = 0, | |
236 | SLAVE_PORT_GEN_EVENT_UP, | |
237 | SLAVE_PORT_GEN_EVENT_NONE, | |
238 | }; | |
239 | ||
240 | enum slave_port_state_event { | |
241 | MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, | |
242 | MLX4_PORT_STATE_DEV_EVENT_PORT_UP, | |
243 | MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, | |
244 | MLX4_PORT_STATE_IB_EVENT_GID_INVALID, | |
245 | }; | |
246 | ||
225c7b1f RD |
247 | enum { |
248 | MLX4_PERM_LOCAL_READ = 1 << 10, | |
249 | MLX4_PERM_LOCAL_WRITE = 1 << 11, | |
250 | MLX4_PERM_REMOTE_READ = 1 << 12, | |
251 | MLX4_PERM_REMOTE_WRITE = 1 << 13, | |
804d6a89 SM |
252 | MLX4_PERM_ATOMIC = 1 << 14, |
253 | MLX4_PERM_BIND_MW = 1 << 15, | |
225c7b1f RD |
254 | }; |
255 | ||
256 | enum { | |
257 | MLX4_OPCODE_NOP = 0x00, | |
258 | MLX4_OPCODE_SEND_INVAL = 0x01, | |
259 | MLX4_OPCODE_RDMA_WRITE = 0x08, | |
260 | MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, | |
261 | MLX4_OPCODE_SEND = 0x0a, | |
262 | MLX4_OPCODE_SEND_IMM = 0x0b, | |
263 | MLX4_OPCODE_LSO = 0x0e, | |
264 | MLX4_OPCODE_RDMA_READ = 0x10, | |
265 | MLX4_OPCODE_ATOMIC_CS = 0x11, | |
266 | MLX4_OPCODE_ATOMIC_FA = 0x12, | |
6fa8f719 VS |
267 | MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, |
268 | MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, | |
225c7b1f RD |
269 | MLX4_OPCODE_BIND_MW = 0x18, |
270 | MLX4_OPCODE_FMR = 0x19, | |
271 | MLX4_OPCODE_LOCAL_INVAL = 0x1b, | |
272 | MLX4_OPCODE_CONFIG_CMD = 0x1f, | |
273 | ||
274 | MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, | |
275 | MLX4_RECV_OPCODE_SEND = 0x01, | |
276 | MLX4_RECV_OPCODE_SEND_IMM = 0x02, | |
277 | MLX4_RECV_OPCODE_SEND_INVAL = 0x03, | |
278 | ||
279 | MLX4_CQE_OPCODE_ERROR = 0x1e, | |
280 | MLX4_CQE_OPCODE_RESIZE = 0x16, | |
281 | }; | |
282 | ||
283 | enum { | |
284 | MLX4_STAT_RATE_OFFSET = 5 | |
285 | }; | |
286 | ||
da995a8a | 287 | enum mlx4_protocol { |
0345584e YP |
288 | MLX4_PROT_IB_IPV6 = 0, |
289 | MLX4_PROT_ETH, | |
290 | MLX4_PROT_IB_IPV4, | |
291 | MLX4_PROT_FCOE | |
da995a8a AS |
292 | }; |
293 | ||
29bdc883 VS |
294 | enum { |
295 | MLX4_MTT_FLAG_PRESENT = 1 | |
296 | }; | |
297 | ||
93fc9e1b YP |
298 | enum mlx4_qp_region { |
299 | MLX4_QP_REGION_FW = 0, | |
300 | MLX4_QP_REGION_ETH_ADDR, | |
301 | MLX4_QP_REGION_FC_ADDR, | |
302 | MLX4_QP_REGION_FC_EXCH, | |
303 | MLX4_NUM_QP_REGION | |
304 | }; | |
305 | ||
7ff93f8b | 306 | enum mlx4_port_type { |
623ed84b | 307 | MLX4_PORT_TYPE_NONE = 0, |
27bf91d6 YP |
308 | MLX4_PORT_TYPE_IB = 1, |
309 | MLX4_PORT_TYPE_ETH = 2, | |
310 | MLX4_PORT_TYPE_AUTO = 3 | |
7ff93f8b YP |
311 | }; |
312 | ||
2a2336f8 YP |
313 | enum mlx4_special_vlan_idx { |
314 | MLX4_NO_VLAN_IDX = 0, | |
315 | MLX4_VLAN_MISS_IDX, | |
316 | MLX4_VLAN_REGULAR | |
317 | }; | |
318 | ||
0345584e YP |
319 | enum mlx4_steer_type { |
320 | MLX4_MC_STEER = 0, | |
321 | MLX4_UC_STEER, | |
322 | MLX4_NUM_STEERS | |
323 | }; | |
324 | ||
93fc9e1b YP |
325 | enum { |
326 | MLX4_NUM_FEXCH = 64 * 1024, | |
327 | }; | |
328 | ||
5a0fd094 EC |
329 | enum { |
330 | MLX4_MAX_FAST_REG_PAGES = 511, | |
331 | }; | |
332 | ||
00f5ce99 JM |
333 | enum { |
334 | MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, | |
335 | MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, | |
336 | MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, | |
337 | }; | |
338 | ||
339 | /* Port mgmt change event handling */ | |
340 | enum { | |
341 | MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, | |
342 | MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, | |
343 | MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, | |
344 | MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, | |
345 | MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, | |
346 | }; | |
347 | ||
348 | #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ | |
349 | MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) | |
350 | ||
ea54b10c JM |
351 | static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) |
352 | { | |
353 | return (major << 32) | (minor << 16) | subminor; | |
354 | } | |
355 | ||
3fc929e2 | 356 | struct mlx4_phys_caps { |
6634961c JM |
357 | u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; |
358 | u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; | |
3fc929e2 | 359 | u32 num_phys_eqs; |
47605df9 JM |
360 | u32 base_sqpn; |
361 | u32 base_proxy_sqpn; | |
362 | u32 base_tunnel_sqpn; | |
3fc929e2 MA |
363 | }; |
364 | ||
225c7b1f RD |
365 | struct mlx4_caps { |
366 | u64 fw_ver; | |
623ed84b | 367 | u32 function; |
225c7b1f | 368 | int num_ports; |
5ae2a7a8 | 369 | int vl_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 | 370 | int ib_mtu_cap[MLX4_MAX_PORTS + 1]; |
9a5aa622 | 371 | __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 YP |
372 | u64 def_mac[MLX4_MAX_PORTS + 1]; |
373 | int eth_mtu_cap[MLX4_MAX_PORTS + 1]; | |
5ae2a7a8 RD |
374 | int gid_table_len[MLX4_MAX_PORTS + 1]; |
375 | int pkey_table_len[MLX4_MAX_PORTS + 1]; | |
7699517d YP |
376 | int trans_type[MLX4_MAX_PORTS + 1]; |
377 | int vendor_oui[MLX4_MAX_PORTS + 1]; | |
378 | int wavelength[MLX4_MAX_PORTS + 1]; | |
379 | u64 trans_code[MLX4_MAX_PORTS + 1]; | |
225c7b1f RD |
380 | int local_ca_ack_delay; |
381 | int num_uars; | |
f5311ac1 | 382 | u32 uar_page_size; |
225c7b1f RD |
383 | int bf_reg_size; |
384 | int bf_regs_per_page; | |
385 | int max_sq_sg; | |
386 | int max_rq_sg; | |
387 | int num_qps; | |
388 | int max_wqes; | |
389 | int max_sq_desc_sz; | |
390 | int max_rq_desc_sz; | |
391 | int max_qp_init_rdma; | |
392 | int max_qp_dest_rdma; | |
47605df9 JM |
393 | u32 *qp0_proxy; |
394 | u32 *qp1_proxy; | |
395 | u32 *qp0_tunnel; | |
396 | u32 *qp1_tunnel; | |
225c7b1f RD |
397 | int num_srqs; |
398 | int max_srq_wqes; | |
399 | int max_srq_sge; | |
400 | int reserved_srqs; | |
401 | int num_cqs; | |
402 | int max_cqes; | |
403 | int reserved_cqs; | |
404 | int num_eqs; | |
405 | int reserved_eqs; | |
b8dd786f | 406 | int num_comp_vectors; |
0b7ca5a9 | 407 | int comp_pool; |
225c7b1f | 408 | int num_mpts; |
a5bbe892 | 409 | int max_fmr_maps; |
2b8fb286 | 410 | int num_mtts; |
225c7b1f RD |
411 | int fmr_reserved_mtts; |
412 | int reserved_mtts; | |
413 | int reserved_mrws; | |
414 | int reserved_uars; | |
415 | int num_mgms; | |
416 | int num_amgms; | |
417 | int reserved_mcgs; | |
418 | int num_qp_per_mgm; | |
c96d97f4 | 419 | int steering_mode; |
0ff1fb65 | 420 | int fs_log_max_ucast_qp_range_size; |
225c7b1f RD |
421 | int num_pds; |
422 | int reserved_pds; | |
012a8ff5 SH |
423 | int max_xrcds; |
424 | int reserved_xrcds; | |
225c7b1f | 425 | int mtt_entry_sz; |
149983af | 426 | u32 max_msg_sz; |
225c7b1f | 427 | u32 page_size_cap; |
52eafc68 | 428 | u64 flags; |
b3416f44 | 429 | u64 flags2; |
95d04f07 RD |
430 | u32 bmme_flags; |
431 | u32 reserved_lkey; | |
225c7b1f | 432 | u16 stat_rate_support; |
5ae2a7a8 | 433 | u8 port_width_cap[MLX4_MAX_PORTS + 1]; |
b832be1e | 434 | int max_gso_sz; |
b3416f44 | 435 | int max_rss_tbl_sz; |
93fc9e1b YP |
436 | int reserved_qps_cnt[MLX4_NUM_QP_REGION]; |
437 | int reserved_qps; | |
438 | int reserved_qps_base[MLX4_NUM_QP_REGION]; | |
439 | int log_num_macs; | |
440 | int log_num_vlans; | |
441 | int log_num_prios; | |
7ff93f8b YP |
442 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; |
443 | u8 supported_type[MLX4_MAX_PORTS + 1]; | |
8d0fc7b6 YP |
444 | u8 suggested_type[MLX4_MAX_PORTS + 1]; |
445 | u8 default_sense[MLX4_MAX_PORTS + 1]; | |
65dab25d | 446 | u32 port_mask[MLX4_MAX_PORTS + 1]; |
27bf91d6 | 447 | enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; |
f2a3f6a3 | 448 | u32 max_counters; |
096335b3 | 449 | u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; |
1ffeb2eb | 450 | u16 sqp_demux; |
08ff3235 OG |
451 | u32 eqe_size; |
452 | u32 cqe_size; | |
453 | u8 eqe_factor; | |
454 | u32 userspace_caps; /* userspace must be aware of these */ | |
455 | u32 function_caps; /* VFs must be aware of these */ | |
ddd8a6c1 | 456 | u16 hca_core_clock; |
225c7b1f RD |
457 | }; |
458 | ||
459 | struct mlx4_buf_list { | |
460 | void *buf; | |
461 | dma_addr_t map; | |
462 | }; | |
463 | ||
464 | struct mlx4_buf { | |
b57aacfa RD |
465 | struct mlx4_buf_list direct; |
466 | struct mlx4_buf_list *page_list; | |
225c7b1f RD |
467 | int nbufs; |
468 | int npages; | |
469 | int page_shift; | |
470 | }; | |
471 | ||
472 | struct mlx4_mtt { | |
2b8fb286 | 473 | u32 offset; |
225c7b1f RD |
474 | int order; |
475 | int page_shift; | |
476 | }; | |
477 | ||
6296883c YP |
478 | enum { |
479 | MLX4_DB_PER_PAGE = PAGE_SIZE / 4 | |
480 | }; | |
481 | ||
482 | struct mlx4_db_pgdir { | |
483 | struct list_head list; | |
484 | DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); | |
485 | DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); | |
486 | unsigned long *bits[2]; | |
487 | __be32 *db_page; | |
488 | dma_addr_t db_dma; | |
489 | }; | |
490 | ||
491 | struct mlx4_ib_user_db_page; | |
492 | ||
493 | struct mlx4_db { | |
494 | __be32 *db; | |
495 | union { | |
496 | struct mlx4_db_pgdir *pgdir; | |
497 | struct mlx4_ib_user_db_page *user_page; | |
498 | } u; | |
499 | dma_addr_t dma; | |
500 | int index; | |
501 | int order; | |
502 | }; | |
503 | ||
38ae6a53 YP |
504 | struct mlx4_hwq_resources { |
505 | struct mlx4_db db; | |
506 | struct mlx4_mtt mtt; | |
507 | struct mlx4_buf buf; | |
508 | }; | |
509 | ||
225c7b1f RD |
510 | struct mlx4_mr { |
511 | struct mlx4_mtt mtt; | |
512 | u64 iova; | |
513 | u64 size; | |
514 | u32 key; | |
515 | u32 pd; | |
516 | u32 access; | |
517 | int enabled; | |
518 | }; | |
519 | ||
804d6a89 SM |
520 | enum mlx4_mw_type { |
521 | MLX4_MW_TYPE_1 = 1, | |
522 | MLX4_MW_TYPE_2 = 2, | |
523 | }; | |
524 | ||
525 | struct mlx4_mw { | |
526 | u32 key; | |
527 | u32 pd; | |
528 | enum mlx4_mw_type type; | |
529 | int enabled; | |
530 | }; | |
531 | ||
8ad11fb6 JM |
532 | struct mlx4_fmr { |
533 | struct mlx4_mr mr; | |
534 | struct mlx4_mpt_entry *mpt; | |
535 | __be64 *mtts; | |
536 | dma_addr_t dma_handle; | |
537 | int max_pages; | |
538 | int max_maps; | |
539 | int maps; | |
540 | u8 page_shift; | |
541 | }; | |
542 | ||
225c7b1f RD |
543 | struct mlx4_uar { |
544 | unsigned long pfn; | |
545 | int index; | |
c1b43dca EC |
546 | struct list_head bf_list; |
547 | unsigned free_bf_bmap; | |
548 | void __iomem *map; | |
549 | void __iomem *bf_map; | |
550 | }; | |
551 | ||
552 | struct mlx4_bf { | |
553 | unsigned long offset; | |
554 | int buf_size; | |
555 | struct mlx4_uar *uar; | |
556 | void __iomem *reg; | |
225c7b1f RD |
557 | }; |
558 | ||
559 | struct mlx4_cq { | |
560 | void (*comp) (struct mlx4_cq *); | |
561 | void (*event) (struct mlx4_cq *, enum mlx4_event); | |
562 | ||
563 | struct mlx4_uar *uar; | |
564 | ||
565 | u32 cons_index; | |
566 | ||
567 | __be32 *set_ci_db; | |
568 | __be32 *arm_db; | |
569 | int arm_sn; | |
570 | ||
571 | int cqn; | |
b8dd786f | 572 | unsigned vector; |
225c7b1f RD |
573 | |
574 | atomic_t refcount; | |
575 | struct completion free; | |
576 | }; | |
577 | ||
578 | struct mlx4_qp { | |
579 | void (*event) (struct mlx4_qp *, enum mlx4_event); | |
580 | ||
581 | int qpn; | |
582 | ||
583 | atomic_t refcount; | |
584 | struct completion free; | |
585 | }; | |
586 | ||
587 | struct mlx4_srq { | |
588 | void (*event) (struct mlx4_srq *, enum mlx4_event); | |
589 | ||
590 | int srqn; | |
591 | int max; | |
592 | int max_gs; | |
593 | int wqe_shift; | |
594 | ||
595 | atomic_t refcount; | |
596 | struct completion free; | |
597 | }; | |
598 | ||
599 | struct mlx4_av { | |
600 | __be32 port_pd; | |
601 | u8 reserved1; | |
602 | u8 g_slid; | |
603 | __be16 dlid; | |
604 | u8 reserved2; | |
605 | u8 gid_index; | |
606 | u8 stat_rate; | |
607 | u8 hop_limit; | |
608 | __be32 sl_tclass_flowlabel; | |
609 | u8 dgid[16]; | |
610 | }; | |
611 | ||
fa417f7b EC |
612 | struct mlx4_eth_av { |
613 | __be32 port_pd; | |
614 | u8 reserved1; | |
615 | u8 smac_idx; | |
616 | u16 reserved2; | |
617 | u8 reserved3; | |
618 | u8 gid_index; | |
619 | u8 stat_rate; | |
620 | u8 hop_limit; | |
621 | __be32 sl_tclass_flowlabel; | |
622 | u8 dgid[16]; | |
623 | u32 reserved4[2]; | |
624 | __be16 vlan; | |
574e2af7 | 625 | u8 mac[ETH_ALEN]; |
fa417f7b EC |
626 | }; |
627 | ||
628 | union mlx4_ext_av { | |
629 | struct mlx4_av ib; | |
630 | struct mlx4_eth_av eth; | |
631 | }; | |
632 | ||
f2a3f6a3 OG |
633 | struct mlx4_counter { |
634 | u8 reserved1[3]; | |
635 | u8 counter_mode; | |
636 | __be32 num_ifc; | |
637 | u32 reserved2[2]; | |
638 | __be64 rx_frames; | |
639 | __be64 rx_bytes; | |
640 | __be64 tx_frames; | |
641 | __be64 tx_bytes; | |
642 | }; | |
643 | ||
5a0d0a61 JM |
644 | struct mlx4_quotas { |
645 | int qp; | |
646 | int cq; | |
647 | int srq; | |
648 | int mpt; | |
649 | int mtt; | |
650 | int counter; | |
651 | int xrcd; | |
652 | }; | |
653 | ||
225c7b1f RD |
654 | struct mlx4_dev { |
655 | struct pci_dev *pdev; | |
656 | unsigned long flags; | |
623ed84b | 657 | unsigned long num_slaves; |
225c7b1f | 658 | struct mlx4_caps caps; |
3fc929e2 | 659 | struct mlx4_phys_caps phys_caps; |
5a0d0a61 | 660 | struct mlx4_quotas quotas; |
225c7b1f | 661 | struct radix_tree_root qp_table_tree; |
725c8999 | 662 | u8 rev_id; |
cd9281d8 | 663 | char board_id[MLX4_BOARD_ID_LEN]; |
ab9c17a0 | 664 | int num_vfs; |
6e7136ed | 665 | int numa_node; |
3c439b55 | 666 | int oper_log_mgm_entry_size; |
592e49dd HHZ |
667 | u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; |
668 | u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; | |
225c7b1f RD |
669 | }; |
670 | ||
00f5ce99 JM |
671 | struct mlx4_eqe { |
672 | u8 reserved1; | |
673 | u8 type; | |
674 | u8 reserved2; | |
675 | u8 subtype; | |
676 | union { | |
677 | u32 raw[6]; | |
678 | struct { | |
679 | __be32 cqn; | |
680 | } __packed comp; | |
681 | struct { | |
682 | u16 reserved1; | |
683 | __be16 token; | |
684 | u32 reserved2; | |
685 | u8 reserved3[3]; | |
686 | u8 status; | |
687 | __be64 out_param; | |
688 | } __packed cmd; | |
689 | struct { | |
690 | __be32 qpn; | |
691 | } __packed qp; | |
692 | struct { | |
693 | __be32 srqn; | |
694 | } __packed srq; | |
695 | struct { | |
696 | __be32 cqn; | |
697 | u32 reserved1; | |
698 | u8 reserved2[3]; | |
699 | u8 syndrome; | |
700 | } __packed cq_err; | |
701 | struct { | |
702 | u32 reserved1[2]; | |
703 | __be32 port; | |
704 | } __packed port_change; | |
705 | struct { | |
706 | #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 | |
707 | u32 reserved; | |
708 | u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; | |
709 | } __packed comm_channel_arm; | |
710 | struct { | |
711 | u8 port; | |
712 | u8 reserved[3]; | |
713 | __be64 mac; | |
714 | } __packed mac_update; | |
715 | struct { | |
716 | __be32 slave_id; | |
717 | } __packed flr_event; | |
718 | struct { | |
719 | __be16 current_temperature; | |
720 | __be16 warning_threshold; | |
721 | } __packed warming; | |
722 | struct { | |
723 | u8 reserved[3]; | |
724 | u8 port; | |
725 | union { | |
726 | struct { | |
727 | __be16 mstr_sm_lid; | |
728 | __be16 port_lid; | |
729 | __be32 changed_attr; | |
730 | u8 reserved[3]; | |
731 | u8 mstr_sm_sl; | |
732 | __be64 gid_prefix; | |
733 | } __packed port_info; | |
734 | struct { | |
735 | __be32 block_ptr; | |
736 | __be32 tbl_entries_mask; | |
737 | } __packed tbl_change_info; | |
738 | } params; | |
739 | } __packed port_mgmt_change; | |
740 | } event; | |
741 | u8 slave_id; | |
742 | u8 reserved3[2]; | |
743 | u8 owner; | |
744 | } __packed; | |
745 | ||
225c7b1f RD |
746 | struct mlx4_init_port_param { |
747 | int set_guid0; | |
748 | int set_node_guid; | |
749 | int set_si_guid; | |
750 | u16 mtu; | |
751 | int port_width_cap; | |
752 | u16 vl_cap; | |
753 | u16 max_gid; | |
754 | u16 max_pkey; | |
755 | u64 guid0; | |
756 | u64 node_guid; | |
757 | u64 si_guid; | |
758 | }; | |
759 | ||
7ff93f8b YP |
760 | #define mlx4_foreach_port(port, dev, type) \ |
761 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
65dab25d | 762 | if ((type) == (dev)->caps.port_mask[(port)]) |
7ff93f8b | 763 | |
026149cb JM |
764 | #define mlx4_foreach_non_ib_transport_port(port, dev) \ |
765 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
766 | if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB)) | |
767 | ||
65dab25d JM |
768 | #define mlx4_foreach_ib_transport_port(port, dev) \ |
769 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
770 | if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ | |
771 | ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) | |
623ed84b | 772 | |
752a50ca JM |
773 | #define MLX4_INVALID_SLAVE_ID 0xFF |
774 | ||
00f5ce99 JM |
775 | void handle_port_mgmt_change_event(struct work_struct *work); |
776 | ||
2aca1172 JM |
777 | static inline int mlx4_master_func_num(struct mlx4_dev *dev) |
778 | { | |
779 | return dev->caps.function; | |
780 | } | |
781 | ||
623ed84b JM |
782 | static inline int mlx4_is_master(struct mlx4_dev *dev) |
783 | { | |
784 | return dev->flags & MLX4_FLAG_MASTER; | |
785 | } | |
786 | ||
5a0d0a61 JM |
787 | static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) |
788 | { | |
789 | return dev->phys_caps.base_sqpn + 8 + | |
790 | 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); | |
791 | } | |
792 | ||
623ed84b JM |
793 | static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) |
794 | { | |
47605df9 | 795 | return (qpn < dev->phys_caps.base_sqpn + 8 + |
e2c76824 JM |
796 | 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev)); |
797 | } | |
798 | ||
799 | static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) | |
800 | { | |
47605df9 | 801 | int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; |
e2c76824 | 802 | |
47605df9 | 803 | if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) |
e2c76824 JM |
804 | return 1; |
805 | ||
806 | return 0; | |
623ed84b | 807 | } |
fa417f7b | 808 | |
623ed84b JM |
809 | static inline int mlx4_is_mfunc(struct mlx4_dev *dev) |
810 | { | |
811 | return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); | |
812 | } | |
813 | ||
814 | static inline int mlx4_is_slave(struct mlx4_dev *dev) | |
815 | { | |
816 | return dev->flags & MLX4_FLAG_SLAVE; | |
817 | } | |
fa417f7b | 818 | |
225c7b1f RD |
819 | int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, |
820 | struct mlx4_buf *buf); | |
821 | void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); | |
1c69fc2a RD |
822 | static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) |
823 | { | |
313abe55 | 824 | if (BITS_PER_LONG == 64 || buf->nbufs == 1) |
b57aacfa | 825 | return buf->direct.buf + offset; |
1c69fc2a | 826 | else |
b57aacfa | 827 | return buf->page_list[offset >> PAGE_SHIFT].buf + |
1c69fc2a RD |
828 | (offset & (PAGE_SIZE - 1)); |
829 | } | |
225c7b1f RD |
830 | |
831 | int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); | |
832 | void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); | |
012a8ff5 SH |
833 | int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); |
834 | void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); | |
225c7b1f RD |
835 | |
836 | int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
837 | void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
163561a4 | 838 | int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); |
c1b43dca | 839 | void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); |
225c7b1f RD |
840 | |
841 | int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, | |
842 | struct mlx4_mtt *mtt); | |
843 | void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
844 | u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
845 | ||
846 | int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, | |
847 | int npages, int page_shift, struct mlx4_mr *mr); | |
61083720 | 848 | int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); |
225c7b1f | 849 | int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); |
804d6a89 SM |
850 | int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, |
851 | struct mlx4_mw *mw); | |
852 | void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); | |
853 | int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); | |
225c7b1f RD |
854 | int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
855 | int start_index, int npages, u64 *page_list); | |
856 | int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
857 | struct mlx4_buf *buf); | |
858 | ||
6296883c YP |
859 | int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); |
860 | void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); | |
861 | ||
38ae6a53 YP |
862 | int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, |
863 | int size, int max_direct); | |
864 | void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, | |
865 | int size); | |
866 | ||
225c7b1f | 867 | int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, |
e463c7b1 | 868 | struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, |
ec693d47 | 869 | unsigned vector, int collapsed, int timestamp_en); |
225c7b1f RD |
870 | void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); |
871 | ||
a3cdcbfa YP |
872 | int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); |
873 | void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); | |
874 | ||
875 | int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); | |
225c7b1f RD |
876 | void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); |
877 | ||
18abd5ea SH |
878 | int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, |
879 | struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); | |
225c7b1f RD |
880 | void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); |
881 | int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); | |
65541cb7 | 882 | int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); |
225c7b1f | 883 | |
5ae2a7a8 | 884 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); |
225c7b1f RD |
885 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); |
886 | ||
ffe455ad EE |
887 | int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
888 | int block_mcast_loopback, enum mlx4_protocol prot); | |
889 | int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | |
890 | enum mlx4_protocol prot); | |
521e575b | 891 | int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
0ff1fb65 HHZ |
892 | u8 port, int block_mcast_loopback, |
893 | enum mlx4_protocol protocol, u64 *reg_id); | |
da995a8a | 894 | int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
0ff1fb65 HHZ |
895 | enum mlx4_protocol protocol, u64 reg_id); |
896 | ||
897 | enum { | |
898 | MLX4_DOMAIN_UVERBS = 0x1000, | |
899 | MLX4_DOMAIN_ETHTOOL = 0x2000, | |
900 | MLX4_DOMAIN_RFS = 0x3000, | |
901 | MLX4_DOMAIN_NIC = 0x5000, | |
902 | }; | |
903 | ||
904 | enum mlx4_net_trans_rule_id { | |
905 | MLX4_NET_TRANS_RULE_ID_ETH = 0, | |
906 | MLX4_NET_TRANS_RULE_ID_IB, | |
907 | MLX4_NET_TRANS_RULE_ID_IPV6, | |
908 | MLX4_NET_TRANS_RULE_ID_IPV4, | |
909 | MLX4_NET_TRANS_RULE_ID_TCP, | |
910 | MLX4_NET_TRANS_RULE_ID_UDP, | |
911 | MLX4_NET_TRANS_RULE_NUM, /* should be last */ | |
912 | }; | |
913 | ||
a8edc3bf HHZ |
914 | extern const u16 __sw_id_hw[]; |
915 | ||
7fb40f87 HHZ |
916 | static inline int map_hw_to_sw_id(u16 header_id) |
917 | { | |
918 | ||
919 | int i; | |
920 | for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { | |
921 | if (header_id == __sw_id_hw[i]) | |
922 | return i; | |
923 | } | |
924 | return -EINVAL; | |
925 | } | |
926 | ||
0ff1fb65 | 927 | enum mlx4_net_trans_promisc_mode { |
f9162539 HHZ |
928 | MLX4_FS_REGULAR = 1, |
929 | MLX4_FS_ALL_DEFAULT, | |
930 | MLX4_FS_MC_DEFAULT, | |
931 | MLX4_FS_UC_SNIFFER, | |
932 | MLX4_FS_MC_SNIFFER, | |
c2c19dc3 | 933 | MLX4_FS_MODE_NUM, /* should be last */ |
0ff1fb65 HHZ |
934 | }; |
935 | ||
936 | struct mlx4_spec_eth { | |
574e2af7 JP |
937 | u8 dst_mac[ETH_ALEN]; |
938 | u8 dst_mac_msk[ETH_ALEN]; | |
939 | u8 src_mac[ETH_ALEN]; | |
940 | u8 src_mac_msk[ETH_ALEN]; | |
0ff1fb65 HHZ |
941 | u8 ether_type_enable; |
942 | __be16 ether_type; | |
943 | __be16 vlan_id_msk; | |
944 | __be16 vlan_id; | |
945 | }; | |
946 | ||
947 | struct mlx4_spec_tcp_udp { | |
948 | __be16 dst_port; | |
949 | __be16 dst_port_msk; | |
950 | __be16 src_port; | |
951 | __be16 src_port_msk; | |
952 | }; | |
953 | ||
954 | struct mlx4_spec_ipv4 { | |
955 | __be32 dst_ip; | |
956 | __be32 dst_ip_msk; | |
957 | __be32 src_ip; | |
958 | __be32 src_ip_msk; | |
959 | }; | |
960 | ||
961 | struct mlx4_spec_ib { | |
ba60a356 | 962 | __be32 l3_qpn; |
0ff1fb65 HHZ |
963 | __be32 qpn_msk; |
964 | u8 dst_gid[16]; | |
965 | u8 dst_gid_msk[16]; | |
966 | }; | |
967 | ||
968 | struct mlx4_spec_list { | |
969 | struct list_head list; | |
970 | enum mlx4_net_trans_rule_id id; | |
971 | union { | |
972 | struct mlx4_spec_eth eth; | |
973 | struct mlx4_spec_ib ib; | |
974 | struct mlx4_spec_ipv4 ipv4; | |
975 | struct mlx4_spec_tcp_udp tcp_udp; | |
976 | }; | |
977 | }; | |
978 | ||
979 | enum mlx4_net_trans_hw_rule_queue { | |
980 | MLX4_NET_TRANS_Q_FIFO, | |
981 | MLX4_NET_TRANS_Q_LIFO, | |
982 | }; | |
983 | ||
984 | struct mlx4_net_trans_rule { | |
985 | struct list_head list; | |
986 | enum mlx4_net_trans_hw_rule_queue queue_mode; | |
987 | bool exclusive; | |
988 | bool allow_loopback; | |
989 | enum mlx4_net_trans_promisc_mode promisc_mode; | |
990 | u8 port; | |
991 | u16 priority; | |
992 | u32 qpn; | |
993 | }; | |
994 | ||
3cd0e178 | 995 | struct mlx4_net_trans_rule_hw_ctrl { |
bcf37297 HHZ |
996 | __be16 prio; |
997 | u8 type; | |
998 | u8 flags; | |
3cd0e178 HHZ |
999 | u8 rsvd1; |
1000 | u8 funcid; | |
1001 | u8 vep; | |
1002 | u8 port; | |
1003 | __be32 qpn; | |
1004 | __be32 rsvd2; | |
1005 | }; | |
1006 | ||
1007 | struct mlx4_net_trans_rule_hw_ib { | |
1008 | u8 size; | |
1009 | u8 rsvd1; | |
1010 | __be16 id; | |
1011 | u32 rsvd2; | |
ba60a356 | 1012 | __be32 l3_qpn; |
3cd0e178 HHZ |
1013 | __be32 qpn_mask; |
1014 | u8 dst_gid[16]; | |
1015 | u8 dst_gid_msk[16]; | |
1016 | } __packed; | |
1017 | ||
1018 | struct mlx4_net_trans_rule_hw_eth { | |
1019 | u8 size; | |
1020 | u8 rsvd; | |
1021 | __be16 id; | |
1022 | u8 rsvd1[6]; | |
1023 | u8 dst_mac[6]; | |
1024 | u16 rsvd2; | |
1025 | u8 dst_mac_msk[6]; | |
1026 | u16 rsvd3; | |
1027 | u8 src_mac[6]; | |
1028 | u16 rsvd4; | |
1029 | u8 src_mac_msk[6]; | |
1030 | u8 rsvd5; | |
1031 | u8 ether_type_enable; | |
1032 | __be16 ether_type; | |
ba60a356 HHZ |
1033 | __be16 vlan_tag_msk; |
1034 | __be16 vlan_tag; | |
3cd0e178 HHZ |
1035 | } __packed; |
1036 | ||
1037 | struct mlx4_net_trans_rule_hw_tcp_udp { | |
1038 | u8 size; | |
1039 | u8 rsvd; | |
1040 | __be16 id; | |
1041 | __be16 rsvd1[3]; | |
1042 | __be16 dst_port; | |
1043 | __be16 rsvd2; | |
1044 | __be16 dst_port_msk; | |
1045 | __be16 rsvd3; | |
1046 | __be16 src_port; | |
1047 | __be16 rsvd4; | |
1048 | __be16 src_port_msk; | |
1049 | } __packed; | |
1050 | ||
1051 | struct mlx4_net_trans_rule_hw_ipv4 { | |
1052 | u8 size; | |
1053 | u8 rsvd; | |
1054 | __be16 id; | |
1055 | __be32 rsvd1; | |
1056 | __be32 dst_ip; | |
1057 | __be32 dst_ip_msk; | |
1058 | __be32 src_ip; | |
1059 | __be32 src_ip_msk; | |
1060 | } __packed; | |
1061 | ||
1062 | struct _rule_hw { | |
1063 | union { | |
1064 | struct { | |
1065 | u8 size; | |
1066 | u8 rsvd; | |
1067 | __be16 id; | |
1068 | }; | |
1069 | struct mlx4_net_trans_rule_hw_eth eth; | |
1070 | struct mlx4_net_trans_rule_hw_ib ib; | |
1071 | struct mlx4_net_trans_rule_hw_ipv4 ipv4; | |
1072 | struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; | |
1073 | }; | |
1074 | }; | |
1075 | ||
592e49dd HHZ |
1076 | int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, |
1077 | enum mlx4_net_trans_promisc_mode mode); | |
1078 | int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, | |
1079 | enum mlx4_net_trans_promisc_mode mode); | |
1679200f YP |
1080 | int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); |
1081 | int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1082 | int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1083 | int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1084 | int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); | |
1085 | ||
ffe455ad EE |
1086 | int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); |
1087 | void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); | |
16a10ffd YB |
1088 | int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); |
1089 | int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); | |
93ece0c1 | 1090 | void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap); |
9a9a232a YP |
1091 | int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, |
1092 | u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); | |
1093 | int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, | |
1094 | u8 promisc); | |
e5395e92 AV |
1095 | int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); |
1096 | int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, | |
1097 | u8 *pg, u16 *ratelimit); | |
4c3eb3ca | 1098 | int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); |
2a2336f8 | 1099 | int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); |
2009d005 | 1100 | void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); |
2a2336f8 | 1101 | |
8ad11fb6 JM |
1102 | int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, |
1103 | int npages, u64 iova, u32 *lkey, u32 *rkey); | |
1104 | int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, | |
1105 | int max_maps, u8 page_shift, struct mlx4_fmr *fmr); | |
1106 | int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
1107 | void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, | |
1108 | u32 *lkey, u32 *rkey); | |
1109 | int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
1110 | int mlx4_SYNC_TPT(struct mlx4_dev *dev); | |
e7c1c2c4 | 1111 | int mlx4_test_interrupts(struct mlx4_dev *dev); |
d9236c3f AV |
1112 | int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap, |
1113 | int *vector); | |
0b7ca5a9 | 1114 | void mlx4_release_eq(struct mlx4_dev *dev, int vec); |
8ad11fb6 | 1115 | |
14c07b13 YP |
1116 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); |
1117 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); | |
1118 | ||
f2a3f6a3 OG |
1119 | int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); |
1120 | void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); | |
1121 | ||
0ff1fb65 HHZ |
1122 | int mlx4_flow_attach(struct mlx4_dev *dev, |
1123 | struct mlx4_net_trans_rule *rule, u64 *reg_id); | |
1124 | int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); | |
c2c19dc3 HHZ |
1125 | int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, |
1126 | enum mlx4_net_trans_promisc_mode flow_type); | |
1127 | int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, | |
1128 | enum mlx4_net_trans_rule_id id); | |
1129 | int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); | |
0ff1fb65 | 1130 | |
54679e14 JM |
1131 | void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, |
1132 | int i, int val); | |
1133 | ||
396f2feb JM |
1134 | int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); |
1135 | ||
993c401e JM |
1136 | int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); |
1137 | int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); | |
1138 | int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); | |
1139 | int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); | |
1140 | int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); | |
1141 | enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); | |
1142 | int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); | |
1143 | ||
afa8fd1d JM |
1144 | void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); |
1145 | __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); | |
993c401e | 1146 | |
ec693d47 AV |
1147 | cycle_t mlx4_read_clock(struct mlx4_dev *dev); |
1148 | ||
225c7b1f | 1149 | #endif /* MLX4_DEVICE_H */ |