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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX4_DEVICE_H | |
34 | #define MLX4_DEVICE_H | |
35 | ||
36 | #include <linux/pci.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/radix-tree.h> | |
39 | ||
40 | #include <asm/atomic.h> | |
41 | ||
42 | enum { | |
43 | MLX4_FLAG_MSI_X = 1 << 0, | |
5ae2a7a8 | 44 | MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, |
225c7b1f RD |
45 | }; |
46 | ||
47 | enum { | |
48 | MLX4_MAX_PORTS = 2 | |
49 | }; | |
50 | ||
cd9281d8 JM |
51 | enum { |
52 | MLX4_BOARD_ID_LEN = 64 | |
53 | }; | |
54 | ||
225c7b1f RD |
55 | enum { |
56 | MLX4_DEV_CAP_FLAG_RC = 1 << 0, | |
57 | MLX4_DEV_CAP_FLAG_UC = 1 << 1, | |
58 | MLX4_DEV_CAP_FLAG_UD = 1 << 2, | |
59 | MLX4_DEV_CAP_FLAG_SRQ = 1 << 6, | |
60 | MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7, | |
61 | MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8, | |
62 | MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9, | |
7ff93f8b | 63 | MLX4_DEV_CAP_FLAG_DPDP = 1 << 12, |
225c7b1f RD |
64 | MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16, |
65 | MLX4_DEV_CAP_FLAG_APM = 1 << 17, | |
66 | MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18, | |
67 | MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19, | |
68 | MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20, | |
69 | MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21 | |
70 | }; | |
71 | ||
95d04f07 RD |
72 | enum { |
73 | MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, | |
74 | MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, | |
75 | MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, | |
76 | MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, | |
77 | MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, | |
78 | }; | |
79 | ||
225c7b1f RD |
80 | enum mlx4_event { |
81 | MLX4_EVENT_TYPE_COMP = 0x00, | |
82 | MLX4_EVENT_TYPE_PATH_MIG = 0x01, | |
83 | MLX4_EVENT_TYPE_COMM_EST = 0x02, | |
84 | MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, | |
85 | MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, | |
86 | MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, | |
87 | MLX4_EVENT_TYPE_CQ_ERROR = 0x04, | |
88 | MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
89 | MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, | |
90 | MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, | |
91 | MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | |
92 | MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | |
93 | MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | |
94 | MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, | |
95 | MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, | |
96 | MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, | |
97 | MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, | |
98 | MLX4_EVENT_TYPE_CMD = 0x0a | |
99 | }; | |
100 | ||
101 | enum { | |
102 | MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, | |
103 | MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 | |
104 | }; | |
105 | ||
106 | enum { | |
107 | MLX4_PERM_LOCAL_READ = 1 << 10, | |
108 | MLX4_PERM_LOCAL_WRITE = 1 << 11, | |
109 | MLX4_PERM_REMOTE_READ = 1 << 12, | |
110 | MLX4_PERM_REMOTE_WRITE = 1 << 13, | |
111 | MLX4_PERM_ATOMIC = 1 << 14 | |
112 | }; | |
113 | ||
114 | enum { | |
115 | MLX4_OPCODE_NOP = 0x00, | |
116 | MLX4_OPCODE_SEND_INVAL = 0x01, | |
117 | MLX4_OPCODE_RDMA_WRITE = 0x08, | |
118 | MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, | |
119 | MLX4_OPCODE_SEND = 0x0a, | |
120 | MLX4_OPCODE_SEND_IMM = 0x0b, | |
121 | MLX4_OPCODE_LSO = 0x0e, | |
122 | MLX4_OPCODE_RDMA_READ = 0x10, | |
123 | MLX4_OPCODE_ATOMIC_CS = 0x11, | |
124 | MLX4_OPCODE_ATOMIC_FA = 0x12, | |
125 | MLX4_OPCODE_ATOMIC_MASK_CS = 0x14, | |
126 | MLX4_OPCODE_ATOMIC_MASK_FA = 0x15, | |
127 | MLX4_OPCODE_BIND_MW = 0x18, | |
128 | MLX4_OPCODE_FMR = 0x19, | |
129 | MLX4_OPCODE_LOCAL_INVAL = 0x1b, | |
130 | MLX4_OPCODE_CONFIG_CMD = 0x1f, | |
131 | ||
132 | MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, | |
133 | MLX4_RECV_OPCODE_SEND = 0x01, | |
134 | MLX4_RECV_OPCODE_SEND_IMM = 0x02, | |
135 | MLX4_RECV_OPCODE_SEND_INVAL = 0x03, | |
136 | ||
137 | MLX4_CQE_OPCODE_ERROR = 0x1e, | |
138 | MLX4_CQE_OPCODE_RESIZE = 0x16, | |
139 | }; | |
140 | ||
141 | enum { | |
142 | MLX4_STAT_RATE_OFFSET = 5 | |
143 | }; | |
144 | ||
29bdc883 VS |
145 | enum { |
146 | MLX4_MTT_FLAG_PRESENT = 1 | |
147 | }; | |
148 | ||
93fc9e1b YP |
149 | enum mlx4_qp_region { |
150 | MLX4_QP_REGION_FW = 0, | |
151 | MLX4_QP_REGION_ETH_ADDR, | |
152 | MLX4_QP_REGION_FC_ADDR, | |
153 | MLX4_QP_REGION_FC_EXCH, | |
154 | MLX4_NUM_QP_REGION | |
155 | }; | |
156 | ||
7ff93f8b YP |
157 | enum mlx4_port_type { |
158 | MLX4_PORT_TYPE_IB = 1 << 0, | |
159 | MLX4_PORT_TYPE_ETH = 1 << 1, | |
160 | }; | |
161 | ||
2a2336f8 YP |
162 | enum mlx4_special_vlan_idx { |
163 | MLX4_NO_VLAN_IDX = 0, | |
164 | MLX4_VLAN_MISS_IDX, | |
165 | MLX4_VLAN_REGULAR | |
166 | }; | |
167 | ||
93fc9e1b YP |
168 | enum { |
169 | MLX4_NUM_FEXCH = 64 * 1024, | |
170 | }; | |
171 | ||
ea54b10c JM |
172 | static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) |
173 | { | |
174 | return (major << 32) | (minor << 16) | subminor; | |
175 | } | |
176 | ||
225c7b1f RD |
177 | struct mlx4_caps { |
178 | u64 fw_ver; | |
179 | int num_ports; | |
5ae2a7a8 | 180 | int vl_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 YP |
181 | int ib_mtu_cap[MLX4_MAX_PORTS + 1]; |
182 | u64 def_mac[MLX4_MAX_PORTS + 1]; | |
183 | int eth_mtu_cap[MLX4_MAX_PORTS + 1]; | |
5ae2a7a8 RD |
184 | int gid_table_len[MLX4_MAX_PORTS + 1]; |
185 | int pkey_table_len[MLX4_MAX_PORTS + 1]; | |
225c7b1f RD |
186 | int local_ca_ack_delay; |
187 | int num_uars; | |
188 | int bf_reg_size; | |
189 | int bf_regs_per_page; | |
190 | int max_sq_sg; | |
191 | int max_rq_sg; | |
192 | int num_qps; | |
193 | int max_wqes; | |
194 | int max_sq_desc_sz; | |
195 | int max_rq_desc_sz; | |
196 | int max_qp_init_rdma; | |
197 | int max_qp_dest_rdma; | |
225c7b1f RD |
198 | int sqp_start; |
199 | int num_srqs; | |
200 | int max_srq_wqes; | |
201 | int max_srq_sge; | |
202 | int reserved_srqs; | |
203 | int num_cqs; | |
204 | int max_cqes; | |
205 | int reserved_cqs; | |
206 | int num_eqs; | |
207 | int reserved_eqs; | |
208 | int num_mpts; | |
209 | int num_mtt_segs; | |
210 | int fmr_reserved_mtts; | |
211 | int reserved_mtts; | |
212 | int reserved_mrws; | |
213 | int reserved_uars; | |
214 | int num_mgms; | |
215 | int num_amgms; | |
216 | int reserved_mcgs; | |
217 | int num_qp_per_mgm; | |
218 | int num_pds; | |
219 | int reserved_pds; | |
220 | int mtt_entry_sz; | |
149983af | 221 | u32 max_msg_sz; |
225c7b1f RD |
222 | u32 page_size_cap; |
223 | u32 flags; | |
95d04f07 RD |
224 | u32 bmme_flags; |
225 | u32 reserved_lkey; | |
225c7b1f | 226 | u16 stat_rate_support; |
5ae2a7a8 | 227 | u8 port_width_cap[MLX4_MAX_PORTS + 1]; |
b832be1e | 228 | int max_gso_sz; |
93fc9e1b YP |
229 | int reserved_qps_cnt[MLX4_NUM_QP_REGION]; |
230 | int reserved_qps; | |
231 | int reserved_qps_base[MLX4_NUM_QP_REGION]; | |
232 | int log_num_macs; | |
233 | int log_num_vlans; | |
234 | int log_num_prios; | |
7ff93f8b YP |
235 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; |
236 | u8 supported_type[MLX4_MAX_PORTS + 1]; | |
237 | u32 port_mask; | |
225c7b1f RD |
238 | }; |
239 | ||
240 | struct mlx4_buf_list { | |
241 | void *buf; | |
242 | dma_addr_t map; | |
243 | }; | |
244 | ||
245 | struct mlx4_buf { | |
b57aacfa RD |
246 | struct mlx4_buf_list direct; |
247 | struct mlx4_buf_list *page_list; | |
225c7b1f RD |
248 | int nbufs; |
249 | int npages; | |
250 | int page_shift; | |
251 | }; | |
252 | ||
253 | struct mlx4_mtt { | |
254 | u32 first_seg; | |
255 | int order; | |
256 | int page_shift; | |
257 | }; | |
258 | ||
6296883c YP |
259 | enum { |
260 | MLX4_DB_PER_PAGE = PAGE_SIZE / 4 | |
261 | }; | |
262 | ||
263 | struct mlx4_db_pgdir { | |
264 | struct list_head list; | |
265 | DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); | |
266 | DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); | |
267 | unsigned long *bits[2]; | |
268 | __be32 *db_page; | |
269 | dma_addr_t db_dma; | |
270 | }; | |
271 | ||
272 | struct mlx4_ib_user_db_page; | |
273 | ||
274 | struct mlx4_db { | |
275 | __be32 *db; | |
276 | union { | |
277 | struct mlx4_db_pgdir *pgdir; | |
278 | struct mlx4_ib_user_db_page *user_page; | |
279 | } u; | |
280 | dma_addr_t dma; | |
281 | int index; | |
282 | int order; | |
283 | }; | |
284 | ||
38ae6a53 YP |
285 | struct mlx4_hwq_resources { |
286 | struct mlx4_db db; | |
287 | struct mlx4_mtt mtt; | |
288 | struct mlx4_buf buf; | |
289 | }; | |
290 | ||
225c7b1f RD |
291 | struct mlx4_mr { |
292 | struct mlx4_mtt mtt; | |
293 | u64 iova; | |
294 | u64 size; | |
295 | u32 key; | |
296 | u32 pd; | |
297 | u32 access; | |
298 | int enabled; | |
299 | }; | |
300 | ||
8ad11fb6 JM |
301 | struct mlx4_fmr { |
302 | struct mlx4_mr mr; | |
303 | struct mlx4_mpt_entry *mpt; | |
304 | __be64 *mtts; | |
305 | dma_addr_t dma_handle; | |
306 | int max_pages; | |
307 | int max_maps; | |
308 | int maps; | |
309 | u8 page_shift; | |
310 | }; | |
311 | ||
225c7b1f RD |
312 | struct mlx4_uar { |
313 | unsigned long pfn; | |
314 | int index; | |
315 | }; | |
316 | ||
317 | struct mlx4_cq { | |
318 | void (*comp) (struct mlx4_cq *); | |
319 | void (*event) (struct mlx4_cq *, enum mlx4_event); | |
320 | ||
321 | struct mlx4_uar *uar; | |
322 | ||
323 | u32 cons_index; | |
324 | ||
325 | __be32 *set_ci_db; | |
326 | __be32 *arm_db; | |
327 | int arm_sn; | |
328 | ||
329 | int cqn; | |
330 | ||
331 | atomic_t refcount; | |
332 | struct completion free; | |
333 | }; | |
334 | ||
335 | struct mlx4_qp { | |
336 | void (*event) (struct mlx4_qp *, enum mlx4_event); | |
337 | ||
338 | int qpn; | |
339 | ||
340 | atomic_t refcount; | |
341 | struct completion free; | |
342 | }; | |
343 | ||
344 | struct mlx4_srq { | |
345 | void (*event) (struct mlx4_srq *, enum mlx4_event); | |
346 | ||
347 | int srqn; | |
348 | int max; | |
349 | int max_gs; | |
350 | int wqe_shift; | |
351 | ||
352 | atomic_t refcount; | |
353 | struct completion free; | |
354 | }; | |
355 | ||
356 | struct mlx4_av { | |
357 | __be32 port_pd; | |
358 | u8 reserved1; | |
359 | u8 g_slid; | |
360 | __be16 dlid; | |
361 | u8 reserved2; | |
362 | u8 gid_index; | |
363 | u8 stat_rate; | |
364 | u8 hop_limit; | |
365 | __be32 sl_tclass_flowlabel; | |
366 | u8 dgid[16]; | |
367 | }; | |
368 | ||
369 | struct mlx4_dev { | |
370 | struct pci_dev *pdev; | |
371 | unsigned long flags; | |
372 | struct mlx4_caps caps; | |
373 | struct radix_tree_root qp_table_tree; | |
cd9281d8 JM |
374 | u32 rev_id; |
375 | char board_id[MLX4_BOARD_ID_LEN]; | |
225c7b1f RD |
376 | }; |
377 | ||
378 | struct mlx4_init_port_param { | |
379 | int set_guid0; | |
380 | int set_node_guid; | |
381 | int set_si_guid; | |
382 | u16 mtu; | |
383 | int port_width_cap; | |
384 | u16 vl_cap; | |
385 | u16 max_gid; | |
386 | u16 max_pkey; | |
387 | u64 guid0; | |
388 | u64 node_guid; | |
389 | u64 si_guid; | |
390 | }; | |
391 | ||
7ff93f8b YP |
392 | #define mlx4_foreach_port(port, dev, type) \ |
393 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
394 | if (((type) == MLX4_PORT_TYPE_IB ? (dev)->caps.port_mask : \ | |
395 | ~(dev)->caps.port_mask) & 1 << ((port) - 1)) | |
396 | ||
225c7b1f RD |
397 | int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, |
398 | struct mlx4_buf *buf); | |
399 | void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); | |
1c69fc2a RD |
400 | static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) |
401 | { | |
313abe55 | 402 | if (BITS_PER_LONG == 64 || buf->nbufs == 1) |
b57aacfa | 403 | return buf->direct.buf + offset; |
1c69fc2a | 404 | else |
b57aacfa | 405 | return buf->page_list[offset >> PAGE_SHIFT].buf + |
1c69fc2a RD |
406 | (offset & (PAGE_SIZE - 1)); |
407 | } | |
225c7b1f RD |
408 | |
409 | int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); | |
410 | void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); | |
411 | ||
412 | int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
413 | void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
414 | ||
415 | int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, | |
416 | struct mlx4_mtt *mtt); | |
417 | void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
418 | u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
419 | ||
420 | int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, | |
421 | int npages, int page_shift, struct mlx4_mr *mr); | |
422 | void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); | |
423 | int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); | |
424 | int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
425 | int start_index, int npages, u64 *page_list); | |
426 | int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
427 | struct mlx4_buf *buf); | |
428 | ||
6296883c YP |
429 | int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); |
430 | void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); | |
431 | ||
38ae6a53 YP |
432 | int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, |
433 | int size, int max_direct); | |
434 | void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, | |
435 | int size); | |
436 | ||
225c7b1f | 437 | int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, |
e463c7b1 YP |
438 | struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, |
439 | int collapsed); | |
225c7b1f RD |
440 | void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); |
441 | ||
a3cdcbfa YP |
442 | int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); |
443 | void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); | |
444 | ||
445 | int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); | |
225c7b1f RD |
446 | void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); |
447 | ||
448 | int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt, | |
449 | u64 db_rec, struct mlx4_srq *srq); | |
450 | void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); | |
451 | int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); | |
65541cb7 | 452 | int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); |
225c7b1f | 453 | |
5ae2a7a8 | 454 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); |
225c7b1f RD |
455 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); |
456 | ||
521e575b RL |
457 | int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
458 | int block_mcast_loopback); | |
225c7b1f RD |
459 | int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]); |
460 | ||
2a2336f8 YP |
461 | int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *index); |
462 | void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int index); | |
463 | ||
464 | int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); | |
465 | void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index); | |
466 | ||
8ad11fb6 JM |
467 | int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, |
468 | int npages, u64 iova, u32 *lkey, u32 *rkey); | |
469 | int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, | |
470 | int max_maps, u8 page_shift, struct mlx4_fmr *fmr); | |
471 | int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
472 | void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, | |
473 | u32 *lkey, u32 *rkey); | |
474 | int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
475 | int mlx4_SYNC_TPT(struct mlx4_dev *dev); | |
476 | ||
225c7b1f | 477 | #endif /* MLX4_DEVICE_H */ |