projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
{net,IB}/mlx5: CQ commands via mlx5 ifc
[deliverable/linux.git] / include / linux / mlx5 / device.h
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
e281682b 38#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
d29b796a
EC		 48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
58
59#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
9218b44d 62#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
938fe83c
SM		 63#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
64#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
d29b796a
EC		 65#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
66#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
67
68/* insert a value to a struct */
69#define MLX5_SET(typ, p, fld, v) do { \
70 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
71 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
72 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
73 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
74 << __mlx5_dw_bit_off(typ, fld))); \
75} while (0)
76
e281682b
SM		 77#define MLX5_SET_TO_ONES(typ, p, fld) do { \
78 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
79 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
80 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
81 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
82 << __mlx5_dw_bit_off(typ, fld))); \
83} while (0)
84
d29b796a
EC		 85#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
86__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
87__mlx5_mask(typ, fld))
88
89#define MLX5_GET_PR(typ, p, fld) ({ \
90 u32 ___t = MLX5_GET(typ, p, fld); \
91 pr_debug(#fld " = 0x%x\n", ___t); \
92 ___t; \
93})
94
95#define MLX5_SET64(typ, p, fld, v) do { \
96 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
97 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
98 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
99} while (0)
100
101#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
102
707c4602
MD		 103#define MLX5_GET64_PR(typ, p, fld) ({ \
104 u64 ___t = MLX5_GET64(typ, p, fld); \
105 pr_debug(#fld " = 0x%llx\n", ___t); \
106 ___t; \
107})
108
3efd9a11
MY		 109/* Big endian getters */
110#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
111 __mlx5_64_off(typ, fld)))
112
113#define MLX5_GET_BE(type_t, typ, p, fld) ({ \
114 type_t tmp; \
115 switch (sizeof(tmp)) { \
116 case sizeof(u8): \
117 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
118 break; \
119 case sizeof(u16): \
120 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
121 break; \
122 case sizeof(u32): \
123 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
124 break; \
125 case sizeof(u64): \
126 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
127 break; \
128 } \
129 tmp; \
130 })
131
ae76715d
HHZ		 132enum mlx5_inline_modes {
133 MLX5_INLINE_MODE_NONE,
134 MLX5_INLINE_MODE_L2,
135 MLX5_INLINE_MODE_IP,
136 MLX5_INLINE_MODE_TCP_UDP,
137};
138
e126ba97
EC		 139enum {
140 MLX5_MAX_COMMANDS = 32,
141 MLX5_CMD_DATA_BLOCK_SIZE = 512,
142 MLX5_PCI_CMD_XPORT = 7,
3121e3c4
SG		 143 MLX5_MKEY_BSF_OCTO_SIZE = 4,
144 MLX5_MAX_PSVS = 4,
e126ba97
EC		 145};
146
147enum {
148 MLX5_EXTENDED_UD_AV = 0x80000000,
149};
150
151enum {
152 MLX5_CQ_STATE_ARMED = 9,
153 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
154 MLX5_CQ_STATE_FIRED = 0xa,
155};
156
157enum {
158 MLX5_STAT_RATE_OFFSET = 5,
159};
160
161enum {
162 MLX5_INLINE_SEG = 0x80000000,
163};
164
fc11fbf9
SM		 165enum {
166 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
167};
168
c7a08ac7
EC		 169enum {
170 MLX5_MIN_PKEY_TABLE_SIZE = 128,
171 MLX5_MAX_LOG_PKEY_TABLE = 5,
172};
173
e420f0c0
HE		 174enum {
175 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
176};
177
178enum {
179 MLX5_PFAULT_SUBTYPE_WQE = 0,
180 MLX5_PFAULT_SUBTYPE_RDMA = 1,
181};
182
e126ba97
EC		 183enum {
184 MLX5_PERM_LOCAL_READ = 1 << 2,
185 MLX5_PERM_LOCAL_WRITE = 1 << 3,
186 MLX5_PERM_REMOTE_READ = 1 << 4,
187 MLX5_PERM_REMOTE_WRITE = 1 << 5,
188 MLX5_PERM_ATOMIC = 1 << 6,
189 MLX5_PERM_UMR_EN = 1 << 7,
190};
191
192enum {
193 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
194 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
195 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
196 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
197 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
198};
199
200enum {
201 MLX5_ACCESS_MODE_PA = 0,
202 MLX5_ACCESS_MODE_MTT = 1,
203 MLX5_ACCESS_MODE_KLM = 2
204};
205
206enum {
207 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
208 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
209 MLX5_MKEY_BSF_EN = 1 << 30,
210 MLX5_MKEY_LEN64 = 1 << 31,
211};
212
213enum {
214 MLX5_EN_RD = (u64)1,
215 MLX5_EN_WR = (u64)2
216};
217
218enum {
c1be5232
EC		 219 MLX5_BF_REGS_PER_PAGE = 4,
220 MLX5_MAX_UAR_PAGES = 1 << 8,
221 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
222 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
e126ba97
EC		 223};
224
225enum {
226 MLX5_MKEY_MASK_LEN = 1ull << 0,
227 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
228 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
229 MLX5_MKEY_MASK_PD = 1ull << 7,
230 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
d5436ba0 231 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
e126ba97
EC		 232 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
233 MLX5_MKEY_MASK_KEY = 1ull << 13,
234 MLX5_MKEY_MASK_QPN = 1ull << 14,
235 MLX5_MKEY_MASK_LR = 1ull << 17,
236 MLX5_MKEY_MASK_LW = 1ull << 18,
237 MLX5_MKEY_MASK_RR = 1ull << 19,
238 MLX5_MKEY_MASK_RW = 1ull << 20,
239 MLX5_MKEY_MASK_A = 1ull << 21,
240 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
241 MLX5_MKEY_MASK_FREE = 1ull << 29,
242};
243
968e78dd
HE		 244enum {
245 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
246
247 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
248 MLX5_UMR_CHECK_FREE = (2 << 5),
249
250 MLX5_UMR_INLINE = (1 << 7),
251};
252
cc149f75
HE		 253#define MLX5_UMR_MTT_ALIGNMENT 0x40
254#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
832a6b06 255#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
cc149f75 256
e2013b21 257#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
258
259enum {
260 MLX5_EVENT_QUEUE_TYPE_QP = 0,
261 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
262 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
263};
264
e126ba97
EC		 265enum mlx5_event {
266 MLX5_EVENT_TYPE_COMP = 0x0,
267
268 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
269 MLX5_EVENT_TYPE_COMM_EST = 0x02,
270 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
271 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
272 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
273
274 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
275 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
276 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
277 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
278 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
279 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
280
281 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
282 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
283 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
284 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
285
286 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
287 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
288
289 MLX5_EVENT_TYPE_CMD = 0x0a,
290 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
e420f0c0
HE		 291
292 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
073bb189 293 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
e126ba97
EC		 294};
295
296enum {
297 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
298 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
299 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
300 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
301 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
302 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
303 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
304};
305
306enum {
e126ba97 307 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
e126ba97
EC		 308 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
309 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
310 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
311 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
f360d88a 312 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
6cb7ff3d 313 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
3bdb31f6 314 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
bde51583 315 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
c7a08ac7 316 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
e126ba97 317 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
c1868b82 318 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
e126ba97
EC		 319};
320
3cca2606
AS		 321enum {
322 MLX5_ROCE_VERSION_1 = 0,
323 MLX5_ROCE_VERSION_2 = 2,
324};
325
326enum {
327 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
328 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
329};
330
331enum {
332 MLX5_ROCE_L3_TYPE_IPV4 = 0,
333 MLX5_ROCE_L3_TYPE_IPV6 = 1,
334};
335
336enum {
337 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
338 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
339};
340
e126ba97
EC		 341enum {
342 MLX5_OPCODE_NOP = 0x00,
343 MLX5_OPCODE_SEND_INVAL = 0x01,
344 MLX5_OPCODE_RDMA_WRITE = 0x08,
345 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
346 MLX5_OPCODE_SEND = 0x0a,
347 MLX5_OPCODE_SEND_IMM = 0x0b,
e281682b 348 MLX5_OPCODE_LSO = 0x0e,
e126ba97
EC		 349 MLX5_OPCODE_RDMA_READ = 0x10,
350 MLX5_OPCODE_ATOMIC_CS = 0x11,
351 MLX5_OPCODE_ATOMIC_FA = 0x12,
352 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
353 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
354 MLX5_OPCODE_BIND_MW = 0x18,
355 MLX5_OPCODE_CONFIG_CMD = 0x1f,
356
357 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
358 MLX5_RECV_OPCODE_SEND = 0x01,
359 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
360 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
361
362 MLX5_CQE_OPCODE_ERROR = 0x1e,
363 MLX5_CQE_OPCODE_RESIZE = 0x16,
364
365 MLX5_OPCODE_SET_PSV = 0x20,
366 MLX5_OPCODE_GET_PSV = 0x21,
367 MLX5_OPCODE_CHECK_PSV = 0x22,
368 MLX5_OPCODE_RGET_PSV = 0x26,
369 MLX5_OPCODE_RCHECK_PSV = 0x27,
370
371 MLX5_OPCODE_UMR = 0x25,
372
373};
374
375enum {
376 MLX5_SET_PORT_RESET_QKEY = 0,
377 MLX5_SET_PORT_GUID0 = 16,
378 MLX5_SET_PORT_NODE_GUID = 17,
379 MLX5_SET_PORT_SYS_GUID = 18,
380 MLX5_SET_PORT_GID_TABLE = 19,
381 MLX5_SET_PORT_PKEY_TABLE = 20,
382};
383
d8880795
TT		 384enum {
385 MLX5_BW_NO_LIMIT = 0,
386 MLX5_100_MBPS_UNIT = 3,
387 MLX5_GBPS_UNIT = 4,
388};
389
e126ba97
EC		 390enum {
391 MLX5_MAX_PAGE_SHIFT = 31
392};
393
1b77d2bd 394enum {
05bdb2ab
EC		 395 MLX5_ADAPTER_PAGE_SHIFT = 12,
396 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
1b77d2bd
EC		 397};
398
87b8de49 399enum {
87b8de49
EC		 400 MLX5_CAP_OFF_CMDIF_CSUM = 46,
401};
402
986ef95e
SG		 403enum {
404 /*
405 * Max wqe size for rdma read is 512 bytes, so this
406 * limits our max_sge_rd as the wqe needs to fit:
407 * - ctrl segment (16 bytes)
408 * - rdma segment (16 bytes)
409 * - scatter elements (16 bytes each)
410 */
411 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
412};
413
e126ba97
EC		 414struct mlx5_inbox_hdr {
415 __be16 opcode;
416 u8 rsvd[4];
417 __be16 opmod;
418};
419
420struct mlx5_outbox_hdr {
421 u8 status;
422 u8 rsvd[3];
423 __be32 syndrome;
424};
425
426struct mlx5_cmd_query_adapter_mbox_in {
427 struct mlx5_inbox_hdr hdr;
428 u8 rsvd[8];
429};
430
431struct mlx5_cmd_query_adapter_mbox_out {
432 struct mlx5_outbox_hdr hdr;
433 u8 rsvd0[24];
434 u8 intapin;
435 u8 rsvd1[13];
436 __be16 vsd_vendor_id;
437 u8 vsd[208];
438 u8 vsd_psid[16];
439};
440
e420f0c0
HE		 441enum mlx5_odp_transport_cap_bits {
442 MLX5_ODP_SUPPORT_SEND = 1 << 31,
443 MLX5_ODP_SUPPORT_RECV = 1 << 30,
444 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
445 MLX5_ODP_SUPPORT_READ = 1 << 28,
446};
447
448struct mlx5_odp_caps {
449 char reserved[0x10];
450 struct {
451 __be32 rc_odp_caps;
452 __be32 uc_odp_caps;
453 __be32 ud_odp_caps;
454 } per_transport_caps;
455 char reserved2[0xe4];
456};
457
e126ba97
EC		 458struct mlx5_cmd_layout {
459 u8 type;
460 u8 rsvd0[3];
461 __be32 inlen;
462 __be64 in_ptr;
463 __be32 in[4];
464 __be32 out[4];
465 __be64 out_ptr;
466 __be32 outlen;
467 u8 token;
468 u8 sig;
469 u8 rsvd1;
470 u8 status_own;
471};
472
473
474struct health_buffer {
475 __be32 assert_var[5];
476 __be32 rsvd0[3];
477 __be32 assert_exit_ptr;
478 __be32 assert_callra;
479 __be32 rsvd1[2];
480 __be32 fw_ver;
481 __be32 hw_id;
482 __be32 rsvd2;
483 u8 irisc_index;
484 u8 synd;
78ccb258 485 __be16 ext_synd;
e126ba97
EC		 486};
487
488struct mlx5_init_seg {
489 __be32 fw_rev;
490 __be32 cmdif_rev_fw_sub;
491 __be32 rsvd0[2];
492 __be32 cmdq_addr_h;
493 __be32 cmdq_addr_l_sz;
494 __be32 cmd_dbell;
e3297246
EC		 495 __be32 rsvd1[120];
496 __be32 initializing;
e126ba97 497 struct health_buffer health;
b0844444
EBE		 498 __be32 rsvd2[880];
499 __be32 internal_timer_h;
500 __be32 internal_timer_l;
b368d7cb 501 __be32 rsvd3[2];
e126ba97 502 __be32 health_counter;
b0844444 503 __be32 rsvd4[1019];
e126ba97
EC		 504 __be64 ieee1588_clk;
505 __be32 ieee1588_clk_type;
506 __be32 clr_intx;
507};
508
509struct mlx5_eqe_comp {
510 __be32 reserved[6];
511 __be32 cqn;
512};
513
514struct mlx5_eqe_qp_srq {
e2013b21 515 __be32 reserved1[5];
516 u8 type;
517 u8 reserved2[3];
e126ba97
EC		 518 __be32 qp_srq_n;
519};
520
521struct mlx5_eqe_cq_err {
522 __be32 cqn;
523 u8 reserved1[7];
524 u8 syndrome;
525};
526
e126ba97
EC		 527struct mlx5_eqe_port_state {
528 u8 reserved0[8];
529 u8 port;
530};
531
532struct mlx5_eqe_gpio {
533 __be32 reserved0[2];
534 __be64 gpio_event;
535};
536
537struct mlx5_eqe_congestion {
538 u8 type;
539 u8 rsvd0;
540 u8 congestion_level;
541};
542
543struct mlx5_eqe_stall_vl {
544 u8 rsvd0[3];
545 u8 port_vl;
546};
547
548struct mlx5_eqe_cmd {
549 __be32 vector;
550 __be32 rsvd[6];
551};
552
553struct mlx5_eqe_page_req {
554 u8 rsvd0[2];
555 __be16 func_id;
0a324f31
ML		 556 __be32 num_pages;
557 __be32 rsvd1[5];
e126ba97
EC		 558};
559
e420f0c0
HE		 560struct mlx5_eqe_page_fault {
561 __be32 bytes_committed;
562 union {
563 struct {
564 u16 reserved1;
565 __be16 wqe_index;
566 u16 reserved2;
567 __be16 packet_length;
568 u8 reserved3[12];
569 } __packed wqe;
570 struct {
571 __be32 r_key;
572 u16 reserved1;
573 __be16 packet_length;
574 __be32 rdma_op_len;
575 __be64 rdma_va;
576 } __packed rdma;
577 } __packed;
578 __be32 flags_qpn;
579} __packed;
580
073bb189
SM		 581struct mlx5_eqe_vport_change {
582 u8 rsvd0[2];
583 __be16 vport_num;
584 __be32 rsvd1[6];
585} __packed;
586
e126ba97
EC		 587union ev_data {
588 __be32 raw[7];
589 struct mlx5_eqe_cmd cmd;
590 struct mlx5_eqe_comp comp;
591 struct mlx5_eqe_qp_srq qp_srq;
592 struct mlx5_eqe_cq_err cq_err;
e126ba97
EC		 593 struct mlx5_eqe_port_state port;
594 struct mlx5_eqe_gpio gpio;
595 struct mlx5_eqe_congestion cong;
596 struct mlx5_eqe_stall_vl stall_vl;
597 struct mlx5_eqe_page_req req_pages;
e420f0c0 598 struct mlx5_eqe_page_fault page_fault;
073bb189 599 struct mlx5_eqe_vport_change vport_change;
e126ba97
EC		 600} __packed;
601
602struct mlx5_eqe {
603 u8 rsvd0;
604 u8 type;
605 u8 rsvd1;
606 u8 sub_type;
607 __be32 rsvd2[7];
608 union ev_data data;
609 __be16 rsvd3;
610 u8 signature;
611 u8 owner;
612} __packed;
613
614struct mlx5_cmd_prot_block {
615 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
616 u8 rsvd0[48];
617 __be64 next;
618 __be32 block_num;
619 u8 rsvd1;
620 u8 token;
621 u8 ctrl_sig;
622 u8 sig;
623};
624
e281682b
SM		 625enum {
626 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
627};
628
e126ba97
EC		 629struct mlx5_err_cqe {
630 u8 rsvd0[32];
631 __be32 srqn;
632 u8 rsvd1[18];
633 u8 vendor_err_synd;
634 u8 syndrome;
635 __be32 s_wqe_opcode_qpn;
636 __be16 wqe_counter;
637 u8 signature;
638 u8 op_own;
639};
640
641struct mlx5_cqe64 {
1b223dd3
SM		 642 u8 outer_l3_tunneled;
643 u8 rsvd0;
644 __be16 wqe_id;
e281682b
SM		 645 u8 lro_tcppsh_abort_dupack;
646 u8 lro_min_ttl;
647 __be16 lro_tcp_win;
648 __be32 lro_ack_seq_num;
649 __be32 rss_hash_result;
650 u8 rss_hash_type;
e126ba97 651 u8 ml_path;
e281682b
SM		 652 u8 rsvd20[2];
653 __be16 check_sum;
e126ba97
EC		 654 __be16 slid;
655 __be32 flags_rqpn;
e281682b 656 u8 hds_ip_ext;
1b223dd3 657 u8 l4_l3_hdr_type;
e281682b
SM		 658 __be16 vlan_info;
659 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
e126ba97
EC		 660 __be32 imm_inval_pkey;
661 u8 rsvd40[4];
662 __be32 byte_cnt;
b0844444
EBE		 663 __be32 timestamp_h;
664 __be32 timestamp_l;
e126ba97
EC		 665 __be32 sop_drop_qpn;
666 __be16 wqe_counter;
667 u8 signature;
668 u8 op_own;
669};
670
7219ab34
TT		 671struct mlx5_mini_cqe8 {
672 union {
673 __be32 rx_hash_result;
674 struct {
675 __be16 checksum;
676 __be16 rsvd;
677 };
678 struct {
679 __be16 wqe_counter;
680 u8 s_wqe_opcode;
681 u8 reserved;
682 } s_wqe_info;
683 };
684 __be32 byte_cnt;
685};
686
687enum {
688 MLX5_NO_INLINE_DATA,
689 MLX5_INLINE_DATA32_SEG,
690 MLX5_INLINE_DATA64_SEG,
691 MLX5_COMPRESSED,
692};
693
694enum {
695 MLX5_CQE_FORMAT_CSUM = 0x1,
696};
697
698#define MLX5_MINI_CQE_ARRAY_SIZE 8
699
700static inline int mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
701{
702 return (cqe->op_own >> 2) & 0x3;
703}
704
e281682b
SM		 705static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
706{
707 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
708}
709
710static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
711{
1b223dd3
SM		 712 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
713}
714
715static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
716{
717 return (cqe->l4_l3_hdr_type >> 2) & 0x3;
718}
719
720static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe)
721{
722 return cqe->outer_l3_tunneled & 0x1;
e281682b
SM		 723}
724
725static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
726{
1b223dd3 727 return !!(cqe->l4_l3_hdr_type & 0x1);
e281682b
SM		 728}
729
b0844444
EBE		 730static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
731{
732 u32 hi, lo;
733
734 hi = be32_to_cpu(cqe->timestamp_h);
735 lo = be32_to_cpu(cqe->timestamp_l);
736
737 return (u64)lo | ((u64)hi << 32);
738}
739
461017cb
TT		 740struct mpwrq_cqe_bc {
741 __be16 filler_consumed_strides;
742 __be16 byte_cnt;
743};
744
745static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
746{
747 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
748
749 return be16_to_cpu(bc->byte_cnt);
750}
751
752static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
753{
754 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
755}
756
757static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
758{
759 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
760
761 return mpwrq_get_cqe_bc_consumed_strides(bc);
762}
763
764static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
765{
766 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
767
768 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
769}
770
771static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
772{
773 return be16_to_cpu(cqe->wqe_counter);
774}
775
e281682b
SM		 776enum {
777 CQE_L4_HDR_TYPE_NONE = 0x0,
778 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
779 CQE_L4_HDR_TYPE_UDP = 0x2,
780 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
781 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
782};
783
784enum {
785 CQE_RSS_HTYPE_IP = 0x3 << 6,
786 CQE_RSS_HTYPE_L4 = 0x3 << 2,
787};
788
cb34be6d
AS		 789enum {
790 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
791 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
792 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
793};
794
e281682b
SM		 795enum {
796 CQE_L2_OK = 1 << 0,
797 CQE_L3_OK = 1 << 1,
798 CQE_L4_OK = 1 << 2,
799};
800
d5436ba0
SG		 801struct mlx5_sig_err_cqe {
802 u8 rsvd0[16];
803 __be32 expected_trans_sig;
804 __be32 actual_trans_sig;
805 __be32 expected_reftag;
806 __be32 actual_reftag;
807 __be16 syndrome;
808 u8 rsvd22[2];
809 __be32 mkey;
810 __be64 err_offset;
811 u8 rsvd30[8];
812 __be32 qpn;
813 u8 rsvd38[2];
814 u8 signature;
815 u8 op_own;
816};
817
e126ba97
EC		 818struct mlx5_wqe_srq_next_seg {
819 u8 rsvd0[2];
820 __be16 next_wqe_index;
821 u8 signature;
822 u8 rsvd1[11];
823};
824
825union mlx5_ext_cqe {
826 struct ib_grh grh;
827 u8 inl[64];
828};
829
830struct mlx5_cqe128 {
831 union mlx5_ext_cqe inl_grh;
832 struct mlx5_cqe64 cqe64;
833};
834
835struct mlx5_srq_ctx {
836 u8 state_log_sz;
837 u8 rsvd0[3];
838 __be32 flags_xrcd;
839 __be32 pgoff_cqn;
840 u8 rsvd1[4];
841 u8 log_pg_sz;
842 u8 rsvd2[7];
843 __be32 pd;
844 __be16 lwm;
845 __be16 wqe_cnt;
846 u8 rsvd3[8];
847 __be64 db_record;
848};
849
850struct mlx5_create_srq_mbox_in {
851 struct mlx5_inbox_hdr hdr;
852 __be32 input_srqn;
853 u8 rsvd0[4];
854 struct mlx5_srq_ctx ctx;
855 u8 rsvd1[208];
856 __be64 pas[0];
857};
858
859struct mlx5_create_srq_mbox_out {
860 struct mlx5_outbox_hdr hdr;
861 __be32 srqn;
862 u8 rsvd[4];
863};
864
865struct mlx5_destroy_srq_mbox_in {
866 struct mlx5_inbox_hdr hdr;
867 __be32 srqn;
868 u8 rsvd[4];
869};
870
871struct mlx5_destroy_srq_mbox_out {
872 struct mlx5_outbox_hdr hdr;
873 u8 rsvd[8];
874};
875
876struct mlx5_query_srq_mbox_in {
877 struct mlx5_inbox_hdr hdr;
878 __be32 srqn;
879 u8 rsvd0[4];
880};
881
882struct mlx5_query_srq_mbox_out {
883 struct mlx5_outbox_hdr hdr;
884 u8 rsvd0[8];
885 struct mlx5_srq_ctx ctx;
886 u8 rsvd1[32];
887 __be64 pas[0];
888};
889
890struct mlx5_arm_srq_mbox_in {
891 struct mlx5_inbox_hdr hdr;
892 __be32 srqn;
893 __be16 rsvd;
894 __be16 lwm;
895};
896
897struct mlx5_arm_srq_mbox_out {
898 struct mlx5_outbox_hdr hdr;
899 u8 rsvd[8];
900};
901
cd23b14b
EC		 902struct mlx5_enable_hca_mbox_in {
903 struct mlx5_inbox_hdr hdr;
904 u8 rsvd[8];
905};
906
907struct mlx5_enable_hca_mbox_out {
908 struct mlx5_outbox_hdr hdr;
909 u8 rsvd[8];
910};
911
912struct mlx5_disable_hca_mbox_in {
913 struct mlx5_inbox_hdr hdr;
914 u8 rsvd[8];
915};
916
917struct mlx5_disable_hca_mbox_out {
918 struct mlx5_outbox_hdr hdr;
919 u8 rsvd[8];
920};
921
968e78dd
HE		 922enum {
923 MLX5_MKEY_STATUS_FREE = 1 << 6,
924};
925
e126ba97
EC		 926struct mlx5_mkey_seg {
927 /* This is a two bit field occupying bits 31-30.
928 * bit 31 is always 0,
929 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
930 */
931 u8 status;
932 u8 pcie_control;
933 u8 flags;
934 u8 version;
935 __be32 qpn_mkey7_0;
936 u8 rsvd1[4];
937 __be32 flags_pd;
938 __be64 start_addr;
939 __be64 len;
940 __be32 bsfs_octo_size;
941 u8 rsvd2[16];
942 __be32 xlt_oct_size;
943 u8 rsvd3[3];
944 u8 log2_page_size;
945 u8 rsvd4[4];
946};
947
948struct mlx5_query_special_ctxs_mbox_in {
949 struct mlx5_inbox_hdr hdr;
950 u8 rsvd[8];
951};
952
953struct mlx5_query_special_ctxs_mbox_out {
954 struct mlx5_outbox_hdr hdr;
955 __be32 dump_fill_mkey;
956 __be32 reserved_lkey;
957};
958
959struct mlx5_create_mkey_mbox_in {
960 struct mlx5_inbox_hdr hdr;
961 __be32 input_mkey_index;
e420f0c0 962 __be32 flags;
e126ba97
EC		 963 struct mlx5_mkey_seg seg;
964 u8 rsvd1[16];
965 __be32 xlat_oct_act_size;
8c8a4914
EC		 966 __be32 rsvd2;
967 u8 rsvd3[168];
e126ba97
EC		 968 __be64 pas[0];
969};
970
971struct mlx5_create_mkey_mbox_out {
972 struct mlx5_outbox_hdr hdr;
973 __be32 mkey;
974 u8 rsvd[4];
975};
976
977struct mlx5_destroy_mkey_mbox_in {
978 struct mlx5_inbox_hdr hdr;
979 __be32 mkey;
980 u8 rsvd[4];
981};
982
983struct mlx5_destroy_mkey_mbox_out {
984 struct mlx5_outbox_hdr hdr;
985 u8 rsvd[8];
986};
987
988struct mlx5_query_mkey_mbox_in {
989 struct mlx5_inbox_hdr hdr;
990 __be32 mkey;
991};
992
993struct mlx5_query_mkey_mbox_out {
994 struct mlx5_outbox_hdr hdr;
995 __be64 pas[0];
996};
997
998struct mlx5_modify_mkey_mbox_in {
999 struct mlx5_inbox_hdr hdr;
1000 __be32 mkey;
1001 __be64 pas[0];
1002};
1003
1004struct mlx5_modify_mkey_mbox_out {
1005 struct mlx5_outbox_hdr hdr;
3bdb31f6 1006 u8 rsvd[8];
e126ba97
EC		 1007};
1008
1009struct mlx5_dump_mkey_mbox_in {
1010 struct mlx5_inbox_hdr hdr;
1011};
1012
1013struct mlx5_dump_mkey_mbox_out {
1014 struct mlx5_outbox_hdr hdr;
1015 __be32 mkey;
1016};
1017
e126ba97
EC		 1018#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1019
1020enum {
1021 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1022};
1023
3121e3c4
SG		 1024struct mlx5_allocate_psv_in {
1025 struct mlx5_inbox_hdr hdr;
1026 __be32 npsv_pd;
1027 __be32 rsvd_psv0;
1028};
1029
1030struct mlx5_allocate_psv_out {
1031 struct mlx5_outbox_hdr hdr;
1032 u8 rsvd[8];
1033 __be32 psv_idx[4];
1034};
1035
1036struct mlx5_destroy_psv_in {
1037 struct mlx5_inbox_hdr hdr;
1038 __be32 psv_number;
1039 u8 rsvd[4];
1040};
1041
1042struct mlx5_destroy_psv_out {
1043 struct mlx5_outbox_hdr hdr;
1044 u8 rsvd[8];
1045};
1046
e281682b
SM		 1047enum {
1048 VPORT_STATE_DOWN = 0x0,
1049 VPORT_STATE_UP = 0x1,
1050};
1051
81848731
SM		 1052enum {
1053 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
1054 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
1055 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
1056};
1057
e281682b
SM		 1058enum {
1059 MLX5_L3_PROT_TYPE_IPV4 = 0,
1060 MLX5_L3_PROT_TYPE_IPV6 = 1,
1061};
1062
1063enum {
1064 MLX5_L4_PROT_TYPE_TCP = 0,
1065 MLX5_L4_PROT_TYPE_UDP = 1,
1066};
1067
1068enum {
1069 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1070 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1071 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1072 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1073 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1074};
1075
1076enum {
1077 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1078 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1079 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1080
1081};
1082
1083enum {
1084 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1085 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1086};
1087
1088enum {
1089 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1090 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1091 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1092};
1093
e16aea27
SM		 1094enum mlx5_list_type {
1095 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
1096 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
1097 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
1098};
1099
e281682b
SM		 1100enum {
1101 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1102 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1103};
1104
928cfe87
TT		 1105enum mlx5_wol_mode {
1106 MLX5_WOL_DISABLE = 0,
1107 MLX5_WOL_SECURED_MAGIC = 1 << 1,
1108 MLX5_WOL_MAGIC = 1 << 2,
1109 MLX5_WOL_ARP = 1 << 3,
1110 MLX5_WOL_BROADCAST = 1 << 4,
1111 MLX5_WOL_MULTICAST = 1 << 5,
1112 MLX5_WOL_UNICAST = 1 << 6,
1113 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
1114};
1115
938fe83c
SM		 1116/* MLX5 DEV CAPs */
1117
1118/* TODO: EAT.ME */
1119enum mlx5_cap_mode {
1120 HCA_CAP_OPMOD_GET_MAX = 0,
1121 HCA_CAP_OPMOD_GET_CUR = 1,
1122};
1123
1124enum mlx5_cap_type {
1125 MLX5_CAP_GENERAL = 0,
1126 MLX5_CAP_ETHERNET_OFFLOADS,
1127 MLX5_CAP_ODP,
1128 MLX5_CAP_ATOMIC,
1129 MLX5_CAP_ROCE,
1130 MLX5_CAP_IPOIB_OFFLOADS,
1131 MLX5_CAP_EOIB_OFFLOADS,
1132 MLX5_CAP_FLOW_TABLE,
495716b1 1133 MLX5_CAP_ESWITCH_FLOW_TABLE,
d6666753 1134 MLX5_CAP_ESWITCH,
3f0393a5
SG		 1135 MLX5_CAP_RESERVED,
1136 MLX5_CAP_VECTOR_CALC,
1466cc5b 1137 MLX5_CAP_QOS,
938fe83c
SM		 1138 /* NUM OF CAP Types */
1139 MLX5_CAP_NUM
1140};
1141
1142/* GET Dev Caps macros */
1143#define MLX5_CAP_GEN(mdev, cap) \
1144 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1145
1146#define MLX5_CAP_GEN_MAX(mdev, cap) \
1147 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1148
1149#define MLX5_CAP_ETH(mdev, cap) \
1150 MLX5_GET(per_protocol_networking_offload_caps,\
1151 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1152
1153#define MLX5_CAP_ETH_MAX(mdev, cap) \
1154 MLX5_GET(per_protocol_networking_offload_caps,\
1155 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1156
1157#define MLX5_CAP_ROCE(mdev, cap) \
1158 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1159
1160#define MLX5_CAP_ROCE_MAX(mdev, cap) \
1161 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1162
1163#define MLX5_CAP_ATOMIC(mdev, cap) \
1164 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1165
1166#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1167 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1168
1169#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1170 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1171
1172#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1173 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1174
876d634d
MG		 1175#define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1176 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1177
1178#define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1179 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1180
495716b1
SM		 1181#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1182 MLX5_GET(flow_table_eswitch_cap, \
1183 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1184
1185#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1186 MLX5_GET(flow_table_eswitch_cap, \
1187 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1188
1189#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1190 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1191
1192#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1193 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1194
efdc810b
MHY		 1195#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1196 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1197
1198#define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1199 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1200
1201#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1202 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1203
1204#define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1205 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1206
d6666753
SM		 1207#define MLX5_CAP_ESW(mdev, cap) \
1208 MLX5_GET(e_switch_cap, \
1209 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1210
1211#define MLX5_CAP_ESW_MAX(mdev, cap) \
1212 MLX5_GET(e_switch_cap, \
1213 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1214
938fe83c
SM		 1215#define MLX5_CAP_ODP(mdev, cap)\
1216 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1217
3f0393a5
SG		 1218#define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1219 MLX5_GET(vector_calc_cap, \
1220 mdev->hca_caps_cur[MLX5_CAP_VECTOR_CALC], cap)
1221
1466cc5b
YP		 1222#define MLX5_CAP_QOS(mdev, cap)\
1223 MLX5_GET(qos_cap, mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1224
f62b8bb8
AV		 1225enum {
1226 MLX5_CMD_STAT_OK = 0x0,
1227 MLX5_CMD_STAT_INT_ERR = 0x1,
1228 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1229 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1230 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1231 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1232 MLX5_CMD_STAT_RES_BUSY = 0x6,
1233 MLX5_CMD_STAT_LIM_ERR = 0x8,
1234 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1235 MLX5_CMD_STAT_IX_ERR = 0xa,
1236 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1237 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1238 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1239 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1240 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1241 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1242};
1243
efea389d
GP		 1244enum {
1245 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1246 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1247 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1248 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1249 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1250 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1c64bf6f 1251 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
121fcdc8 1252 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1c64bf6f 1253 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
efea389d
GP		 1254};
1255
707c4602
MD		 1256static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1257{
1258 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1259 return 0;
1260 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1261}
1262
35d19011
MG		 1263#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
1264#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
1265#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1266#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1267 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1268 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
4cbdd30e 1269
e126ba97 1270#endif /* MLX5_DEVICE_H */
Linux kernel - Deliverables
This page took 0.314633 seconds and 5 git commands to generate.