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net/mlx5_core: Refactor device capability function
[deliverable/linux.git] / include / linux / mlx5 / device.h
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
e281682b 38#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
d29b796a
EC		 48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
58
59#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
938fe83c
SM		 62#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
63#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
d29b796a
EC		 64#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
65#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
66
67/* insert a value to a struct */
68#define MLX5_SET(typ, p, fld, v) do { \
69 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
70 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
71 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
72 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
73 << __mlx5_dw_bit_off(typ, fld))); \
74} while (0)
75
e281682b
SM		 76#define MLX5_SET_TO_ONES(typ, p, fld) do { \
77 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
78 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
79 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
80 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
81 << __mlx5_dw_bit_off(typ, fld))); \
82} while (0)
83
d29b796a
EC		 84#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
85__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
86__mlx5_mask(typ, fld))
87
88#define MLX5_GET_PR(typ, p, fld) ({ \
89 u32 ___t = MLX5_GET(typ, p, fld); \
90 pr_debug(#fld " = 0x%x\n", ___t); \
91 ___t; \
92})
93
94#define MLX5_SET64(typ, p, fld, v) do { \
95 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
96 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
97 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
98} while (0)
99
100#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
101
707c4602
MD		 102#define MLX5_GET64_PR(typ, p, fld) ({ \
103 u64 ___t = MLX5_GET64(typ, p, fld); \
104 pr_debug(#fld " = 0x%llx\n", ___t); \
105 ___t; \
106})
107
3efd9a11
MY		 108/* Big endian getters */
109#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
110 __mlx5_64_off(typ, fld)))
111
112#define MLX5_GET_BE(type_t, typ, p, fld) ({ \
113 type_t tmp; \
114 switch (sizeof(tmp)) { \
115 case sizeof(u8): \
116 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
117 break; \
118 case sizeof(u16): \
119 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
120 break; \
121 case sizeof(u32): \
122 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
123 break; \
124 case sizeof(u64): \
125 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
126 break; \
127 } \
128 tmp; \
129 })
130
e126ba97
EC		 131enum {
132 MLX5_MAX_COMMANDS = 32,
133 MLX5_CMD_DATA_BLOCK_SIZE = 512,
134 MLX5_PCI_CMD_XPORT = 7,
3121e3c4
SG		 135 MLX5_MKEY_BSF_OCTO_SIZE = 4,
136 MLX5_MAX_PSVS = 4,
e126ba97
EC		 137};
138
139enum {
140 MLX5_EXTENDED_UD_AV = 0x80000000,
141};
142
143enum {
144 MLX5_CQ_STATE_ARMED = 9,
145 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
146 MLX5_CQ_STATE_FIRED = 0xa,
147};
148
149enum {
150 MLX5_STAT_RATE_OFFSET = 5,
151};
152
153enum {
154 MLX5_INLINE_SEG = 0x80000000,
155};
156
fc11fbf9
SM		 157enum {
158 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
159};
160
c7a08ac7
EC		 161enum {
162 MLX5_MIN_PKEY_TABLE_SIZE = 128,
163 MLX5_MAX_LOG_PKEY_TABLE = 5,
164};
165
e420f0c0
HE		 166enum {
167 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
168};
169
170enum {
171 MLX5_PFAULT_SUBTYPE_WQE = 0,
172 MLX5_PFAULT_SUBTYPE_RDMA = 1,
173};
174
e126ba97
EC		 175enum {
176 MLX5_PERM_LOCAL_READ = 1 << 2,
177 MLX5_PERM_LOCAL_WRITE = 1 << 3,
178 MLX5_PERM_REMOTE_READ = 1 << 4,
179 MLX5_PERM_REMOTE_WRITE = 1 << 5,
180 MLX5_PERM_ATOMIC = 1 << 6,
181 MLX5_PERM_UMR_EN = 1 << 7,
182};
183
184enum {
185 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
186 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
187 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
188 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
189 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
190};
191
192enum {
193 MLX5_ACCESS_MODE_PA = 0,
194 MLX5_ACCESS_MODE_MTT = 1,
195 MLX5_ACCESS_MODE_KLM = 2
196};
197
198enum {
199 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
200 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
201 MLX5_MKEY_BSF_EN = 1 << 30,
202 MLX5_MKEY_LEN64 = 1 << 31,
203};
204
205enum {
206 MLX5_EN_RD = (u64)1,
207 MLX5_EN_WR = (u64)2
208};
209
210enum {
c1be5232
EC		 211 MLX5_BF_REGS_PER_PAGE = 4,
212 MLX5_MAX_UAR_PAGES = 1 << 8,
213 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
214 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
e126ba97
EC		 215};
216
217enum {
218 MLX5_MKEY_MASK_LEN = 1ull << 0,
219 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
220 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
221 MLX5_MKEY_MASK_PD = 1ull << 7,
222 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
d5436ba0 223 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
e126ba97
EC		 224 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
225 MLX5_MKEY_MASK_KEY = 1ull << 13,
226 MLX5_MKEY_MASK_QPN = 1ull << 14,
227 MLX5_MKEY_MASK_LR = 1ull << 17,
228 MLX5_MKEY_MASK_LW = 1ull << 18,
229 MLX5_MKEY_MASK_RR = 1ull << 19,
230 MLX5_MKEY_MASK_RW = 1ull << 20,
231 MLX5_MKEY_MASK_A = 1ull << 21,
232 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
233 MLX5_MKEY_MASK_FREE = 1ull << 29,
234};
235
968e78dd
HE		 236enum {
237 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
238
239 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
240 MLX5_UMR_CHECK_FREE = (2 << 5),
241
242 MLX5_UMR_INLINE = (1 << 7),
243};
244
cc149f75
HE		 245#define MLX5_UMR_MTT_ALIGNMENT 0x40
246#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
832a6b06 247#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
cc149f75 248
e2013b21 249#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
250
251enum {
252 MLX5_EVENT_QUEUE_TYPE_QP = 0,
253 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
254 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
255};
256
e126ba97
EC		 257enum mlx5_event {
258 MLX5_EVENT_TYPE_COMP = 0x0,
259
260 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
261 MLX5_EVENT_TYPE_COMM_EST = 0x02,
262 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
263 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
264 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
265
266 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
267 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
268 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
269 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
270 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
271 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
272
273 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
274 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
275 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
276 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
277
278 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
279 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
280
281 MLX5_EVENT_TYPE_CMD = 0x0a,
282 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
e420f0c0
HE		 283
284 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
073bb189 285 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
e126ba97
EC		 286};
287
288enum {
289 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
290 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
291 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
292 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
293 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
294 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
295 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
296};
297
298enum {
e126ba97 299 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
e126ba97
EC		 300 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
301 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
302 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
303 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
f360d88a 304 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
6cb7ff3d 305 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
3bdb31f6 306 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
bde51583 307 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
c7a08ac7 308 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
e126ba97 309 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
c1868b82 310 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
e126ba97
EC		 311};
312
3cca2606
AS		 313enum {
314 MLX5_ROCE_VERSION_1 = 0,
315 MLX5_ROCE_VERSION_2 = 2,
316};
317
318enum {
319 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
320 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
321};
322
323enum {
324 MLX5_ROCE_L3_TYPE_IPV4 = 0,
325 MLX5_ROCE_L3_TYPE_IPV6 = 1,
326};
327
328enum {
329 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
330 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
331};
332
e126ba97
EC		 333enum {
334 MLX5_OPCODE_NOP = 0x00,
335 MLX5_OPCODE_SEND_INVAL = 0x01,
336 MLX5_OPCODE_RDMA_WRITE = 0x08,
337 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
338 MLX5_OPCODE_SEND = 0x0a,
339 MLX5_OPCODE_SEND_IMM = 0x0b,
e281682b 340 MLX5_OPCODE_LSO = 0x0e,
e126ba97
EC		 341 MLX5_OPCODE_RDMA_READ = 0x10,
342 MLX5_OPCODE_ATOMIC_CS = 0x11,
343 MLX5_OPCODE_ATOMIC_FA = 0x12,
344 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
345 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
346 MLX5_OPCODE_BIND_MW = 0x18,
347 MLX5_OPCODE_CONFIG_CMD = 0x1f,
348
349 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
350 MLX5_RECV_OPCODE_SEND = 0x01,
351 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
352 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
353
354 MLX5_CQE_OPCODE_ERROR = 0x1e,
355 MLX5_CQE_OPCODE_RESIZE = 0x16,
356
357 MLX5_OPCODE_SET_PSV = 0x20,
358 MLX5_OPCODE_GET_PSV = 0x21,
359 MLX5_OPCODE_CHECK_PSV = 0x22,
360 MLX5_OPCODE_RGET_PSV = 0x26,
361 MLX5_OPCODE_RCHECK_PSV = 0x27,
362
363 MLX5_OPCODE_UMR = 0x25,
364
365};
366
367enum {
368 MLX5_SET_PORT_RESET_QKEY = 0,
369 MLX5_SET_PORT_GUID0 = 16,
370 MLX5_SET_PORT_NODE_GUID = 17,
371 MLX5_SET_PORT_SYS_GUID = 18,
372 MLX5_SET_PORT_GID_TABLE = 19,
373 MLX5_SET_PORT_PKEY_TABLE = 20,
374};
375
376enum {
377 MLX5_MAX_PAGE_SHIFT = 31
378};
379
1b77d2bd 380enum {
05bdb2ab
EC		 381 MLX5_ADAPTER_PAGE_SHIFT = 12,
382 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
1b77d2bd
EC		 383};
384
87b8de49 385enum {
87b8de49
EC		 386 MLX5_CAP_OFF_CMDIF_CSUM = 46,
387};
388
e126ba97
EC		 389struct mlx5_inbox_hdr {
390 __be16 opcode;
391 u8 rsvd[4];
392 __be16 opmod;
393};
394
395struct mlx5_outbox_hdr {
396 u8 status;
397 u8 rsvd[3];
398 __be32 syndrome;
399};
400
401struct mlx5_cmd_query_adapter_mbox_in {
402 struct mlx5_inbox_hdr hdr;
403 u8 rsvd[8];
404};
405
406struct mlx5_cmd_query_adapter_mbox_out {
407 struct mlx5_outbox_hdr hdr;
408 u8 rsvd0[24];
409 u8 intapin;
410 u8 rsvd1[13];
411 __be16 vsd_vendor_id;
412 u8 vsd[208];
413 u8 vsd_psid[16];
414};
415
e420f0c0
HE		 416enum mlx5_odp_transport_cap_bits {
417 MLX5_ODP_SUPPORT_SEND = 1 << 31,
418 MLX5_ODP_SUPPORT_RECV = 1 << 30,
419 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
420 MLX5_ODP_SUPPORT_READ = 1 << 28,
421};
422
423struct mlx5_odp_caps {
424 char reserved[0x10];
425 struct {
426 __be32 rc_odp_caps;
427 __be32 uc_odp_caps;
428 __be32 ud_odp_caps;
429 } per_transport_caps;
430 char reserved2[0xe4];
431};
432
e126ba97
EC		 433struct mlx5_cmd_init_hca_mbox_in {
434 struct mlx5_inbox_hdr hdr;
435 u8 rsvd0[2];
436 __be16 profile;
437 u8 rsvd1[4];
438};
439
440struct mlx5_cmd_init_hca_mbox_out {
441 struct mlx5_outbox_hdr hdr;
442 u8 rsvd[8];
443};
444
445struct mlx5_cmd_teardown_hca_mbox_in {
446 struct mlx5_inbox_hdr hdr;
447 u8 rsvd0[2];
448 __be16 profile;
449 u8 rsvd1[4];
450};
451
452struct mlx5_cmd_teardown_hca_mbox_out {
453 struct mlx5_outbox_hdr hdr;
454 u8 rsvd[8];
455};
456
457struct mlx5_cmd_layout {
458 u8 type;
459 u8 rsvd0[3];
460 __be32 inlen;
461 __be64 in_ptr;
462 __be32 in[4];
463 __be32 out[4];
464 __be64 out_ptr;
465 __be32 outlen;
466 u8 token;
467 u8 sig;
468 u8 rsvd1;
469 u8 status_own;
470};
471
472
473struct health_buffer {
474 __be32 assert_var[5];
475 __be32 rsvd0[3];
476 __be32 assert_exit_ptr;
477 __be32 assert_callra;
478 __be32 rsvd1[2];
479 __be32 fw_ver;
480 __be32 hw_id;
481 __be32 rsvd2;
482 u8 irisc_index;
483 u8 synd;
78ccb258 484 __be16 ext_synd;
e126ba97
EC		 485};
486
487struct mlx5_init_seg {
488 __be32 fw_rev;
489 __be32 cmdif_rev_fw_sub;
490 __be32 rsvd0[2];
491 __be32 cmdq_addr_h;
492 __be32 cmdq_addr_l_sz;
493 __be32 cmd_dbell;
e3297246
EC		 494 __be32 rsvd1[120];
495 __be32 initializing;
e126ba97 496 struct health_buffer health;
b0844444
EBE		 497 __be32 rsvd2[880];
498 __be32 internal_timer_h;
499 __be32 internal_timer_l;
b368d7cb 500 __be32 rsvd3[2];
e126ba97 501 __be32 health_counter;
b0844444 502 __be32 rsvd4[1019];
e126ba97
EC		 503 __be64 ieee1588_clk;
504 __be32 ieee1588_clk_type;
505 __be32 clr_intx;
506};
507
508struct mlx5_eqe_comp {
509 __be32 reserved[6];
510 __be32 cqn;
511};
512
513struct mlx5_eqe_qp_srq {
e2013b21 514 __be32 reserved1[5];
515 u8 type;
516 u8 reserved2[3];
e126ba97
EC		 517 __be32 qp_srq_n;
518};
519
520struct mlx5_eqe_cq_err {
521 __be32 cqn;
522 u8 reserved1[7];
523 u8 syndrome;
524};
525
e126ba97
EC		 526struct mlx5_eqe_port_state {
527 u8 reserved0[8];
528 u8 port;
529};
530
531struct mlx5_eqe_gpio {
532 __be32 reserved0[2];
533 __be64 gpio_event;
534};
535
536struct mlx5_eqe_congestion {
537 u8 type;
538 u8 rsvd0;
539 u8 congestion_level;
540};
541
542struct mlx5_eqe_stall_vl {
543 u8 rsvd0[3];
544 u8 port_vl;
545};
546
547struct mlx5_eqe_cmd {
548 __be32 vector;
549 __be32 rsvd[6];
550};
551
552struct mlx5_eqe_page_req {
553 u8 rsvd0[2];
554 __be16 func_id;
0a324f31
ML		 555 __be32 num_pages;
556 __be32 rsvd1[5];
e126ba97
EC		 557};
558
e420f0c0
HE		 559struct mlx5_eqe_page_fault {
560 __be32 bytes_committed;
561 union {
562 struct {
563 u16 reserved1;
564 __be16 wqe_index;
565 u16 reserved2;
566 __be16 packet_length;
567 u8 reserved3[12];
568 } __packed wqe;
569 struct {
570 __be32 r_key;
571 u16 reserved1;
572 __be16 packet_length;
573 __be32 rdma_op_len;
574 __be64 rdma_va;
575 } __packed rdma;
576 } __packed;
577 __be32 flags_qpn;
578} __packed;
579
073bb189
SM		 580struct mlx5_eqe_vport_change {
581 u8 rsvd0[2];
582 __be16 vport_num;
583 __be32 rsvd1[6];
584} __packed;
585
e126ba97
EC		 586union ev_data {
587 __be32 raw[7];
588 struct mlx5_eqe_cmd cmd;
589 struct mlx5_eqe_comp comp;
590 struct mlx5_eqe_qp_srq qp_srq;
591 struct mlx5_eqe_cq_err cq_err;
e126ba97
EC		 592 struct mlx5_eqe_port_state port;
593 struct mlx5_eqe_gpio gpio;
594 struct mlx5_eqe_congestion cong;
595 struct mlx5_eqe_stall_vl stall_vl;
596 struct mlx5_eqe_page_req req_pages;
e420f0c0 597 struct mlx5_eqe_page_fault page_fault;
073bb189 598 struct mlx5_eqe_vport_change vport_change;
e126ba97
EC		 599} __packed;
600
601struct mlx5_eqe {
602 u8 rsvd0;
603 u8 type;
604 u8 rsvd1;
605 u8 sub_type;
606 __be32 rsvd2[7];
607 union ev_data data;
608 __be16 rsvd3;
609 u8 signature;
610 u8 owner;
611} __packed;
612
613struct mlx5_cmd_prot_block {
614 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
615 u8 rsvd0[48];
616 __be64 next;
617 __be32 block_num;
618 u8 rsvd1;
619 u8 token;
620 u8 ctrl_sig;
621 u8 sig;
622};
623
e281682b
SM		 624enum {
625 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
626};
627
e126ba97
EC		 628struct mlx5_err_cqe {
629 u8 rsvd0[32];
630 __be32 srqn;
631 u8 rsvd1[18];
632 u8 vendor_err_synd;
633 u8 syndrome;
634 __be32 s_wqe_opcode_qpn;
635 __be16 wqe_counter;
636 u8 signature;
637 u8 op_own;
638};
639
640struct mlx5_cqe64 {
e281682b
SM		 641 u8 rsvd0[4];
642 u8 lro_tcppsh_abort_dupack;
643 u8 lro_min_ttl;
644 __be16 lro_tcp_win;
645 __be32 lro_ack_seq_num;
646 __be32 rss_hash_result;
647 u8 rss_hash_type;
e126ba97 648 u8 ml_path;
e281682b
SM		 649 u8 rsvd20[2];
650 __be16 check_sum;
e126ba97
EC		 651 __be16 slid;
652 __be32 flags_rqpn;
e281682b
SM		 653 u8 hds_ip_ext;
654 u8 l4_hdr_type_etc;
655 __be16 vlan_info;
656 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
e126ba97
EC		 657 __be32 imm_inval_pkey;
658 u8 rsvd40[4];
659 __be32 byte_cnt;
b0844444
EBE		 660 __be32 timestamp_h;
661 __be32 timestamp_l;
e126ba97
EC		 662 __be32 sop_drop_qpn;
663 __be16 wqe_counter;
664 u8 signature;
665 u8 op_own;
666};
667
e281682b
SM		 668static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
669{
670 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
671}
672
673static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
674{
675 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
676}
677
678static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
679{
680 return !!(cqe->l4_hdr_type_etc & 0x1);
681}
682
b0844444
EBE		 683static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
684{
685 u32 hi, lo;
686
687 hi = be32_to_cpu(cqe->timestamp_h);
688 lo = be32_to_cpu(cqe->timestamp_l);
689
690 return (u64)lo | ((u64)hi << 32);
691}
692
e281682b
SM		 693enum {
694 CQE_L4_HDR_TYPE_NONE = 0x0,
695 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
696 CQE_L4_HDR_TYPE_UDP = 0x2,
697 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
698 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
699};
700
701enum {
702 CQE_RSS_HTYPE_IP = 0x3 << 6,
703 CQE_RSS_HTYPE_L4 = 0x3 << 2,
704};
705
cb34be6d
AS		 706enum {
707 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
708 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
709 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
710};
711
e281682b
SM		 712enum {
713 CQE_L2_OK = 1 << 0,
714 CQE_L3_OK = 1 << 1,
715 CQE_L4_OK = 1 << 2,
716};
717
d5436ba0
SG		 718struct mlx5_sig_err_cqe {
719 u8 rsvd0[16];
720 __be32 expected_trans_sig;
721 __be32 actual_trans_sig;
722 __be32 expected_reftag;
723 __be32 actual_reftag;
724 __be16 syndrome;
725 u8 rsvd22[2];
726 __be32 mkey;
727 __be64 err_offset;
728 u8 rsvd30[8];
729 __be32 qpn;
730 u8 rsvd38[2];
731 u8 signature;
732 u8 op_own;
733};
734
e126ba97
EC		 735struct mlx5_wqe_srq_next_seg {
736 u8 rsvd0[2];
737 __be16 next_wqe_index;
738 u8 signature;
739 u8 rsvd1[11];
740};
741
742union mlx5_ext_cqe {
743 struct ib_grh grh;
744 u8 inl[64];
745};
746
747struct mlx5_cqe128 {
748 union mlx5_ext_cqe inl_grh;
749 struct mlx5_cqe64 cqe64;
750};
751
752struct mlx5_srq_ctx {
753 u8 state_log_sz;
754 u8 rsvd0[3];
755 __be32 flags_xrcd;
756 __be32 pgoff_cqn;
757 u8 rsvd1[4];
758 u8 log_pg_sz;
759 u8 rsvd2[7];
760 __be32 pd;
761 __be16 lwm;
762 __be16 wqe_cnt;
763 u8 rsvd3[8];
764 __be64 db_record;
765};
766
767struct mlx5_create_srq_mbox_in {
768 struct mlx5_inbox_hdr hdr;
769 __be32 input_srqn;
770 u8 rsvd0[4];
771 struct mlx5_srq_ctx ctx;
772 u8 rsvd1[208];
773 __be64 pas[0];
774};
775
776struct mlx5_create_srq_mbox_out {
777 struct mlx5_outbox_hdr hdr;
778 __be32 srqn;
779 u8 rsvd[4];
780};
781
782struct mlx5_destroy_srq_mbox_in {
783 struct mlx5_inbox_hdr hdr;
784 __be32 srqn;
785 u8 rsvd[4];
786};
787
788struct mlx5_destroy_srq_mbox_out {
789 struct mlx5_outbox_hdr hdr;
790 u8 rsvd[8];
791};
792
793struct mlx5_query_srq_mbox_in {
794 struct mlx5_inbox_hdr hdr;
795 __be32 srqn;
796 u8 rsvd0[4];
797};
798
799struct mlx5_query_srq_mbox_out {
800 struct mlx5_outbox_hdr hdr;
801 u8 rsvd0[8];
802 struct mlx5_srq_ctx ctx;
803 u8 rsvd1[32];
804 __be64 pas[0];
805};
806
807struct mlx5_arm_srq_mbox_in {
808 struct mlx5_inbox_hdr hdr;
809 __be32 srqn;
810 __be16 rsvd;
811 __be16 lwm;
812};
813
814struct mlx5_arm_srq_mbox_out {
815 struct mlx5_outbox_hdr hdr;
816 u8 rsvd[8];
817};
818
819struct mlx5_cq_context {
820 u8 status;
821 u8 cqe_sz_flags;
822 u8 st;
823 u8 rsvd3;
824 u8 rsvd4[6];
825 __be16 page_offset;
826 __be32 log_sz_usr_page;
827 __be16 cq_period;
828 __be16 cq_max_count;
829 __be16 rsvd20;
830 __be16 c_eqn;
831 u8 log_pg_sz;
832 u8 rsvd25[7];
833 __be32 last_notified_index;
834 __be32 solicit_producer_index;
835 __be32 consumer_counter;
836 __be32 producer_counter;
837 u8 rsvd48[8];
838 __be64 db_record_addr;
839};
840
841struct mlx5_create_cq_mbox_in {
842 struct mlx5_inbox_hdr hdr;
843 __be32 input_cqn;
844 u8 rsvdx[4];
845 struct mlx5_cq_context ctx;
846 u8 rsvd6[192];
847 __be64 pas[0];
848};
849
850struct mlx5_create_cq_mbox_out {
851 struct mlx5_outbox_hdr hdr;
852 __be32 cqn;
853 u8 rsvd0[4];
854};
855
856struct mlx5_destroy_cq_mbox_in {
857 struct mlx5_inbox_hdr hdr;
858 __be32 cqn;
859 u8 rsvd0[4];
860};
861
862struct mlx5_destroy_cq_mbox_out {
863 struct mlx5_outbox_hdr hdr;
864 u8 rsvd0[8];
865};
866
867struct mlx5_query_cq_mbox_in {
868 struct mlx5_inbox_hdr hdr;
869 __be32 cqn;
870 u8 rsvd0[4];
871};
872
873struct mlx5_query_cq_mbox_out {
874 struct mlx5_outbox_hdr hdr;
875 u8 rsvd0[8];
876 struct mlx5_cq_context ctx;
877 u8 rsvd6[16];
878 __be64 pas[0];
879};
880
3bdb31f6
EC		 881struct mlx5_modify_cq_mbox_in {
882 struct mlx5_inbox_hdr hdr;
883 __be32 cqn;
884 __be32 field_select;
885 struct mlx5_cq_context ctx;
886 u8 rsvd[192];
887 __be64 pas[0];
888};
889
890struct mlx5_modify_cq_mbox_out {
891 struct mlx5_outbox_hdr hdr;
bde51583 892 u8 rsvd[8];
3bdb31f6
EC		 893};
894
cd23b14b
EC		 895struct mlx5_enable_hca_mbox_in {
896 struct mlx5_inbox_hdr hdr;
897 u8 rsvd[8];
898};
899
900struct mlx5_enable_hca_mbox_out {
901 struct mlx5_outbox_hdr hdr;
902 u8 rsvd[8];
903};
904
905struct mlx5_disable_hca_mbox_in {
906 struct mlx5_inbox_hdr hdr;
907 u8 rsvd[8];
908};
909
910struct mlx5_disable_hca_mbox_out {
911 struct mlx5_outbox_hdr hdr;
912 u8 rsvd[8];
913};
914
e126ba97
EC		 915struct mlx5_eq_context {
916 u8 status;
917 u8 ec_oi;
918 u8 st;
919 u8 rsvd2[7];
920 __be16 page_pffset;
921 __be32 log_sz_usr_page;
922 u8 rsvd3[7];
923 u8 intr;
924 u8 log_page_size;
925 u8 rsvd4[15];
926 __be32 consumer_counter;
927 __be32 produser_counter;
928 u8 rsvd5[16];
929};
930
931struct mlx5_create_eq_mbox_in {
932 struct mlx5_inbox_hdr hdr;
933 u8 rsvd0[3];
934 u8 input_eqn;
935 u8 rsvd1[4];
936 struct mlx5_eq_context ctx;
937 u8 rsvd2[8];
938 __be64 events_mask;
939 u8 rsvd3[176];
940 __be64 pas[0];
941};
942
943struct mlx5_create_eq_mbox_out {
944 struct mlx5_outbox_hdr hdr;
945 u8 rsvd0[3];
946 u8 eq_number;
947 u8 rsvd1[4];
948};
949
950struct mlx5_destroy_eq_mbox_in {
951 struct mlx5_inbox_hdr hdr;
952 u8 rsvd0[3];
953 u8 eqn;
954 u8 rsvd1[4];
955};
956
957struct mlx5_destroy_eq_mbox_out {
958 struct mlx5_outbox_hdr hdr;
959 u8 rsvd[8];
960};
961
962struct mlx5_map_eq_mbox_in {
963 struct mlx5_inbox_hdr hdr;
964 __be64 mask;
965 u8 mu;
966 u8 rsvd0[2];
967 u8 eqn;
968 u8 rsvd1[24];
969};
970
971struct mlx5_map_eq_mbox_out {
972 struct mlx5_outbox_hdr hdr;
973 u8 rsvd[8];
974};
975
976struct mlx5_query_eq_mbox_in {
977 struct mlx5_inbox_hdr hdr;
978 u8 rsvd0[3];
979 u8 eqn;
980 u8 rsvd1[4];
981};
982
983struct mlx5_query_eq_mbox_out {
984 struct mlx5_outbox_hdr hdr;
985 u8 rsvd[8];
986 struct mlx5_eq_context ctx;
987};
988
968e78dd
HE		 989enum {
990 MLX5_MKEY_STATUS_FREE = 1 << 6,
991};
992
e126ba97
EC		 993struct mlx5_mkey_seg {
994 /* This is a two bit field occupying bits 31-30.
995 * bit 31 is always 0,
996 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
997 */
998 u8 status;
999 u8 pcie_control;
1000 u8 flags;
1001 u8 version;
1002 __be32 qpn_mkey7_0;
1003 u8 rsvd1[4];
1004 __be32 flags_pd;
1005 __be64 start_addr;
1006 __be64 len;
1007 __be32 bsfs_octo_size;
1008 u8 rsvd2[16];
1009 __be32 xlt_oct_size;
1010 u8 rsvd3[3];
1011 u8 log2_page_size;
1012 u8 rsvd4[4];
1013};
1014
1015struct mlx5_query_special_ctxs_mbox_in {
1016 struct mlx5_inbox_hdr hdr;
1017 u8 rsvd[8];
1018};
1019
1020struct mlx5_query_special_ctxs_mbox_out {
1021 struct mlx5_outbox_hdr hdr;
1022 __be32 dump_fill_mkey;
1023 __be32 reserved_lkey;
1024};
1025
1026struct mlx5_create_mkey_mbox_in {
1027 struct mlx5_inbox_hdr hdr;
1028 __be32 input_mkey_index;
e420f0c0 1029 __be32 flags;
e126ba97
EC		 1030 struct mlx5_mkey_seg seg;
1031 u8 rsvd1[16];
1032 __be32 xlat_oct_act_size;
8c8a4914
EC		 1033 __be32 rsvd2;
1034 u8 rsvd3[168];
e126ba97
EC		 1035 __be64 pas[0];
1036};
1037
1038struct mlx5_create_mkey_mbox_out {
1039 struct mlx5_outbox_hdr hdr;
1040 __be32 mkey;
1041 u8 rsvd[4];
1042};
1043
1044struct mlx5_destroy_mkey_mbox_in {
1045 struct mlx5_inbox_hdr hdr;
1046 __be32 mkey;
1047 u8 rsvd[4];
1048};
1049
1050struct mlx5_destroy_mkey_mbox_out {
1051 struct mlx5_outbox_hdr hdr;
1052 u8 rsvd[8];
1053};
1054
1055struct mlx5_query_mkey_mbox_in {
1056 struct mlx5_inbox_hdr hdr;
1057 __be32 mkey;
1058};
1059
1060struct mlx5_query_mkey_mbox_out {
1061 struct mlx5_outbox_hdr hdr;
1062 __be64 pas[0];
1063};
1064
1065struct mlx5_modify_mkey_mbox_in {
1066 struct mlx5_inbox_hdr hdr;
1067 __be32 mkey;
1068 __be64 pas[0];
1069};
1070
1071struct mlx5_modify_mkey_mbox_out {
1072 struct mlx5_outbox_hdr hdr;
3bdb31f6 1073 u8 rsvd[8];
e126ba97
EC		 1074};
1075
1076struct mlx5_dump_mkey_mbox_in {
1077 struct mlx5_inbox_hdr hdr;
1078};
1079
1080struct mlx5_dump_mkey_mbox_out {
1081 struct mlx5_outbox_hdr hdr;
1082 __be32 mkey;
1083};
1084
1085struct mlx5_mad_ifc_mbox_in {
1086 struct mlx5_inbox_hdr hdr;
1087 __be16 remote_lid;
1088 u8 rsvd0;
1089 u8 port;
1090 u8 rsvd1[4];
1091 u8 data[256];
1092};
1093
1094struct mlx5_mad_ifc_mbox_out {
1095 struct mlx5_outbox_hdr hdr;
1096 u8 rsvd[8];
1097 u8 data[256];
1098};
1099
1100struct mlx5_access_reg_mbox_in {
1101 struct mlx5_inbox_hdr hdr;
1102 u8 rsvd0[2];
1103 __be16 register_id;
1104 __be32 arg;
1105 __be32 data[0];
1106};
1107
1108struct mlx5_access_reg_mbox_out {
1109 struct mlx5_outbox_hdr hdr;
1110 u8 rsvd[8];
1111 __be32 data[0];
1112};
1113
1114#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1115
1116enum {
1117 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1118};
1119
3121e3c4
SG		 1120struct mlx5_allocate_psv_in {
1121 struct mlx5_inbox_hdr hdr;
1122 __be32 npsv_pd;
1123 __be32 rsvd_psv0;
1124};
1125
1126struct mlx5_allocate_psv_out {
1127 struct mlx5_outbox_hdr hdr;
1128 u8 rsvd[8];
1129 __be32 psv_idx[4];
1130};
1131
1132struct mlx5_destroy_psv_in {
1133 struct mlx5_inbox_hdr hdr;
1134 __be32 psv_number;
1135 u8 rsvd[4];
1136};
1137
1138struct mlx5_destroy_psv_out {
1139 struct mlx5_outbox_hdr hdr;
1140 u8 rsvd[8];
1141};
1142
e281682b
SM		 1143#define MLX5_CMD_OP_MAX 0x920
1144
1145enum {
1146 VPORT_STATE_DOWN = 0x0,
1147 VPORT_STATE_UP = 0x1,
1148};
1149
81848731
SM		 1150enum {
1151 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
1152 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
1153 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
1154};
1155
e281682b
SM		 1156enum {
1157 MLX5_L3_PROT_TYPE_IPV4 = 0,
1158 MLX5_L3_PROT_TYPE_IPV6 = 1,
1159};
1160
1161enum {
1162 MLX5_L4_PROT_TYPE_TCP = 0,
1163 MLX5_L4_PROT_TYPE_UDP = 1,
1164};
1165
1166enum {
1167 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1168 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1169 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1170 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1171 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1172};
1173
1174enum {
1175 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1176 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1177 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1178
1179};
1180
1181enum {
1182 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1183 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1184};
1185
1186enum {
1187 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1188 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1189 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1190};
1191
e16aea27
SM		 1192enum mlx5_list_type {
1193 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
1194 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
1195 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
1196};
1197
e281682b
SM		 1198enum {
1199 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1200 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1201};
1202
938fe83c
SM		 1203/* MLX5 DEV CAPs */
1204
1205/* TODO: EAT.ME */
1206enum mlx5_cap_mode {
1207 HCA_CAP_OPMOD_GET_MAX = 0,
1208 HCA_CAP_OPMOD_GET_CUR = 1,
1209};
1210
1211enum mlx5_cap_type {
1212 MLX5_CAP_GENERAL = 0,
1213 MLX5_CAP_ETHERNET_OFFLOADS,
1214 MLX5_CAP_ODP,
1215 MLX5_CAP_ATOMIC,
1216 MLX5_CAP_ROCE,
1217 MLX5_CAP_IPOIB_OFFLOADS,
1218 MLX5_CAP_EOIB_OFFLOADS,
1219 MLX5_CAP_FLOW_TABLE,
495716b1 1220 MLX5_CAP_ESWITCH_FLOW_TABLE,
d6666753 1221 MLX5_CAP_ESWITCH,
938fe83c
SM		 1222 /* NUM OF CAP Types */
1223 MLX5_CAP_NUM
1224};
1225
1226/* GET Dev Caps macros */
1227#define MLX5_CAP_GEN(mdev, cap) \
1228 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1229
1230#define MLX5_CAP_GEN_MAX(mdev, cap) \
1231 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1232
1233#define MLX5_CAP_ETH(mdev, cap) \
1234 MLX5_GET(per_protocol_networking_offload_caps,\
1235 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1236
1237#define MLX5_CAP_ETH_MAX(mdev, cap) \
1238 MLX5_GET(per_protocol_networking_offload_caps,\
1239 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1240
1241#define MLX5_CAP_ROCE(mdev, cap) \
1242 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1243
1244#define MLX5_CAP_ROCE_MAX(mdev, cap) \
1245 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1246
1247#define MLX5_CAP_ATOMIC(mdev, cap) \
1248 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1249
1250#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1251 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1252
1253#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1254 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1255
1256#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1257 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1258
495716b1
SM		 1259#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1260 MLX5_GET(flow_table_eswitch_cap, \
1261 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1262
1263#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1264 MLX5_GET(flow_table_eswitch_cap, \
1265 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1266
1267#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1268 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1269
1270#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1271 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1272
d6666753
SM		 1273#define MLX5_CAP_ESW(mdev, cap) \
1274 MLX5_GET(e_switch_cap, \
1275 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1276
1277#define MLX5_CAP_ESW_MAX(mdev, cap) \
1278 MLX5_GET(e_switch_cap, \
1279 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1280
938fe83c
SM		 1281#define MLX5_CAP_ODP(mdev, cap)\
1282 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1283
f62b8bb8
AV		 1284enum {
1285 MLX5_CMD_STAT_OK = 0x0,
1286 MLX5_CMD_STAT_INT_ERR = 0x1,
1287 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1288 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1289 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1290 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1291 MLX5_CMD_STAT_RES_BUSY = 0x6,
1292 MLX5_CMD_STAT_LIM_ERR = 0x8,
1293 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1294 MLX5_CMD_STAT_IX_ERR = 0xa,
1295 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1296 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1297 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1298 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1299 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1300 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1301};
1302
efea389d
GP		 1303enum {
1304 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1305 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1306 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1307 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1308 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1309 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1c64bf6f
MY		 1310 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1311 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
efea389d
GP		 1312};
1313
707c4602
MD		 1314static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1315{
1316 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1317 return 0;
1318 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1319}
1320
35d19011
MG		 1321#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
1322#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
1323#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1324#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1325 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1326 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
4cbdd30e 1327
e126ba97 1328#endif /* MLX5_DEVICE_H */
Linux kernel - Deliverables
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