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e126ba97 EC |
1 | /* |
2 | * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DEVICE_H | |
34 | #define MLX5_DEVICE_H | |
35 | ||
36 | #include <linux/types.h> | |
37 | #include <rdma/ib_verbs.h> | |
38 | ||
39 | #if defined(__LITTLE_ENDIAN) | |
40 | #define MLX5_SET_HOST_ENDIANNESS 0 | |
41 | #elif defined(__BIG_ENDIAN) | |
42 | #define MLX5_SET_HOST_ENDIANNESS 0x80 | |
43 | #else | |
44 | #error Host endianness not defined | |
45 | #endif | |
46 | ||
47 | enum { | |
48 | MLX5_MAX_COMMANDS = 32, | |
49 | MLX5_CMD_DATA_BLOCK_SIZE = 512, | |
50 | MLX5_PCI_CMD_XPORT = 7, | |
51 | }; | |
52 | ||
53 | enum { | |
54 | MLX5_EXTENDED_UD_AV = 0x80000000, | |
55 | }; | |
56 | ||
57 | enum { | |
58 | MLX5_CQ_STATE_ARMED = 9, | |
59 | MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, | |
60 | MLX5_CQ_STATE_FIRED = 0xa, | |
61 | }; | |
62 | ||
63 | enum { | |
64 | MLX5_STAT_RATE_OFFSET = 5, | |
65 | }; | |
66 | ||
67 | enum { | |
68 | MLX5_INLINE_SEG = 0x80000000, | |
69 | }; | |
70 | ||
71 | enum { | |
72 | MLX5_PERM_LOCAL_READ = 1 << 2, | |
73 | MLX5_PERM_LOCAL_WRITE = 1 << 3, | |
74 | MLX5_PERM_REMOTE_READ = 1 << 4, | |
75 | MLX5_PERM_REMOTE_WRITE = 1 << 5, | |
76 | MLX5_PERM_ATOMIC = 1 << 6, | |
77 | MLX5_PERM_UMR_EN = 1 << 7, | |
78 | }; | |
79 | ||
80 | enum { | |
81 | MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, | |
82 | MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, | |
83 | MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, | |
84 | MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, | |
85 | MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, | |
86 | }; | |
87 | ||
88 | enum { | |
89 | MLX5_ACCESS_MODE_PA = 0, | |
90 | MLX5_ACCESS_MODE_MTT = 1, | |
91 | MLX5_ACCESS_MODE_KLM = 2 | |
92 | }; | |
93 | ||
94 | enum { | |
95 | MLX5_MKEY_REMOTE_INVAL = 1 << 24, | |
96 | MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, | |
97 | MLX5_MKEY_BSF_EN = 1 << 30, | |
98 | MLX5_MKEY_LEN64 = 1 << 31, | |
99 | }; | |
100 | ||
101 | enum { | |
102 | MLX5_EN_RD = (u64)1, | |
103 | MLX5_EN_WR = (u64)2 | |
104 | }; | |
105 | ||
106 | enum { | |
107 | MLX5_BF_REGS_PER_PAGE = 4, | |
108 | MLX5_MAX_UAR_PAGES = 1 << 8, | |
109 | MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_BF_REGS_PER_PAGE, | |
110 | }; | |
111 | ||
112 | enum { | |
113 | MLX5_MKEY_MASK_LEN = 1ull << 0, | |
114 | MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, | |
115 | MLX5_MKEY_MASK_START_ADDR = 1ull << 6, | |
116 | MLX5_MKEY_MASK_PD = 1ull << 7, | |
117 | MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, | |
118 | MLX5_MKEY_MASK_BSF_EN = 1ull << 12, | |
119 | MLX5_MKEY_MASK_KEY = 1ull << 13, | |
120 | MLX5_MKEY_MASK_QPN = 1ull << 14, | |
121 | MLX5_MKEY_MASK_LR = 1ull << 17, | |
122 | MLX5_MKEY_MASK_LW = 1ull << 18, | |
123 | MLX5_MKEY_MASK_RR = 1ull << 19, | |
124 | MLX5_MKEY_MASK_RW = 1ull << 20, | |
125 | MLX5_MKEY_MASK_A = 1ull << 21, | |
126 | MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, | |
127 | MLX5_MKEY_MASK_FREE = 1ull << 29, | |
128 | }; | |
129 | ||
130 | enum mlx5_event { | |
131 | MLX5_EVENT_TYPE_COMP = 0x0, | |
132 | ||
133 | MLX5_EVENT_TYPE_PATH_MIG = 0x01, | |
134 | MLX5_EVENT_TYPE_COMM_EST = 0x02, | |
135 | MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, | |
136 | MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, | |
137 | MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, | |
138 | ||
139 | MLX5_EVENT_TYPE_CQ_ERROR = 0x04, | |
140 | MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
141 | MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, | |
142 | MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | |
143 | MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | |
144 | MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | |
145 | ||
146 | MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, | |
147 | MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, | |
148 | MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, | |
149 | MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, | |
150 | ||
151 | MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, | |
152 | MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, | |
153 | ||
154 | MLX5_EVENT_TYPE_CMD = 0x0a, | |
155 | MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, | |
156 | }; | |
157 | ||
158 | enum { | |
159 | MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, | |
160 | MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, | |
161 | MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, | |
162 | MLX5_PORT_CHANGE_SUBTYPE_LID = 6, | |
163 | MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, | |
164 | MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, | |
165 | MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, | |
166 | }; | |
167 | ||
168 | enum { | |
169 | MLX5_DEV_CAP_FLAG_RC = 1LL << 0, | |
170 | MLX5_DEV_CAP_FLAG_UC = 1LL << 1, | |
171 | MLX5_DEV_CAP_FLAG_UD = 1LL << 2, | |
172 | MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, | |
173 | MLX5_DEV_CAP_FLAG_SRQ = 1LL << 6, | |
174 | MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, | |
175 | MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, | |
176 | MLX5_DEV_CAP_FLAG_APM = 1LL << 17, | |
177 | MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, | |
178 | MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, | |
179 | MLX5_DEV_CAP_FLAG_RESIZE_SRQ = 1LL << 32, | |
180 | MLX5_DEV_CAP_FLAG_REMOTE_FENCE = 1LL << 38, | |
181 | MLX5_DEV_CAP_FLAG_TLP_HINTS = 1LL << 39, | |
182 | MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, | |
183 | MLX5_DEV_CAP_FLAG_DCT = 1LL << 41, | |
184 | MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 1LL << 46, | |
185 | }; | |
186 | ||
187 | enum { | |
188 | MLX5_OPCODE_NOP = 0x00, | |
189 | MLX5_OPCODE_SEND_INVAL = 0x01, | |
190 | MLX5_OPCODE_RDMA_WRITE = 0x08, | |
191 | MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, | |
192 | MLX5_OPCODE_SEND = 0x0a, | |
193 | MLX5_OPCODE_SEND_IMM = 0x0b, | |
194 | MLX5_OPCODE_RDMA_READ = 0x10, | |
195 | MLX5_OPCODE_ATOMIC_CS = 0x11, | |
196 | MLX5_OPCODE_ATOMIC_FA = 0x12, | |
197 | MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, | |
198 | MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, | |
199 | MLX5_OPCODE_BIND_MW = 0x18, | |
200 | MLX5_OPCODE_CONFIG_CMD = 0x1f, | |
201 | ||
202 | MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, | |
203 | MLX5_RECV_OPCODE_SEND = 0x01, | |
204 | MLX5_RECV_OPCODE_SEND_IMM = 0x02, | |
205 | MLX5_RECV_OPCODE_SEND_INVAL = 0x03, | |
206 | ||
207 | MLX5_CQE_OPCODE_ERROR = 0x1e, | |
208 | MLX5_CQE_OPCODE_RESIZE = 0x16, | |
209 | ||
210 | MLX5_OPCODE_SET_PSV = 0x20, | |
211 | MLX5_OPCODE_GET_PSV = 0x21, | |
212 | MLX5_OPCODE_CHECK_PSV = 0x22, | |
213 | MLX5_OPCODE_RGET_PSV = 0x26, | |
214 | MLX5_OPCODE_RCHECK_PSV = 0x27, | |
215 | ||
216 | MLX5_OPCODE_UMR = 0x25, | |
217 | ||
218 | }; | |
219 | ||
220 | enum { | |
221 | MLX5_SET_PORT_RESET_QKEY = 0, | |
222 | MLX5_SET_PORT_GUID0 = 16, | |
223 | MLX5_SET_PORT_NODE_GUID = 17, | |
224 | MLX5_SET_PORT_SYS_GUID = 18, | |
225 | MLX5_SET_PORT_GID_TABLE = 19, | |
226 | MLX5_SET_PORT_PKEY_TABLE = 20, | |
227 | }; | |
228 | ||
229 | enum { | |
230 | MLX5_MAX_PAGE_SHIFT = 31 | |
231 | }; | |
232 | ||
233 | struct mlx5_inbox_hdr { | |
234 | __be16 opcode; | |
235 | u8 rsvd[4]; | |
236 | __be16 opmod; | |
237 | }; | |
238 | ||
239 | struct mlx5_outbox_hdr { | |
240 | u8 status; | |
241 | u8 rsvd[3]; | |
242 | __be32 syndrome; | |
243 | }; | |
244 | ||
245 | struct mlx5_cmd_query_adapter_mbox_in { | |
246 | struct mlx5_inbox_hdr hdr; | |
247 | u8 rsvd[8]; | |
248 | }; | |
249 | ||
250 | struct mlx5_cmd_query_adapter_mbox_out { | |
251 | struct mlx5_outbox_hdr hdr; | |
252 | u8 rsvd0[24]; | |
253 | u8 intapin; | |
254 | u8 rsvd1[13]; | |
255 | __be16 vsd_vendor_id; | |
256 | u8 vsd[208]; | |
257 | u8 vsd_psid[16]; | |
258 | }; | |
259 | ||
260 | struct mlx5_hca_cap { | |
261 | u8 rsvd1[16]; | |
262 | u8 log_max_srq_sz; | |
263 | u8 log_max_qp_sz; | |
264 | u8 rsvd2; | |
265 | u8 log_max_qp; | |
266 | u8 log_max_strq_sz; | |
267 | u8 log_max_srqs; | |
268 | u8 rsvd4[2]; | |
269 | u8 rsvd5; | |
270 | u8 log_max_cq_sz; | |
271 | u8 rsvd6; | |
272 | u8 log_max_cq; | |
273 | u8 log_max_eq_sz; | |
274 | u8 log_max_mkey; | |
275 | u8 rsvd7; | |
276 | u8 log_max_eq; | |
277 | u8 max_indirection; | |
278 | u8 log_max_mrw_sz; | |
279 | u8 log_max_bsf_list_sz; | |
280 | u8 log_max_klm_list_sz; | |
281 | u8 rsvd_8_0; | |
282 | u8 log_max_ra_req_dc; | |
283 | u8 rsvd_8_1; | |
284 | u8 log_max_ra_res_dc; | |
285 | u8 rsvd9; | |
286 | u8 log_max_ra_req_qp; | |
287 | u8 rsvd10; | |
288 | u8 log_max_ra_res_qp; | |
289 | u8 rsvd11[4]; | |
290 | __be16 max_qp_count; | |
291 | __be16 rsvd12; | |
292 | u8 rsvd13; | |
293 | u8 local_ca_ack_delay; | |
294 | u8 rsvd14; | |
295 | u8 num_ports; | |
296 | u8 log_max_msg; | |
297 | u8 rsvd15[3]; | |
298 | __be16 stat_rate_support; | |
299 | u8 rsvd16[2]; | |
300 | __be64 flags; | |
301 | u8 rsvd17; | |
302 | u8 uar_sz; | |
303 | u8 rsvd18; | |
304 | u8 log_pg_sz; | |
305 | __be16 bf_log_bf_reg_size; | |
306 | u8 rsvd19[4]; | |
307 | __be16 max_desc_sz_sq; | |
308 | u8 rsvd20[2]; | |
309 | __be16 max_desc_sz_rq; | |
310 | u8 rsvd21[2]; | |
311 | __be16 max_desc_sz_sq_dc; | |
0a324f31 ML |
312 | __be32 max_qp_mcg; |
313 | u8 rsvd22[3]; | |
e126ba97 | 314 | u8 log_max_mcg; |
0a324f31 | 315 | u8 rsvd23; |
e126ba97 | 316 | u8 log_max_pd; |
0a324f31 | 317 | u8 rsvd24; |
e126ba97 | 318 | u8 log_max_xrcd; |
0a324f31 | 319 | u8 rsvd25[42]; |
288dde9f | 320 | __be16 log_uar_page_sz; |
0a324f31 | 321 | u8 rsvd26[28]; |
e126ba97 | 322 | u8 log_msx_atomic_size_qp; |
0a324f31 | 323 | u8 rsvd27[2]; |
e126ba97 | 324 | u8 log_msx_atomic_size_dc; |
0a324f31 | 325 | u8 rsvd28[76]; |
e126ba97 EC |
326 | }; |
327 | ||
328 | ||
329 | struct mlx5_cmd_query_hca_cap_mbox_in { | |
330 | struct mlx5_inbox_hdr hdr; | |
331 | u8 rsvd[8]; | |
332 | }; | |
333 | ||
334 | ||
335 | struct mlx5_cmd_query_hca_cap_mbox_out { | |
336 | struct mlx5_outbox_hdr hdr; | |
337 | u8 rsvd0[8]; | |
338 | struct mlx5_hca_cap hca_cap; | |
339 | }; | |
340 | ||
341 | ||
342 | struct mlx5_cmd_set_hca_cap_mbox_in { | |
343 | struct mlx5_inbox_hdr hdr; | |
344 | u8 rsvd[8]; | |
345 | struct mlx5_hca_cap hca_cap; | |
346 | }; | |
347 | ||
348 | ||
349 | struct mlx5_cmd_set_hca_cap_mbox_out { | |
350 | struct mlx5_outbox_hdr hdr; | |
351 | u8 rsvd0[8]; | |
352 | }; | |
353 | ||
354 | ||
355 | struct mlx5_cmd_init_hca_mbox_in { | |
356 | struct mlx5_inbox_hdr hdr; | |
357 | u8 rsvd0[2]; | |
358 | __be16 profile; | |
359 | u8 rsvd1[4]; | |
360 | }; | |
361 | ||
362 | struct mlx5_cmd_init_hca_mbox_out { | |
363 | struct mlx5_outbox_hdr hdr; | |
364 | u8 rsvd[8]; | |
365 | }; | |
366 | ||
367 | struct mlx5_cmd_teardown_hca_mbox_in { | |
368 | struct mlx5_inbox_hdr hdr; | |
369 | u8 rsvd0[2]; | |
370 | __be16 profile; | |
371 | u8 rsvd1[4]; | |
372 | }; | |
373 | ||
374 | struct mlx5_cmd_teardown_hca_mbox_out { | |
375 | struct mlx5_outbox_hdr hdr; | |
376 | u8 rsvd[8]; | |
377 | }; | |
378 | ||
379 | struct mlx5_cmd_layout { | |
380 | u8 type; | |
381 | u8 rsvd0[3]; | |
382 | __be32 inlen; | |
383 | __be64 in_ptr; | |
384 | __be32 in[4]; | |
385 | __be32 out[4]; | |
386 | __be64 out_ptr; | |
387 | __be32 outlen; | |
388 | u8 token; | |
389 | u8 sig; | |
390 | u8 rsvd1; | |
391 | u8 status_own; | |
392 | }; | |
393 | ||
394 | ||
395 | struct health_buffer { | |
396 | __be32 assert_var[5]; | |
397 | __be32 rsvd0[3]; | |
398 | __be32 assert_exit_ptr; | |
399 | __be32 assert_callra; | |
400 | __be32 rsvd1[2]; | |
401 | __be32 fw_ver; | |
402 | __be32 hw_id; | |
403 | __be32 rsvd2; | |
404 | u8 irisc_index; | |
405 | u8 synd; | |
406 | __be16 ext_sync; | |
407 | }; | |
408 | ||
409 | struct mlx5_init_seg { | |
410 | __be32 fw_rev; | |
411 | __be32 cmdif_rev_fw_sub; | |
412 | __be32 rsvd0[2]; | |
413 | __be32 cmdq_addr_h; | |
414 | __be32 cmdq_addr_l_sz; | |
415 | __be32 cmd_dbell; | |
416 | __be32 rsvd1[121]; | |
417 | struct health_buffer health; | |
418 | __be32 rsvd2[884]; | |
419 | __be32 health_counter; | |
420 | __be32 rsvd3[1023]; | |
421 | __be64 ieee1588_clk; | |
422 | __be32 ieee1588_clk_type; | |
423 | __be32 clr_intx; | |
424 | }; | |
425 | ||
426 | struct mlx5_eqe_comp { | |
427 | __be32 reserved[6]; | |
428 | __be32 cqn; | |
429 | }; | |
430 | ||
431 | struct mlx5_eqe_qp_srq { | |
432 | __be32 reserved[6]; | |
433 | __be32 qp_srq_n; | |
434 | }; | |
435 | ||
436 | struct mlx5_eqe_cq_err { | |
437 | __be32 cqn; | |
438 | u8 reserved1[7]; | |
439 | u8 syndrome; | |
440 | }; | |
441 | ||
442 | struct mlx5_eqe_dropped_packet { | |
443 | }; | |
444 | ||
445 | struct mlx5_eqe_port_state { | |
446 | u8 reserved0[8]; | |
447 | u8 port; | |
448 | }; | |
449 | ||
450 | struct mlx5_eqe_gpio { | |
451 | __be32 reserved0[2]; | |
452 | __be64 gpio_event; | |
453 | }; | |
454 | ||
455 | struct mlx5_eqe_congestion { | |
456 | u8 type; | |
457 | u8 rsvd0; | |
458 | u8 congestion_level; | |
459 | }; | |
460 | ||
461 | struct mlx5_eqe_stall_vl { | |
462 | u8 rsvd0[3]; | |
463 | u8 port_vl; | |
464 | }; | |
465 | ||
466 | struct mlx5_eqe_cmd { | |
467 | __be32 vector; | |
468 | __be32 rsvd[6]; | |
469 | }; | |
470 | ||
471 | struct mlx5_eqe_page_req { | |
472 | u8 rsvd0[2]; | |
473 | __be16 func_id; | |
0a324f31 ML |
474 | __be32 num_pages; |
475 | __be32 rsvd1[5]; | |
e126ba97 EC |
476 | }; |
477 | ||
478 | union ev_data { | |
479 | __be32 raw[7]; | |
480 | struct mlx5_eqe_cmd cmd; | |
481 | struct mlx5_eqe_comp comp; | |
482 | struct mlx5_eqe_qp_srq qp_srq; | |
483 | struct mlx5_eqe_cq_err cq_err; | |
484 | struct mlx5_eqe_dropped_packet dp; | |
485 | struct mlx5_eqe_port_state port; | |
486 | struct mlx5_eqe_gpio gpio; | |
487 | struct mlx5_eqe_congestion cong; | |
488 | struct mlx5_eqe_stall_vl stall_vl; | |
489 | struct mlx5_eqe_page_req req_pages; | |
490 | } __packed; | |
491 | ||
492 | struct mlx5_eqe { | |
493 | u8 rsvd0; | |
494 | u8 type; | |
495 | u8 rsvd1; | |
496 | u8 sub_type; | |
497 | __be32 rsvd2[7]; | |
498 | union ev_data data; | |
499 | __be16 rsvd3; | |
500 | u8 signature; | |
501 | u8 owner; | |
502 | } __packed; | |
503 | ||
504 | struct mlx5_cmd_prot_block { | |
505 | u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; | |
506 | u8 rsvd0[48]; | |
507 | __be64 next; | |
508 | __be32 block_num; | |
509 | u8 rsvd1; | |
510 | u8 token; | |
511 | u8 ctrl_sig; | |
512 | u8 sig; | |
513 | }; | |
514 | ||
515 | struct mlx5_err_cqe { | |
516 | u8 rsvd0[32]; | |
517 | __be32 srqn; | |
518 | u8 rsvd1[18]; | |
519 | u8 vendor_err_synd; | |
520 | u8 syndrome; | |
521 | __be32 s_wqe_opcode_qpn; | |
522 | __be16 wqe_counter; | |
523 | u8 signature; | |
524 | u8 op_own; | |
525 | }; | |
526 | ||
527 | struct mlx5_cqe64 { | |
528 | u8 rsvd0[17]; | |
529 | u8 ml_path; | |
530 | u8 rsvd20[4]; | |
531 | __be16 slid; | |
532 | __be32 flags_rqpn; | |
533 | u8 rsvd28[4]; | |
534 | __be32 srqn; | |
535 | __be32 imm_inval_pkey; | |
536 | u8 rsvd40[4]; | |
537 | __be32 byte_cnt; | |
538 | __be64 timestamp; | |
539 | __be32 sop_drop_qpn; | |
540 | __be16 wqe_counter; | |
541 | u8 signature; | |
542 | u8 op_own; | |
543 | }; | |
544 | ||
545 | struct mlx5_wqe_srq_next_seg { | |
546 | u8 rsvd0[2]; | |
547 | __be16 next_wqe_index; | |
548 | u8 signature; | |
549 | u8 rsvd1[11]; | |
550 | }; | |
551 | ||
552 | union mlx5_ext_cqe { | |
553 | struct ib_grh grh; | |
554 | u8 inl[64]; | |
555 | }; | |
556 | ||
557 | struct mlx5_cqe128 { | |
558 | union mlx5_ext_cqe inl_grh; | |
559 | struct mlx5_cqe64 cqe64; | |
560 | }; | |
561 | ||
562 | struct mlx5_srq_ctx { | |
563 | u8 state_log_sz; | |
564 | u8 rsvd0[3]; | |
565 | __be32 flags_xrcd; | |
566 | __be32 pgoff_cqn; | |
567 | u8 rsvd1[4]; | |
568 | u8 log_pg_sz; | |
569 | u8 rsvd2[7]; | |
570 | __be32 pd; | |
571 | __be16 lwm; | |
572 | __be16 wqe_cnt; | |
573 | u8 rsvd3[8]; | |
574 | __be64 db_record; | |
575 | }; | |
576 | ||
577 | struct mlx5_create_srq_mbox_in { | |
578 | struct mlx5_inbox_hdr hdr; | |
579 | __be32 input_srqn; | |
580 | u8 rsvd0[4]; | |
581 | struct mlx5_srq_ctx ctx; | |
582 | u8 rsvd1[208]; | |
583 | __be64 pas[0]; | |
584 | }; | |
585 | ||
586 | struct mlx5_create_srq_mbox_out { | |
587 | struct mlx5_outbox_hdr hdr; | |
588 | __be32 srqn; | |
589 | u8 rsvd[4]; | |
590 | }; | |
591 | ||
592 | struct mlx5_destroy_srq_mbox_in { | |
593 | struct mlx5_inbox_hdr hdr; | |
594 | __be32 srqn; | |
595 | u8 rsvd[4]; | |
596 | }; | |
597 | ||
598 | struct mlx5_destroy_srq_mbox_out { | |
599 | struct mlx5_outbox_hdr hdr; | |
600 | u8 rsvd[8]; | |
601 | }; | |
602 | ||
603 | struct mlx5_query_srq_mbox_in { | |
604 | struct mlx5_inbox_hdr hdr; | |
605 | __be32 srqn; | |
606 | u8 rsvd0[4]; | |
607 | }; | |
608 | ||
609 | struct mlx5_query_srq_mbox_out { | |
610 | struct mlx5_outbox_hdr hdr; | |
611 | u8 rsvd0[8]; | |
612 | struct mlx5_srq_ctx ctx; | |
613 | u8 rsvd1[32]; | |
614 | __be64 pas[0]; | |
615 | }; | |
616 | ||
617 | struct mlx5_arm_srq_mbox_in { | |
618 | struct mlx5_inbox_hdr hdr; | |
619 | __be32 srqn; | |
620 | __be16 rsvd; | |
621 | __be16 lwm; | |
622 | }; | |
623 | ||
624 | struct mlx5_arm_srq_mbox_out { | |
625 | struct mlx5_outbox_hdr hdr; | |
626 | u8 rsvd[8]; | |
627 | }; | |
628 | ||
629 | struct mlx5_cq_context { | |
630 | u8 status; | |
631 | u8 cqe_sz_flags; | |
632 | u8 st; | |
633 | u8 rsvd3; | |
634 | u8 rsvd4[6]; | |
635 | __be16 page_offset; | |
636 | __be32 log_sz_usr_page; | |
637 | __be16 cq_period; | |
638 | __be16 cq_max_count; | |
639 | __be16 rsvd20; | |
640 | __be16 c_eqn; | |
641 | u8 log_pg_sz; | |
642 | u8 rsvd25[7]; | |
643 | __be32 last_notified_index; | |
644 | __be32 solicit_producer_index; | |
645 | __be32 consumer_counter; | |
646 | __be32 producer_counter; | |
647 | u8 rsvd48[8]; | |
648 | __be64 db_record_addr; | |
649 | }; | |
650 | ||
651 | struct mlx5_create_cq_mbox_in { | |
652 | struct mlx5_inbox_hdr hdr; | |
653 | __be32 input_cqn; | |
654 | u8 rsvdx[4]; | |
655 | struct mlx5_cq_context ctx; | |
656 | u8 rsvd6[192]; | |
657 | __be64 pas[0]; | |
658 | }; | |
659 | ||
660 | struct mlx5_create_cq_mbox_out { | |
661 | struct mlx5_outbox_hdr hdr; | |
662 | __be32 cqn; | |
663 | u8 rsvd0[4]; | |
664 | }; | |
665 | ||
666 | struct mlx5_destroy_cq_mbox_in { | |
667 | struct mlx5_inbox_hdr hdr; | |
668 | __be32 cqn; | |
669 | u8 rsvd0[4]; | |
670 | }; | |
671 | ||
672 | struct mlx5_destroy_cq_mbox_out { | |
673 | struct mlx5_outbox_hdr hdr; | |
674 | u8 rsvd0[8]; | |
675 | }; | |
676 | ||
677 | struct mlx5_query_cq_mbox_in { | |
678 | struct mlx5_inbox_hdr hdr; | |
679 | __be32 cqn; | |
680 | u8 rsvd0[4]; | |
681 | }; | |
682 | ||
683 | struct mlx5_query_cq_mbox_out { | |
684 | struct mlx5_outbox_hdr hdr; | |
685 | u8 rsvd0[8]; | |
686 | struct mlx5_cq_context ctx; | |
687 | u8 rsvd6[16]; | |
688 | __be64 pas[0]; | |
689 | }; | |
690 | ||
cd23b14b EC |
691 | struct mlx5_enable_hca_mbox_in { |
692 | struct mlx5_inbox_hdr hdr; | |
693 | u8 rsvd[8]; | |
694 | }; | |
695 | ||
696 | struct mlx5_enable_hca_mbox_out { | |
697 | struct mlx5_outbox_hdr hdr; | |
698 | u8 rsvd[8]; | |
699 | }; | |
700 | ||
701 | struct mlx5_disable_hca_mbox_in { | |
702 | struct mlx5_inbox_hdr hdr; | |
703 | u8 rsvd[8]; | |
704 | }; | |
705 | ||
706 | struct mlx5_disable_hca_mbox_out { | |
707 | struct mlx5_outbox_hdr hdr; | |
708 | u8 rsvd[8]; | |
709 | }; | |
710 | ||
e126ba97 EC |
711 | struct mlx5_eq_context { |
712 | u8 status; | |
713 | u8 ec_oi; | |
714 | u8 st; | |
715 | u8 rsvd2[7]; | |
716 | __be16 page_pffset; | |
717 | __be32 log_sz_usr_page; | |
718 | u8 rsvd3[7]; | |
719 | u8 intr; | |
720 | u8 log_page_size; | |
721 | u8 rsvd4[15]; | |
722 | __be32 consumer_counter; | |
723 | __be32 produser_counter; | |
724 | u8 rsvd5[16]; | |
725 | }; | |
726 | ||
727 | struct mlx5_create_eq_mbox_in { | |
728 | struct mlx5_inbox_hdr hdr; | |
729 | u8 rsvd0[3]; | |
730 | u8 input_eqn; | |
731 | u8 rsvd1[4]; | |
732 | struct mlx5_eq_context ctx; | |
733 | u8 rsvd2[8]; | |
734 | __be64 events_mask; | |
735 | u8 rsvd3[176]; | |
736 | __be64 pas[0]; | |
737 | }; | |
738 | ||
739 | struct mlx5_create_eq_mbox_out { | |
740 | struct mlx5_outbox_hdr hdr; | |
741 | u8 rsvd0[3]; | |
742 | u8 eq_number; | |
743 | u8 rsvd1[4]; | |
744 | }; | |
745 | ||
746 | struct mlx5_destroy_eq_mbox_in { | |
747 | struct mlx5_inbox_hdr hdr; | |
748 | u8 rsvd0[3]; | |
749 | u8 eqn; | |
750 | u8 rsvd1[4]; | |
751 | }; | |
752 | ||
753 | struct mlx5_destroy_eq_mbox_out { | |
754 | struct mlx5_outbox_hdr hdr; | |
755 | u8 rsvd[8]; | |
756 | }; | |
757 | ||
758 | struct mlx5_map_eq_mbox_in { | |
759 | struct mlx5_inbox_hdr hdr; | |
760 | __be64 mask; | |
761 | u8 mu; | |
762 | u8 rsvd0[2]; | |
763 | u8 eqn; | |
764 | u8 rsvd1[24]; | |
765 | }; | |
766 | ||
767 | struct mlx5_map_eq_mbox_out { | |
768 | struct mlx5_outbox_hdr hdr; | |
769 | u8 rsvd[8]; | |
770 | }; | |
771 | ||
772 | struct mlx5_query_eq_mbox_in { | |
773 | struct mlx5_inbox_hdr hdr; | |
774 | u8 rsvd0[3]; | |
775 | u8 eqn; | |
776 | u8 rsvd1[4]; | |
777 | }; | |
778 | ||
779 | struct mlx5_query_eq_mbox_out { | |
780 | struct mlx5_outbox_hdr hdr; | |
781 | u8 rsvd[8]; | |
782 | struct mlx5_eq_context ctx; | |
783 | }; | |
784 | ||
785 | struct mlx5_mkey_seg { | |
786 | /* This is a two bit field occupying bits 31-30. | |
787 | * bit 31 is always 0, | |
788 | * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation | |
789 | */ | |
790 | u8 status; | |
791 | u8 pcie_control; | |
792 | u8 flags; | |
793 | u8 version; | |
794 | __be32 qpn_mkey7_0; | |
795 | u8 rsvd1[4]; | |
796 | __be32 flags_pd; | |
797 | __be64 start_addr; | |
798 | __be64 len; | |
799 | __be32 bsfs_octo_size; | |
800 | u8 rsvd2[16]; | |
801 | __be32 xlt_oct_size; | |
802 | u8 rsvd3[3]; | |
803 | u8 log2_page_size; | |
804 | u8 rsvd4[4]; | |
805 | }; | |
806 | ||
807 | struct mlx5_query_special_ctxs_mbox_in { | |
808 | struct mlx5_inbox_hdr hdr; | |
809 | u8 rsvd[8]; | |
810 | }; | |
811 | ||
812 | struct mlx5_query_special_ctxs_mbox_out { | |
813 | struct mlx5_outbox_hdr hdr; | |
814 | __be32 dump_fill_mkey; | |
815 | __be32 reserved_lkey; | |
816 | }; | |
817 | ||
818 | struct mlx5_create_mkey_mbox_in { | |
819 | struct mlx5_inbox_hdr hdr; | |
820 | __be32 input_mkey_index; | |
821 | u8 rsvd0[4]; | |
822 | struct mlx5_mkey_seg seg; | |
823 | u8 rsvd1[16]; | |
824 | __be32 xlat_oct_act_size; | |
825 | __be32 bsf_coto_act_size; | |
826 | u8 rsvd2[168]; | |
827 | __be64 pas[0]; | |
828 | }; | |
829 | ||
830 | struct mlx5_create_mkey_mbox_out { | |
831 | struct mlx5_outbox_hdr hdr; | |
832 | __be32 mkey; | |
833 | u8 rsvd[4]; | |
834 | }; | |
835 | ||
836 | struct mlx5_destroy_mkey_mbox_in { | |
837 | struct mlx5_inbox_hdr hdr; | |
838 | __be32 mkey; | |
839 | u8 rsvd[4]; | |
840 | }; | |
841 | ||
842 | struct mlx5_destroy_mkey_mbox_out { | |
843 | struct mlx5_outbox_hdr hdr; | |
844 | u8 rsvd[8]; | |
845 | }; | |
846 | ||
847 | struct mlx5_query_mkey_mbox_in { | |
848 | struct mlx5_inbox_hdr hdr; | |
849 | __be32 mkey; | |
850 | }; | |
851 | ||
852 | struct mlx5_query_mkey_mbox_out { | |
853 | struct mlx5_outbox_hdr hdr; | |
854 | __be64 pas[0]; | |
855 | }; | |
856 | ||
857 | struct mlx5_modify_mkey_mbox_in { | |
858 | struct mlx5_inbox_hdr hdr; | |
859 | __be32 mkey; | |
860 | __be64 pas[0]; | |
861 | }; | |
862 | ||
863 | struct mlx5_modify_mkey_mbox_out { | |
864 | struct mlx5_outbox_hdr hdr; | |
865 | }; | |
866 | ||
867 | struct mlx5_dump_mkey_mbox_in { | |
868 | struct mlx5_inbox_hdr hdr; | |
869 | }; | |
870 | ||
871 | struct mlx5_dump_mkey_mbox_out { | |
872 | struct mlx5_outbox_hdr hdr; | |
873 | __be32 mkey; | |
874 | }; | |
875 | ||
876 | struct mlx5_mad_ifc_mbox_in { | |
877 | struct mlx5_inbox_hdr hdr; | |
878 | __be16 remote_lid; | |
879 | u8 rsvd0; | |
880 | u8 port; | |
881 | u8 rsvd1[4]; | |
882 | u8 data[256]; | |
883 | }; | |
884 | ||
885 | struct mlx5_mad_ifc_mbox_out { | |
886 | struct mlx5_outbox_hdr hdr; | |
887 | u8 rsvd[8]; | |
888 | u8 data[256]; | |
889 | }; | |
890 | ||
891 | struct mlx5_access_reg_mbox_in { | |
892 | struct mlx5_inbox_hdr hdr; | |
893 | u8 rsvd0[2]; | |
894 | __be16 register_id; | |
895 | __be32 arg; | |
896 | __be32 data[0]; | |
897 | }; | |
898 | ||
899 | struct mlx5_access_reg_mbox_out { | |
900 | struct mlx5_outbox_hdr hdr; | |
901 | u8 rsvd[8]; | |
902 | __be32 data[0]; | |
903 | }; | |
904 | ||
905 | #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) | |
906 | ||
907 | enum { | |
908 | MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 | |
909 | }; | |
910 | ||
911 | #endif /* MLX5_DEVICE_H */ |