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iw_cxgb3: Fix incorrectly returning error on success
[deliverable/linux.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e281682b
SM		 35enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
d29b796a
EC		 69enum {
70 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
71 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
72 MLX5_CMD_OP_INIT_HCA = 0x102,
73 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
74 MLX5_CMD_OP_ENABLE_HCA = 0x104,
75 MLX5_CMD_OP_DISABLE_HCA = 0x105,
76 MLX5_CMD_OP_QUERY_PAGES = 0x107,
77 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
78 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 79 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
80 MLX5_CMD_OP_SET_ISSI = 0x10b,
d29b796a
EC		 81 MLX5_CMD_OP_CREATE_MKEY = 0x200,
82 MLX5_CMD_OP_QUERY_MKEY = 0x201,
83 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
84 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
85 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
86 MLX5_CMD_OP_CREATE_EQ = 0x301,
87 MLX5_CMD_OP_DESTROY_EQ = 0x302,
88 MLX5_CMD_OP_QUERY_EQ = 0x303,
89 MLX5_CMD_OP_GEN_EQE = 0x304,
90 MLX5_CMD_OP_CREATE_CQ = 0x400,
91 MLX5_CMD_OP_DESTROY_CQ = 0x401,
92 MLX5_CMD_OP_QUERY_CQ = 0x402,
93 MLX5_CMD_OP_MODIFY_CQ = 0x403,
94 MLX5_CMD_OP_CREATE_QP = 0x500,
95 MLX5_CMD_OP_DESTROY_QP = 0x501,
96 MLX5_CMD_OP_RST2INIT_QP = 0x502,
97 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
98 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
99 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
100 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
101 MLX5_CMD_OP_2ERR_QP = 0x507,
102 MLX5_CMD_OP_2RST_QP = 0x50a,
103 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 104 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 105 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
106 MLX5_CMD_OP_CREATE_PSV = 0x600,
107 MLX5_CMD_OP_DESTROY_PSV = 0x601,
108 MLX5_CMD_OP_CREATE_SRQ = 0x700,
109 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
110 MLX5_CMD_OP_QUERY_SRQ = 0x702,
111 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 112 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
113 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
114 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
115 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 116 MLX5_CMD_OP_CREATE_DCT = 0x710,
117 MLX5_CMD_OP_DESTROY_DCT = 0x711,
118 MLX5_CMD_OP_DRAIN_DCT = 0x712,
119 MLX5_CMD_OP_QUERY_DCT = 0x713,
120 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
121 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
122 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
123 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
124 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
125 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
126 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 127 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 128 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 129 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
130 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
131 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
132 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 133 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
134 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
135 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
136 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
137 MLX5_CMD_OP_ALLOC_PD = 0x800,
138 MLX5_CMD_OP_DEALLOC_PD = 0x801,
139 MLX5_CMD_OP_ALLOC_UAR = 0x802,
140 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
141 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
142 MLX5_CMD_OP_ACCESS_REG = 0x805,
143 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
e281682b 144 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
d29b796a
EC		 145 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
146 MLX5_CMD_OP_MAD_IFC = 0x50d,
147 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
148 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
149 MLX5_CMD_OP_NOP = 0x80d,
150 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
151 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 152 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
153 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
154 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
155 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
156 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
157 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
158 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
159 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
160 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
161 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
162 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
163 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
d29b796a
EC		 164 MLX5_CMD_OP_CREATE_TIR = 0x900,
165 MLX5_CMD_OP_MODIFY_TIR = 0x901,
166 MLX5_CMD_OP_DESTROY_TIR = 0x902,
167 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 168 MLX5_CMD_OP_CREATE_SQ = 0x904,
169 MLX5_CMD_OP_MODIFY_SQ = 0x905,
170 MLX5_CMD_OP_DESTROY_SQ = 0x906,
171 MLX5_CMD_OP_QUERY_SQ = 0x907,
172 MLX5_CMD_OP_CREATE_RQ = 0x908,
173 MLX5_CMD_OP_MODIFY_RQ = 0x909,
174 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
175 MLX5_CMD_OP_QUERY_RQ = 0x90b,
176 MLX5_CMD_OP_CREATE_RMP = 0x90c,
177 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
178 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
179 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 180 MLX5_CMD_OP_CREATE_TIS = 0x912,
181 MLX5_CMD_OP_MODIFY_TIS = 0x913,
182 MLX5_CMD_OP_DESTROY_TIS = 0x914,
183 MLX5_CMD_OP_QUERY_TIS = 0x915,
184 MLX5_CMD_OP_CREATE_RQT = 0x916,
185 MLX5_CMD_OP_MODIFY_RQT = 0x917,
186 MLX5_CMD_OP_DESTROY_RQT = 0x918,
187 MLX5_CMD_OP_QUERY_RQT = 0x919,
188 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
189 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
190 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
191 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
192 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
193 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
194 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
195 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
196 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938
197};
198
199struct mlx5_ifc_flow_table_fields_supported_bits {
200 u8 outer_dmac[0x1];
201 u8 outer_smac[0x1];
202 u8 outer_ether_type[0x1];
203 u8 reserved_0[0x1];
204 u8 outer_first_prio[0x1];
205 u8 outer_first_cfi[0x1];
206 u8 outer_first_vid[0x1];
207 u8 reserved_1[0x1];
208 u8 outer_second_prio[0x1];
209 u8 outer_second_cfi[0x1];
210 u8 outer_second_vid[0x1];
211 u8 reserved_2[0x1];
212 u8 outer_sip[0x1];
213 u8 outer_dip[0x1];
214 u8 outer_frag[0x1];
215 u8 outer_ip_protocol[0x1];
216 u8 outer_ip_ecn[0x1];
217 u8 outer_ip_dscp[0x1];
218 u8 outer_udp_sport[0x1];
219 u8 outer_udp_dport[0x1];
220 u8 outer_tcp_sport[0x1];
221 u8 outer_tcp_dport[0x1];
222 u8 outer_tcp_flags[0x1];
223 u8 outer_gre_protocol[0x1];
224 u8 outer_gre_key[0x1];
225 u8 outer_vxlan_vni[0x1];
226 u8 reserved_3[0x5];
227 u8 source_eswitch_port[0x1];
228
229 u8 inner_dmac[0x1];
230 u8 inner_smac[0x1];
231 u8 inner_ether_type[0x1];
232 u8 reserved_4[0x1];
233 u8 inner_first_prio[0x1];
234 u8 inner_first_cfi[0x1];
235 u8 inner_first_vid[0x1];
236 u8 reserved_5[0x1];
237 u8 inner_second_prio[0x1];
238 u8 inner_second_cfi[0x1];
239 u8 inner_second_vid[0x1];
240 u8 reserved_6[0x1];
241 u8 inner_sip[0x1];
242 u8 inner_dip[0x1];
243 u8 inner_frag[0x1];
244 u8 inner_ip_protocol[0x1];
245 u8 inner_ip_ecn[0x1];
246 u8 inner_ip_dscp[0x1];
247 u8 inner_udp_sport[0x1];
248 u8 inner_udp_dport[0x1];
249 u8 inner_tcp_sport[0x1];
250 u8 inner_tcp_dport[0x1];
251 u8 inner_tcp_flags[0x1];
252 u8 reserved_7[0x9];
253
254 u8 reserved_8[0x40];
255};
256
257struct mlx5_ifc_flow_table_prop_layout_bits {
258 u8 ft_support[0x1];
259 u8 reserved_0[0x1f];
260
261 u8 reserved_1[0x2];
262 u8 log_max_ft_size[0x6];
263 u8 reserved_2[0x10];
264 u8 max_ft_level[0x8];
265
266 u8 reserved_3[0x20];
267
268 u8 reserved_4[0x18];
269 u8 log_max_ft_num[0x8];
270
271 u8 reserved_5[0x18];
272 u8 log_max_destination[0x8];
273
274 u8 reserved_6[0x18];
275 u8 log_max_flow[0x8];
276
277 u8 reserved_7[0x40];
278
279 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
280
281 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
282};
283
284struct mlx5_ifc_odp_per_transport_service_cap_bits {
285 u8 send[0x1];
286 u8 receive[0x1];
287 u8 write[0x1];
288 u8 read[0x1];
289 u8 reserved_0[0x1];
290 u8 srq_receive[0x1];
291 u8 reserved_1[0x1a];
292};
293
294struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
295 u8 smac_47_16[0x20];
296
297 u8 smac_15_0[0x10];
298 u8 ethertype[0x10];
299
300 u8 dmac_47_16[0x20];
301
302 u8 dmac_15_0[0x10];
303 u8 first_prio[0x3];
304 u8 first_cfi[0x1];
305 u8 first_vid[0xc];
306
307 u8 ip_protocol[0x8];
308 u8 ip_dscp[0x6];
309 u8 ip_ecn[0x2];
310 u8 vlan_tag[0x1];
311 u8 reserved_0[0x1];
312 u8 frag[0x1];
313 u8 reserved_1[0x4];
314 u8 tcp_flags[0x9];
315
316 u8 tcp_sport[0x10];
317 u8 tcp_dport[0x10];
318
319 u8 reserved_2[0x20];
320
321 u8 udp_sport[0x10];
322 u8 udp_dport[0x10];
323
324 u8 src_ip[4][0x20];
325
326 u8 dst_ip[4][0x20];
327};
328
329struct mlx5_ifc_fte_match_set_misc_bits {
330 u8 reserved_0[0x20];
331
332 u8 reserved_1[0x10];
333 u8 source_port[0x10];
334
335 u8 outer_second_prio[0x3];
336 u8 outer_second_cfi[0x1];
337 u8 outer_second_vid[0xc];
338 u8 inner_second_prio[0x3];
339 u8 inner_second_cfi[0x1];
340 u8 inner_second_vid[0xc];
341
342 u8 outer_second_vlan_tag[0x1];
343 u8 inner_second_vlan_tag[0x1];
344 u8 reserved_2[0xe];
345 u8 gre_protocol[0x10];
346
347 u8 gre_key_h[0x18];
348 u8 gre_key_l[0x8];
349
350 u8 vxlan_vni[0x18];
351 u8 reserved_3[0x8];
352
353 u8 reserved_4[0x20];
354
355 u8 reserved_5[0xc];
356 u8 outer_ipv6_flow_label[0x14];
357
358 u8 reserved_6[0xc];
359 u8 inner_ipv6_flow_label[0x14];
360
361 u8 reserved_7[0xe0];
362};
363
364struct mlx5_ifc_cmd_pas_bits {
365 u8 pa_h[0x20];
366
367 u8 pa_l[0x14];
368 u8 reserved_0[0xc];
369};
370
371struct mlx5_ifc_uint64_bits {
372 u8 hi[0x20];
373
374 u8 lo[0x20];
375};
376
377enum {
378 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
379 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
380 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
381 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
382 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
383 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
384 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
385 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
386 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
387 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
388};
389
390struct mlx5_ifc_ads_bits {
391 u8 fl[0x1];
392 u8 free_ar[0x1];
393 u8 reserved_0[0xe];
394 u8 pkey_index[0x10];
395
396 u8 reserved_1[0x8];
397 u8 grh[0x1];
398 u8 mlid[0x7];
399 u8 rlid[0x10];
400
401 u8 ack_timeout[0x5];
402 u8 reserved_2[0x3];
403 u8 src_addr_index[0x8];
404 u8 reserved_3[0x4];
405 u8 stat_rate[0x4];
406 u8 hop_limit[0x8];
407
408 u8 reserved_4[0x4];
409 u8 tclass[0x8];
410 u8 flow_label[0x14];
411
412 u8 rgid_rip[16][0x8];
413
414 u8 reserved_5[0x4];
415 u8 f_dscp[0x1];
416 u8 f_ecn[0x1];
417 u8 reserved_6[0x1];
418 u8 f_eth_prio[0x1];
419 u8 ecn[0x2];
420 u8 dscp[0x6];
421 u8 udp_sport[0x10];
422
423 u8 dei_cfi[0x1];
424 u8 eth_prio[0x3];
425 u8 sl[0x4];
426 u8 port[0x8];
427 u8 rmac_47_32[0x10];
428
429 u8 rmac_31_0[0x20];
430};
431
432struct mlx5_ifc_flow_table_nic_cap_bits {
433 u8 reserved_0[0x200];
434
435 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
436
437 u8 reserved_1[0x200];
438
439 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
440
441 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
442
443 u8 reserved_2[0x200];
444
445 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
446
447 u8 reserved_3[0x7200];
448};
449
450struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
451 u8 csum_cap[0x1];
452 u8 vlan_cap[0x1];
453 u8 lro_cap[0x1];
454 u8 lro_psh_flag[0x1];
455 u8 lro_time_stamp[0x1];
66189961
TT		 456 u8 reserved_0[0x3];
457 u8 self_lb_en_modifiable[0x1];
458 u8 reserved_1[0x2];
e281682b 459 u8 max_lso_cap[0x5];
66189961 460 u8 reserved_2[0x4];
e281682b 461 u8 rss_ind_tbl_cap[0x4];
66189961 462 u8 reserved_3[0x3];
e281682b 463 u8 tunnel_lso_const_out_ip_id[0x1];
66189961 464 u8 reserved_4[0x2];
e281682b
SM		 465 u8 tunnel_statless_gre[0x1];
466 u8 tunnel_stateless_vxlan[0x1];
467
66189961 468 u8 reserved_5[0x20];
e281682b 469
66189961 470 u8 reserved_6[0x10];
e281682b
SM		 471 u8 lro_min_mss_size[0x10];
472
66189961 473 u8 reserved_7[0x120];
e281682b
SM		 474
475 u8 lro_timer_supported_periods[4][0x20];
476
66189961 477 u8 reserved_8[0x600];
e281682b
SM		 478};
479
480struct mlx5_ifc_roce_cap_bits {
481 u8 roce_apm[0x1];
482 u8 reserved_0[0x1f];
483
484 u8 reserved_1[0x60];
485
486 u8 reserved_2[0xc];
487 u8 l3_type[0x4];
488 u8 reserved_3[0x8];
489 u8 roce_version[0x8];
490
491 u8 reserved_4[0x10];
492 u8 r_roce_dest_udp_port[0x10];
493
494 u8 r_roce_max_src_udp_port[0x10];
495 u8 r_roce_min_src_udp_port[0x10];
496
497 u8 reserved_5[0x10];
498 u8 roce_address_table_size[0x10];
499
500 u8 reserved_6[0x700];
501};
502
503enum {
504 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
505 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
506 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
507 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
508 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
509 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
510 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
511 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
512 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
513};
514
515enum {
516 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
517 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
518 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
519 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
520 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
521 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
522 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
523 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
524 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
525};
526
527struct mlx5_ifc_atomic_caps_bits {
528 u8 reserved_0[0x40];
529
530 u8 atomic_req_endianness[0x1];
531 u8 reserved_1[0x1f];
532
533 u8 reserved_2[0x20];
534
535 u8 reserved_3[0x10];
536 u8 atomic_operations[0x10];
537
538 u8 reserved_4[0x10];
539 u8 atomic_size_qp[0x10];
540
541 u8 reserved_5[0x10];
542 u8 atomic_size_dc[0x10];
543
544 u8 reserved_6[0x720];
545};
546
547struct mlx5_ifc_odp_cap_bits {
548 u8 reserved_0[0x40];
549
550 u8 sig[0x1];
551 u8 reserved_1[0x1f];
552
553 u8 reserved_2[0x20];
554
555 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
556
557 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
558
559 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
560
561 u8 reserved_3[0x720];
562};
563
564enum {
565 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
566 MLX5_WQ_TYPE_CYCLIC = 0x1,
567 MLX5_WQ_TYPE_STRQ = 0x2,
568};
569
570enum {
571 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
572 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
573};
574
575enum {
576 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
577 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
578 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
579 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
580 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
581};
582
583enum {
584 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
585 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
586 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
587 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
588 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
589 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
590};
591
592enum {
593 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
594 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
595};
596
597enum {
598 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
599 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
600 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
601};
602
603enum {
604 MLX5_CAP_PORT_TYPE_IB = 0x0,
605 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 606};
607
b775516b
EC		 608struct mlx5_ifc_cmd_hca_cap_bits {
609 u8 reserved_0[0x80];
610
611 u8 log_max_srq_sz[0x8];
612 u8 log_max_qp_sz[0x8];
613 u8 reserved_1[0xb];
614 u8 log_max_qp[0x5];
615
e281682b
SM		 616 u8 reserved_2[0xb];
617 u8 log_max_srq[0x5];
b775516b
EC		 618 u8 reserved_3[0x10];
619
620 u8 reserved_4[0x8];
621 u8 log_max_cq_sz[0x8];
622 u8 reserved_5[0xb];
623 u8 log_max_cq[0x5];
624
625 u8 log_max_eq_sz[0x8];
626 u8 reserved_6[0x2];
627 u8 log_max_mkey[0x6];
628 u8 reserved_7[0xc];
629 u8 log_max_eq[0x4];
630
631 u8 max_indirection[0x8];
632 u8 reserved_8[0x1];
633 u8 log_max_mrw_sz[0x7];
634 u8 reserved_9[0x2];
635 u8 log_max_bsf_list_size[0x6];
636 u8 reserved_10[0x2];
637 u8 log_max_klm_list_size[0x6];
638
639 u8 reserved_11[0xa];
640 u8 log_max_ra_req_dc[0x6];
641 u8 reserved_12[0xa];
642 u8 log_max_ra_res_dc[0x6];
643
644 u8 reserved_13[0xa];
645 u8 log_max_ra_req_qp[0x6];
646 u8 reserved_14[0xa];
647 u8 log_max_ra_res_qp[0x6];
648
649 u8 pad_cap[0x1];
650 u8 cc_query_allowed[0x1];
651 u8 cc_modify_allowed[0x1];
e281682b
SM		 652 u8 reserved_15[0xd];
653 u8 gid_table_size[0x10];
b775516b 654
e281682b
SM		 655 u8 out_of_seq_cnt[0x1];
656 u8 vport_counters[0x1];
657 u8 reserved_16[0x4];
b775516b
EC		 658 u8 max_qp_cnt[0xa];
659 u8 pkey_table_size[0x10];
660
e281682b
SM		 661 u8 vport_group_manager[0x1];
662 u8 vhca_group_manager[0x1];
663 u8 ib_virt[0x1];
664 u8 eth_virt[0x1];
665 u8 reserved_17[0x1];
666 u8 ets[0x1];
667 u8 nic_flow_table[0x1];
668 u8 reserved_18[0x4];
b775516b 669 u8 local_ca_ack_delay[0x5];
e281682b
SM		 670 u8 reserved_19[0x6];
671 u8 port_type[0x2];
b775516b
EC		 672 u8 num_ports[0x8];
673
e281682b 674 u8 reserved_20[0x3];
b775516b 675 u8 log_max_msg[0x5];
e281682b 676 u8 reserved_21[0x18];
b775516b
EC		 677
678 u8 stat_rate_support[0x10];
e281682b
SM		 679 u8 reserved_22[0xc];
680 u8 cqe_version[0x4];
b775516b 681
e281682b
SM		 682 u8 compact_address_vector[0x1];
683 u8 reserved_23[0xe];
684 u8 drain_sigerr[0x1];
b775516b
EC		 685 u8 cmdif_checksum[0x2];
686 u8 sigerr_cqe[0x1];
e281682b 687 u8 reserved_24[0x1];
b775516b
EC		 688 u8 wq_signature[0x1];
689 u8 sctr_data_cqe[0x1];
e281682b 690 u8 reserved_25[0x1];
b775516b
EC		 691 u8 sho[0x1];
692 u8 tph[0x1];
693 u8 rf[0x1];
e281682b
SM		 694 u8 dct[0x1];
695 u8 reserved_26[0x1];
696 u8 eth_net_offloads[0x1];
b775516b
EC		 697 u8 roce[0x1];
698 u8 atomic[0x1];
e281682b 699 u8 reserved_27[0x1];
b775516b
EC		 700
701 u8 cq_oi[0x1];
702 u8 cq_resize[0x1];
703 u8 cq_moderation[0x1];
e281682b
SM		 704 u8 reserved_28[0x3];
705 u8 cq_eq_remap[0x1];
b775516b
EC		 706 u8 pg[0x1];
707 u8 block_lb_mc[0x1];
e281682b
SM		 708 u8 reserved_29[0x1];
709 u8 scqe_break_moderation[0x1];
710 u8 reserved_30[0x1];
b775516b 711 u8 cd[0x1];
e281682b 712 u8 reserved_31[0x1];
b775516b 713 u8 apm[0x1];
e281682b 714 u8 reserved_32[0x7];
b775516b
EC		 715 u8 qkv[0x1];
716 u8 pkv[0x1];
e281682b 717 u8 reserved_33[0x4];
b775516b
EC		 718 u8 xrc[0x1];
719 u8 ud[0x1];
720 u8 uc[0x1];
721 u8 rc[0x1];
722
e281682b 723 u8 reserved_34[0xa];
b775516b 724 u8 uar_sz[0x6];
e281682b 725 u8 reserved_35[0x8];
b775516b
EC		 726 u8 log_pg_sz[0x8];
727
728 u8 bf[0x1];
e281682b
SM		 729 u8 reserved_36[0x1];
730 u8 pad_tx_eth_packet[0x1];
731 u8 reserved_37[0x8];
b775516b 732 u8 log_bf_reg_size[0x5];
e281682b 733 u8 reserved_38[0x10];
b775516b 734
e281682b 735 u8 reserved_39[0x10];
b775516b
EC		 736 u8 max_wqe_sz_sq[0x10];
737
e281682b 738 u8 reserved_40[0x10];
b775516b
EC		 739 u8 max_wqe_sz_rq[0x10];
740
e281682b 741 u8 reserved_41[0x10];
b775516b
EC		 742 u8 max_wqe_sz_sq_dc[0x10];
743
e281682b 744 u8 reserved_42[0x7];
b775516b
EC		 745 u8 max_qp_mcg[0x19];
746
e281682b 747 u8 reserved_43[0x18];
b775516b
EC		 748 u8 log_max_mcg[0x8];
749
e281682b
SM		 750 u8 reserved_44[0x3];
751 u8 log_max_transport_domain[0x5];
752 u8 reserved_45[0x3];
b775516b 753 u8 log_max_pd[0x5];
e281682b 754 u8 reserved_46[0xb];
b775516b
EC		 755 u8 log_max_xrcd[0x5];
756
e281682b 757 u8 reserved_47[0x20];
b775516b 758
e281682b 759 u8 reserved_48[0x3];
b775516b 760 u8 log_max_rq[0x5];
e281682b 761 u8 reserved_49[0x3];
b775516b 762 u8 log_max_sq[0x5];
e281682b 763 u8 reserved_50[0x3];
b775516b 764 u8 log_max_tir[0x5];
e281682b 765 u8 reserved_51[0x3];
b775516b
EC		 766 u8 log_max_tis[0x5];
767
e281682b
SM		 768 u8 basic_cyclic_rcv_wqe[0x1];
769 u8 reserved_52[0x2];
770 u8 log_max_rmp[0x5];
771 u8 reserved_53[0x3];
772 u8 log_max_rqt[0x5];
773 u8 reserved_54[0x3];
774 u8 log_max_rqt_size[0x5];
775 u8 reserved_55[0x3];
b775516b
EC		 776 u8 log_max_tis_per_sq[0x5];
777
e281682b
SM		 778 u8 reserved_56[0x3];
779 u8 log_max_stride_sz_rq[0x5];
780 u8 reserved_57[0x3];
781 u8 log_min_stride_sz_rq[0x5];
782 u8 reserved_58[0x3];
783 u8 log_max_stride_sz_sq[0x5];
784 u8 reserved_59[0x3];
785 u8 log_min_stride_sz_sq[0x5];
786
787 u8 reserved_60[0x1b];
788 u8 log_max_wq_sz[0x5];
789
790 u8 reserved_61[0xa0];
b775516b 791
e281682b
SM		 792 u8 reserved_62[0x3];
793 u8 log_max_l2_table[0x5];
794 u8 reserved_63[0x8];
b775516b
EC		 795 u8 log_uar_page_sz[0x10];
796
7c60bcbb
MB		 797 u8 reserved_64[0x20];
798 u8 device_frequency_mhz[0x20];
799 u8 device_frequency_khz[0x20];
800 u8 reserved_65[0xa0];
b775516b 801
7c60bcbb 802 u8 reserved_66[0x1f];
b775516b
EC		 803 u8 cqe_zip[0x1];
804
805 u8 cqe_zip_timeout[0x10];
806 u8 cqe_zip_max_num[0x10];
807
7c60bcbb 808 u8 reserved_67[0x220];
b775516b
EC		 809};
810
e281682b
SM		 811enum {
812 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_FLOW_TABLE_ = 0x1,
813 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_TIR = 0x2,
814};
b775516b 815
e281682b
SM		 816struct mlx5_ifc_dest_format_struct_bits {
817 u8 destination_type[0x8];
818 u8 destination_id[0x18];
b775516b 819
e281682b
SM		 820 u8 reserved_0[0x20];
821};
822
823struct mlx5_ifc_fte_match_param_bits {
824 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
825
826 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
827
828 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 829
e281682b 830 u8 reserved_0[0xa00];
b775516b
EC		 831};
832
e281682b
SM		 833enum {
834 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
835 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
836 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
837 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
838 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
839};
b775516b 840
e281682b
SM		 841struct mlx5_ifc_rx_hash_field_select_bits {
842 u8 l3_prot_type[0x1];
843 u8 l4_prot_type[0x1];
844 u8 selected_fields[0x1e];
845};
b775516b 846
e281682b
SM		 847enum {
848 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
849 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 850};
851
e281682b
SM		 852enum {
853 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
854 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
855};
856
857struct mlx5_ifc_wq_bits {
858 u8 wq_type[0x4];
859 u8 wq_signature[0x1];
860 u8 end_padding_mode[0x2];
861 u8 cd_slave[0x1];
b775516b
EC		 862 u8 reserved_0[0x18];
863
e281682b
SM		 864 u8 hds_skip_first_sge[0x1];
865 u8 log2_hds_buf_size[0x3];
866 u8 reserved_1[0x7];
867 u8 page_offset[0x5];
868 u8 lwm[0x10];
b775516b 869
e281682b
SM		 870 u8 reserved_2[0x8];
871 u8 pd[0x18];
872
873 u8 reserved_3[0x8];
874 u8 uar_page[0x18];
875
876 u8 dbr_addr[0x40];
877
878 u8 hw_counter[0x20];
879
880 u8 sw_counter[0x20];
881
882 u8 reserved_4[0xc];
883 u8 log_wq_stride[0x4];
884 u8 reserved_5[0x3];
885 u8 log_wq_pg_sz[0x5];
886 u8 reserved_6[0x3];
887 u8 log_wq_sz[0x5];
888
889 u8 reserved_7[0x4e0];
b775516b 890
e281682b 891 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 892};
893
e281682b
SM		 894struct mlx5_ifc_rq_num_bits {
895 u8 reserved_0[0x8];
896 u8 rq_num[0x18];
897};
b775516b 898
e281682b
SM		 899struct mlx5_ifc_mac_address_layout_bits {
900 u8 reserved_0[0x10];
901 u8 mac_addr_47_32[0x10];
b775516b 902
e281682b
SM		 903 u8 mac_addr_31_0[0x20];
904};
905
906struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
907 u8 reserved_0[0xa0];
908
909 u8 min_time_between_cnps[0x20];
910
911 u8 reserved_1[0x12];
912 u8 cnp_dscp[0x6];
913 u8 reserved_2[0x5];
914 u8 cnp_802p_prio[0x3];
915
916 u8 reserved_3[0x720];
917};
918
919struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
920 u8 reserved_0[0x60];
921
922 u8 reserved_1[0x4];
923 u8 clamp_tgt_rate[0x1];
924 u8 reserved_2[0x3];
925 u8 clamp_tgt_rate_after_time_inc[0x1];
926 u8 reserved_3[0x17];
927
928 u8 reserved_4[0x20];
929
930 u8 rpg_time_reset[0x20];
931
932 u8 rpg_byte_reset[0x20];
933
934 u8 rpg_threshold[0x20];
935
936 u8 rpg_max_rate[0x20];
937
938 u8 rpg_ai_rate[0x20];
939
940 u8 rpg_hai_rate[0x20];
941
942 u8 rpg_gd[0x20];
943
944 u8 rpg_min_dec_fac[0x20];
945
946 u8 rpg_min_rate[0x20];
947
948 u8 reserved_5[0xe0];
949
950 u8 rate_to_set_on_first_cnp[0x20];
951
952 u8 dce_tcp_g[0x20];
953
954 u8 dce_tcp_rtt[0x20];
955
956 u8 rate_reduce_monitor_period[0x20];
957
958 u8 reserved_6[0x20];
959
960 u8 initial_alpha_value[0x20];
961
962 u8 reserved_7[0x4a0];
963};
964
965struct mlx5_ifc_cong_control_802_1qau_rp_bits {
966 u8 reserved_0[0x80];
967
968 u8 rppp_max_rps[0x20];
969
970 u8 rpg_time_reset[0x20];
971
972 u8 rpg_byte_reset[0x20];
973
974 u8 rpg_threshold[0x20];
975
976 u8 rpg_max_rate[0x20];
977
978 u8 rpg_ai_rate[0x20];
979
980 u8 rpg_hai_rate[0x20];
981
982 u8 rpg_gd[0x20];
983
984 u8 rpg_min_dec_fac[0x20];
985
986 u8 rpg_min_rate[0x20];
987
988 u8 reserved_1[0x640];
989};
990
991enum {
992 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
993 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
994 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
995};
996
997struct mlx5_ifc_resize_field_select_bits {
998 u8 resize_field_select[0x20];
999};
1000
1001enum {
1002 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1003 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1004 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1005 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1006};
1007
1008struct mlx5_ifc_modify_field_select_bits {
1009 u8 modify_field_select[0x20];
1010};
1011
1012struct mlx5_ifc_field_select_r_roce_np_bits {
1013 u8 field_select_r_roce_np[0x20];
1014};
1015
1016struct mlx5_ifc_field_select_r_roce_rp_bits {
1017 u8 field_select_r_roce_rp[0x20];
1018};
1019
1020enum {
1021 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1022 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1023 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1024 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1025 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1026 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1027 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1028 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1029 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1030 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1031};
1032
1033struct mlx5_ifc_field_select_802_1qau_rp_bits {
1034 u8 field_select_8021qaurp[0x20];
1035};
1036
1037struct mlx5_ifc_phys_layer_cntrs_bits {
1038 u8 time_since_last_clear_high[0x20];
1039
1040 u8 time_since_last_clear_low[0x20];
1041
1042 u8 symbol_errors_high[0x20];
1043
1044 u8 symbol_errors_low[0x20];
1045
1046 u8 sync_headers_errors_high[0x20];
1047
1048 u8 sync_headers_errors_low[0x20];
1049
1050 u8 edpl_bip_errors_lane0_high[0x20];
1051
1052 u8 edpl_bip_errors_lane0_low[0x20];
1053
1054 u8 edpl_bip_errors_lane1_high[0x20];
1055
1056 u8 edpl_bip_errors_lane1_low[0x20];
1057
1058 u8 edpl_bip_errors_lane2_high[0x20];
1059
1060 u8 edpl_bip_errors_lane2_low[0x20];
1061
1062 u8 edpl_bip_errors_lane3_high[0x20];
1063
1064 u8 edpl_bip_errors_lane3_low[0x20];
1065
1066 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1067
1068 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1069
1070 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1071
1072 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1073
1074 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1075
1076 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1077
1078 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1079
1080 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1081
1082 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1083
1084 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1085
1086 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1087
1088 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1089
1090 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1091
1092 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1093
1094 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1095
1096 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1097
1098 u8 rs_fec_corrected_blocks_high[0x20];
1099
1100 u8 rs_fec_corrected_blocks_low[0x20];
1101
1102 u8 rs_fec_uncorrectable_blocks_high[0x20];
1103
1104 u8 rs_fec_uncorrectable_blocks_low[0x20];
1105
1106 u8 rs_fec_no_errors_blocks_high[0x20];
1107
1108 u8 rs_fec_no_errors_blocks_low[0x20];
1109
1110 u8 rs_fec_single_error_blocks_high[0x20];
1111
1112 u8 rs_fec_single_error_blocks_low[0x20];
1113
1114 u8 rs_fec_corrected_symbols_total_high[0x20];
1115
1116 u8 rs_fec_corrected_symbols_total_low[0x20];
1117
1118 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1119
1120 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1121
1122 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1123
1124 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1125
1126 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1127
1128 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1129
1130 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1131
1132 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1133
1134 u8 link_down_events[0x20];
1135
1136 u8 successful_recovery_events[0x20];
1137
1138 u8 reserved_0[0x180];
1139};
1140
1141struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1142 u8 transmit_queue_high[0x20];
1143
1144 u8 transmit_queue_low[0x20];
1145
1146 u8 reserved_0[0x780];
1147};
1148
1149struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1150 u8 rx_octets_high[0x20];
1151
1152 u8 rx_octets_low[0x20];
1153
1154 u8 reserved_0[0xc0];
1155
1156 u8 rx_frames_high[0x20];
1157
1158 u8 rx_frames_low[0x20];
1159
1160 u8 tx_octets_high[0x20];
1161
1162 u8 tx_octets_low[0x20];
1163
1164 u8 reserved_1[0xc0];
1165
1166 u8 tx_frames_high[0x20];
1167
1168 u8 tx_frames_low[0x20];
1169
1170 u8 rx_pause_high[0x20];
1171
1172 u8 rx_pause_low[0x20];
1173
1174 u8 rx_pause_duration_high[0x20];
1175
1176 u8 rx_pause_duration_low[0x20];
1177
1178 u8 tx_pause_high[0x20];
1179
1180 u8 tx_pause_low[0x20];
1181
1182 u8 tx_pause_duration_high[0x20];
1183
1184 u8 tx_pause_duration_low[0x20];
1185
1186 u8 rx_pause_transition_high[0x20];
1187
1188 u8 rx_pause_transition_low[0x20];
1189
1190 u8 reserved_2[0x400];
1191};
1192
1193struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1194 u8 port_transmit_wait_high[0x20];
1195
1196 u8 port_transmit_wait_low[0x20];
1197
1198 u8 reserved_0[0x780];
1199};
1200
1201struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1202 u8 dot3stats_alignment_errors_high[0x20];
1203
1204 u8 dot3stats_alignment_errors_low[0x20];
1205
1206 u8 dot3stats_fcs_errors_high[0x20];
1207
1208 u8 dot3stats_fcs_errors_low[0x20];
1209
1210 u8 dot3stats_single_collision_frames_high[0x20];
1211
1212 u8 dot3stats_single_collision_frames_low[0x20];
1213
1214 u8 dot3stats_multiple_collision_frames_high[0x20];
1215
1216 u8 dot3stats_multiple_collision_frames_low[0x20];
1217
1218 u8 dot3stats_sqe_test_errors_high[0x20];
1219
1220 u8 dot3stats_sqe_test_errors_low[0x20];
1221
1222 u8 dot3stats_deferred_transmissions_high[0x20];
1223
1224 u8 dot3stats_deferred_transmissions_low[0x20];
1225
1226 u8 dot3stats_late_collisions_high[0x20];
1227
1228 u8 dot3stats_late_collisions_low[0x20];
1229
1230 u8 dot3stats_excessive_collisions_high[0x20];
1231
1232 u8 dot3stats_excessive_collisions_low[0x20];
1233
1234 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1235
1236 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1237
1238 u8 dot3stats_carrier_sense_errors_high[0x20];
1239
1240 u8 dot3stats_carrier_sense_errors_low[0x20];
1241
1242 u8 dot3stats_frame_too_longs_high[0x20];
1243
1244 u8 dot3stats_frame_too_longs_low[0x20];
1245
1246 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1247
1248 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1249
1250 u8 dot3stats_symbol_errors_high[0x20];
1251
1252 u8 dot3stats_symbol_errors_low[0x20];
1253
1254 u8 dot3control_in_unknown_opcodes_high[0x20];
1255
1256 u8 dot3control_in_unknown_opcodes_low[0x20];
1257
1258 u8 dot3in_pause_frames_high[0x20];
1259
1260 u8 dot3in_pause_frames_low[0x20];
1261
1262 u8 dot3out_pause_frames_high[0x20];
1263
1264 u8 dot3out_pause_frames_low[0x20];
1265
1266 u8 reserved_0[0x3c0];
1267};
1268
1269struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1270 u8 ether_stats_drop_events_high[0x20];
1271
1272 u8 ether_stats_drop_events_low[0x20];
1273
1274 u8 ether_stats_octets_high[0x20];
1275
1276 u8 ether_stats_octets_low[0x20];
1277
1278 u8 ether_stats_pkts_high[0x20];
1279
1280 u8 ether_stats_pkts_low[0x20];
1281
1282 u8 ether_stats_broadcast_pkts_high[0x20];
1283
1284 u8 ether_stats_broadcast_pkts_low[0x20];
1285
1286 u8 ether_stats_multicast_pkts_high[0x20];
1287
1288 u8 ether_stats_multicast_pkts_low[0x20];
1289
1290 u8 ether_stats_crc_align_errors_high[0x20];
1291
1292 u8 ether_stats_crc_align_errors_low[0x20];
1293
1294 u8 ether_stats_undersize_pkts_high[0x20];
1295
1296 u8 ether_stats_undersize_pkts_low[0x20];
1297
1298 u8 ether_stats_oversize_pkts_high[0x20];
1299
1300 u8 ether_stats_oversize_pkts_low[0x20];
1301
1302 u8 ether_stats_fragments_high[0x20];
1303
1304 u8 ether_stats_fragments_low[0x20];
1305
1306 u8 ether_stats_jabbers_high[0x20];
1307
1308 u8 ether_stats_jabbers_low[0x20];
1309
1310 u8 ether_stats_collisions_high[0x20];
1311
1312 u8 ether_stats_collisions_low[0x20];
1313
1314 u8 ether_stats_pkts64octets_high[0x20];
1315
1316 u8 ether_stats_pkts64octets_low[0x20];
1317
1318 u8 ether_stats_pkts65to127octets_high[0x20];
1319
1320 u8 ether_stats_pkts65to127octets_low[0x20];
1321
1322 u8 ether_stats_pkts128to255octets_high[0x20];
1323
1324 u8 ether_stats_pkts128to255octets_low[0x20];
1325
1326 u8 ether_stats_pkts256to511octets_high[0x20];
1327
1328 u8 ether_stats_pkts256to511octets_low[0x20];
1329
1330 u8 ether_stats_pkts512to1023octets_high[0x20];
1331
1332 u8 ether_stats_pkts512to1023octets_low[0x20];
1333
1334 u8 ether_stats_pkts1024to1518octets_high[0x20];
1335
1336 u8 ether_stats_pkts1024to1518octets_low[0x20];
1337
1338 u8 ether_stats_pkts1519to2047octets_high[0x20];
1339
1340 u8 ether_stats_pkts1519to2047octets_low[0x20];
1341
1342 u8 ether_stats_pkts2048to4095octets_high[0x20];
1343
1344 u8 ether_stats_pkts2048to4095octets_low[0x20];
1345
1346 u8 ether_stats_pkts4096to8191octets_high[0x20];
1347
1348 u8 ether_stats_pkts4096to8191octets_low[0x20];
1349
1350 u8 ether_stats_pkts8192to10239octets_high[0x20];
1351
1352 u8 ether_stats_pkts8192to10239octets_low[0x20];
1353
1354 u8 reserved_0[0x280];
1355};
1356
1357struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1358 u8 if_in_octets_high[0x20];
1359
1360 u8 if_in_octets_low[0x20];
1361
1362 u8 if_in_ucast_pkts_high[0x20];
1363
1364 u8 if_in_ucast_pkts_low[0x20];
1365
1366 u8 if_in_discards_high[0x20];
1367
1368 u8 if_in_discards_low[0x20];
1369
1370 u8 if_in_errors_high[0x20];
1371
1372 u8 if_in_errors_low[0x20];
1373
1374 u8 if_in_unknown_protos_high[0x20];
1375
1376 u8 if_in_unknown_protos_low[0x20];
1377
1378 u8 if_out_octets_high[0x20];
1379
1380 u8 if_out_octets_low[0x20];
1381
1382 u8 if_out_ucast_pkts_high[0x20];
1383
1384 u8 if_out_ucast_pkts_low[0x20];
1385
1386 u8 if_out_discards_high[0x20];
1387
1388 u8 if_out_discards_low[0x20];
1389
1390 u8 if_out_errors_high[0x20];
1391
1392 u8 if_out_errors_low[0x20];
1393
1394 u8 if_in_multicast_pkts_high[0x20];
1395
1396 u8 if_in_multicast_pkts_low[0x20];
1397
1398 u8 if_in_broadcast_pkts_high[0x20];
1399
1400 u8 if_in_broadcast_pkts_low[0x20];
1401
1402 u8 if_out_multicast_pkts_high[0x20];
1403
1404 u8 if_out_multicast_pkts_low[0x20];
1405
1406 u8 if_out_broadcast_pkts_high[0x20];
1407
1408 u8 if_out_broadcast_pkts_low[0x20];
1409
1410 u8 reserved_0[0x480];
1411};
1412
1413struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1414 u8 a_frames_transmitted_ok_high[0x20];
1415
1416 u8 a_frames_transmitted_ok_low[0x20];
1417
1418 u8 a_frames_received_ok_high[0x20];
1419
1420 u8 a_frames_received_ok_low[0x20];
1421
1422 u8 a_frame_check_sequence_errors_high[0x20];
1423
1424 u8 a_frame_check_sequence_errors_low[0x20];
1425
1426 u8 a_alignment_errors_high[0x20];
1427
1428 u8 a_alignment_errors_low[0x20];
1429
1430 u8 a_octets_transmitted_ok_high[0x20];
1431
1432 u8 a_octets_transmitted_ok_low[0x20];
1433
1434 u8 a_octets_received_ok_high[0x20];
1435
1436 u8 a_octets_received_ok_low[0x20];
1437
1438 u8 a_multicast_frames_xmitted_ok_high[0x20];
1439
1440 u8 a_multicast_frames_xmitted_ok_low[0x20];
1441
1442 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1443
1444 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1445
1446 u8 a_multicast_frames_received_ok_high[0x20];
1447
1448 u8 a_multicast_frames_received_ok_low[0x20];
1449
1450 u8 a_broadcast_frames_received_ok_high[0x20];
1451
1452 u8 a_broadcast_frames_received_ok_low[0x20];
1453
1454 u8 a_in_range_length_errors_high[0x20];
1455
1456 u8 a_in_range_length_errors_low[0x20];
1457
1458 u8 a_out_of_range_length_field_high[0x20];
1459
1460 u8 a_out_of_range_length_field_low[0x20];
1461
1462 u8 a_frame_too_long_errors_high[0x20];
1463
1464 u8 a_frame_too_long_errors_low[0x20];
1465
1466 u8 a_symbol_error_during_carrier_high[0x20];
1467
1468 u8 a_symbol_error_during_carrier_low[0x20];
1469
1470 u8 a_mac_control_frames_transmitted_high[0x20];
1471
1472 u8 a_mac_control_frames_transmitted_low[0x20];
1473
1474 u8 a_mac_control_frames_received_high[0x20];
1475
1476 u8 a_mac_control_frames_received_low[0x20];
1477
1478 u8 a_unsupported_opcodes_received_high[0x20];
1479
1480 u8 a_unsupported_opcodes_received_low[0x20];
1481
1482 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1483
1484 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1485
1486 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1487
1488 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1489
1490 u8 reserved_0[0x300];
1491};
1492
1493struct mlx5_ifc_cmd_inter_comp_event_bits {
1494 u8 command_completion_vector[0x20];
1495
1496 u8 reserved_0[0xc0];
1497};
1498
1499struct mlx5_ifc_stall_vl_event_bits {
1500 u8 reserved_0[0x18];
1501 u8 port_num[0x1];
1502 u8 reserved_1[0x3];
1503 u8 vl[0x4];
1504
1505 u8 reserved_2[0xa0];
1506};
1507
1508struct mlx5_ifc_db_bf_congestion_event_bits {
1509 u8 event_subtype[0x8];
1510 u8 reserved_0[0x8];
1511 u8 congestion_level[0x8];
1512 u8 reserved_1[0x8];
1513
1514 u8 reserved_2[0xa0];
1515};
1516
1517struct mlx5_ifc_gpio_event_bits {
1518 u8 reserved_0[0x60];
1519
1520 u8 gpio_event_hi[0x20];
1521
1522 u8 gpio_event_lo[0x20];
1523
1524 u8 reserved_1[0x40];
1525};
1526
1527struct mlx5_ifc_port_state_change_event_bits {
1528 u8 reserved_0[0x40];
1529
1530 u8 port_num[0x4];
1531 u8 reserved_1[0x1c];
1532
1533 u8 reserved_2[0x80];
1534};
1535
1536struct mlx5_ifc_dropped_packet_logged_bits {
1537 u8 reserved_0[0xe0];
1538};
1539
1540enum {
1541 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1542 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1543};
1544
1545struct mlx5_ifc_cq_error_bits {
1546 u8 reserved_0[0x8];
1547 u8 cqn[0x18];
1548
1549 u8 reserved_1[0x20];
1550
1551 u8 reserved_2[0x18];
1552 u8 syndrome[0x8];
1553
1554 u8 reserved_3[0x80];
1555};
1556
1557struct mlx5_ifc_rdma_page_fault_event_bits {
1558 u8 bytes_committed[0x20];
1559
1560 u8 r_key[0x20];
1561
1562 u8 reserved_0[0x10];
1563 u8 packet_len[0x10];
1564
1565 u8 rdma_op_len[0x20];
1566
1567 u8 rdma_va[0x40];
1568
1569 u8 reserved_1[0x5];
1570 u8 rdma[0x1];
1571 u8 write[0x1];
1572 u8 requestor[0x1];
1573 u8 qp_number[0x18];
1574};
1575
1576struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1577 u8 bytes_committed[0x20];
1578
1579 u8 reserved_0[0x10];
1580 u8 wqe_index[0x10];
1581
1582 u8 reserved_1[0x10];
1583 u8 len[0x10];
1584
1585 u8 reserved_2[0x60];
1586
1587 u8 reserved_3[0x5];
1588 u8 rdma[0x1];
1589 u8 write_read[0x1];
1590 u8 requestor[0x1];
1591 u8 qpn[0x18];
1592};
1593
1594struct mlx5_ifc_qp_events_bits {
1595 u8 reserved_0[0xa0];
1596
1597 u8 type[0x8];
1598 u8 reserved_1[0x18];
1599
1600 u8 reserved_2[0x8];
1601 u8 qpn_rqn_sqn[0x18];
1602};
1603
1604struct mlx5_ifc_dct_events_bits {
1605 u8 reserved_0[0xc0];
1606
1607 u8 reserved_1[0x8];
1608 u8 dct_number[0x18];
1609};
1610
1611struct mlx5_ifc_comp_event_bits {
1612 u8 reserved_0[0xc0];
1613
1614 u8 reserved_1[0x8];
1615 u8 cq_number[0x18];
1616};
1617
1618enum {
1619 MLX5_QPC_STATE_RST = 0x0,
1620 MLX5_QPC_STATE_INIT = 0x1,
1621 MLX5_QPC_STATE_RTR = 0x2,
1622 MLX5_QPC_STATE_RTS = 0x3,
1623 MLX5_QPC_STATE_SQER = 0x4,
1624 MLX5_QPC_STATE_ERR = 0x6,
1625 MLX5_QPC_STATE_SQD = 0x7,
1626 MLX5_QPC_STATE_SUSPENDED = 0x9,
1627};
1628
1629enum {
1630 MLX5_QPC_ST_RC = 0x0,
1631 MLX5_QPC_ST_UC = 0x1,
1632 MLX5_QPC_ST_UD = 0x2,
1633 MLX5_QPC_ST_XRC = 0x3,
1634 MLX5_QPC_ST_DCI = 0x5,
1635 MLX5_QPC_ST_QP0 = 0x7,
1636 MLX5_QPC_ST_QP1 = 0x8,
1637 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1638 MLX5_QPC_ST_REG_UMR = 0xc,
1639};
1640
1641enum {
1642 MLX5_QPC_PM_STATE_ARMED = 0x0,
1643 MLX5_QPC_PM_STATE_REARM = 0x1,
1644 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1645 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1646};
1647
1648enum {
1649 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1650 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1651};
1652
1653enum {
1654 MLX5_QPC_MTU_256_BYTES = 0x1,
1655 MLX5_QPC_MTU_512_BYTES = 0x2,
1656 MLX5_QPC_MTU_1K_BYTES = 0x3,
1657 MLX5_QPC_MTU_2K_BYTES = 0x4,
1658 MLX5_QPC_MTU_4K_BYTES = 0x5,
1659 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1660};
1661
1662enum {
1663 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1664 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1665 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1666 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1667 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1668 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1669 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1670 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1671};
1672
1673enum {
1674 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1675 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1676 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1677};
1678
1679enum {
1680 MLX5_QPC_CS_RES_DISABLE = 0x0,
1681 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1682 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1683};
1684
1685struct mlx5_ifc_qpc_bits {
1686 u8 state[0x4];
1687 u8 reserved_0[0x4];
1688 u8 st[0x8];
1689 u8 reserved_1[0x3];
1690 u8 pm_state[0x2];
1691 u8 reserved_2[0x7];
1692 u8 end_padding_mode[0x2];
1693 u8 reserved_3[0x2];
1694
1695 u8 wq_signature[0x1];
1696 u8 block_lb_mc[0x1];
1697 u8 atomic_like_write_en[0x1];
1698 u8 latency_sensitive[0x1];
1699 u8 reserved_4[0x1];
1700 u8 drain_sigerr[0x1];
1701 u8 reserved_5[0x2];
1702 u8 pd[0x18];
1703
1704 u8 mtu[0x3];
1705 u8 log_msg_max[0x5];
1706 u8 reserved_6[0x1];
1707 u8 log_rq_size[0x4];
1708 u8 log_rq_stride[0x3];
1709 u8 no_sq[0x1];
1710 u8 log_sq_size[0x4];
1711 u8 reserved_7[0x6];
1712 u8 rlky[0x1];
1713 u8 reserved_8[0x4];
1714
1715 u8 counter_set_id[0x8];
1716 u8 uar_page[0x18];
1717
1718 u8 reserved_9[0x8];
1719 u8 user_index[0x18];
1720
1721 u8 reserved_10[0x3];
1722 u8 log_page_size[0x5];
1723 u8 remote_qpn[0x18];
1724
1725 struct mlx5_ifc_ads_bits primary_address_path;
1726
1727 struct mlx5_ifc_ads_bits secondary_address_path;
1728
1729 u8 log_ack_req_freq[0x4];
1730 u8 reserved_11[0x4];
1731 u8 log_sra_max[0x3];
1732 u8 reserved_12[0x2];
1733 u8 retry_count[0x3];
1734 u8 rnr_retry[0x3];
1735 u8 reserved_13[0x1];
1736 u8 fre[0x1];
1737 u8 cur_rnr_retry[0x3];
1738 u8 cur_retry_count[0x3];
1739 u8 reserved_14[0x5];
1740
1741 u8 reserved_15[0x20];
1742
1743 u8 reserved_16[0x8];
1744 u8 next_send_psn[0x18];
1745
1746 u8 reserved_17[0x8];
1747 u8 cqn_snd[0x18];
1748
1749 u8 reserved_18[0x40];
1750
1751 u8 reserved_19[0x8];
1752 u8 last_acked_psn[0x18];
1753
1754 u8 reserved_20[0x8];
1755 u8 ssn[0x18];
1756
1757 u8 reserved_21[0x8];
1758 u8 log_rra_max[0x3];
1759 u8 reserved_22[0x1];
1760 u8 atomic_mode[0x4];
1761 u8 rre[0x1];
1762 u8 rwe[0x1];
1763 u8 rae[0x1];
1764 u8 reserved_23[0x1];
1765 u8 page_offset[0x6];
1766 u8 reserved_24[0x3];
1767 u8 cd_slave_receive[0x1];
1768 u8 cd_slave_send[0x1];
1769 u8 cd_master[0x1];
1770
1771 u8 reserved_25[0x3];
1772 u8 min_rnr_nak[0x5];
1773 u8 next_rcv_psn[0x18];
1774
1775 u8 reserved_26[0x8];
1776 u8 xrcd[0x18];
1777
1778 u8 reserved_27[0x8];
1779 u8 cqn_rcv[0x18];
1780
1781 u8 dbr_addr[0x40];
1782
1783 u8 q_key[0x20];
1784
1785 u8 reserved_28[0x5];
1786 u8 rq_type[0x3];
1787 u8 srqn_rmpn[0x18];
1788
1789 u8 reserved_29[0x8];
1790 u8 rmsn[0x18];
1791
1792 u8 hw_sq_wqebb_counter[0x10];
1793 u8 sw_sq_wqebb_counter[0x10];
1794
1795 u8 hw_rq_counter[0x20];
1796
1797 u8 sw_rq_counter[0x20];
1798
1799 u8 reserved_30[0x20];
1800
1801 u8 reserved_31[0xf];
1802 u8 cgs[0x1];
1803 u8 cs_req[0x8];
1804 u8 cs_res[0x8];
1805
1806 u8 dc_access_key[0x40];
1807
1808 u8 reserved_32[0xc0];
1809};
1810
1811struct mlx5_ifc_roce_addr_layout_bits {
1812 u8 source_l3_address[16][0x8];
1813
1814 u8 reserved_0[0x3];
1815 u8 vlan_valid[0x1];
1816 u8 vlan_id[0xc];
1817 u8 source_mac_47_32[0x10];
1818
1819 u8 source_mac_31_0[0x20];
1820
1821 u8 reserved_1[0x14];
1822 u8 roce_l3_type[0x4];
1823 u8 roce_version[0x8];
1824
1825 u8 reserved_2[0x20];
1826};
1827
1828union mlx5_ifc_hca_cap_union_bits {
1829 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1830 struct mlx5_ifc_odp_cap_bits odp_cap;
1831 struct mlx5_ifc_atomic_caps_bits atomic_caps;
1832 struct mlx5_ifc_roce_cap_bits roce_cap;
1833 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1834 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1835 u8 reserved_0[0x8000];
1836};
1837
1838enum {
1839 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
1840 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
1841 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
1842};
1843
1844struct mlx5_ifc_flow_context_bits {
1845 u8 reserved_0[0x20];
1846
1847 u8 group_id[0x20];
1848
1849 u8 reserved_1[0x8];
1850 u8 flow_tag[0x18];
1851
1852 u8 reserved_2[0x10];
1853 u8 action[0x10];
1854
1855 u8 reserved_3[0x8];
1856 u8 destination_list_size[0x18];
1857
1858 u8 reserved_4[0x160];
1859
1860 struct mlx5_ifc_fte_match_param_bits match_value;
1861
1862 u8 reserved_5[0x600];
1863
1864 struct mlx5_ifc_dest_format_struct_bits destination[0];
1865};
1866
1867enum {
1868 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
1869 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
1870};
1871
1872struct mlx5_ifc_xrc_srqc_bits {
1873 u8 state[0x4];
1874 u8 log_xrc_srq_size[0x4];
1875 u8 reserved_0[0x18];
1876
1877 u8 wq_signature[0x1];
1878 u8 cont_srq[0x1];
1879 u8 reserved_1[0x1];
1880 u8 rlky[0x1];
1881 u8 basic_cyclic_rcv_wqe[0x1];
1882 u8 log_rq_stride[0x3];
1883 u8 xrcd[0x18];
1884
1885 u8 page_offset[0x6];
1886 u8 reserved_2[0x2];
1887 u8 cqn[0x18];
1888
1889 u8 reserved_3[0x20];
1890
1891 u8 user_index_equal_xrc_srqn[0x1];
1892 u8 reserved_4[0x1];
1893 u8 log_page_size[0x6];
1894 u8 user_index[0x18];
1895
1896 u8 reserved_5[0x20];
1897
1898 u8 reserved_6[0x8];
1899 u8 pd[0x18];
1900
1901 u8 lwm[0x10];
1902 u8 wqe_cnt[0x10];
1903
1904 u8 reserved_7[0x40];
1905
1906 u8 db_record_addr_h[0x20];
1907
1908 u8 db_record_addr_l[0x1e];
1909 u8 reserved_8[0x2];
1910
1911 u8 reserved_9[0x80];
1912};
1913
1914struct mlx5_ifc_traffic_counter_bits {
1915 u8 packets[0x40];
1916
1917 u8 octets[0x40];
1918};
1919
1920struct mlx5_ifc_tisc_bits {
1921 u8 reserved_0[0xc];
1922 u8 prio[0x4];
1923 u8 reserved_1[0x10];
1924
1925 u8 reserved_2[0x100];
1926
1927 u8 reserved_3[0x8];
1928 u8 transport_domain[0x18];
1929
1930 u8 reserved_4[0x3c0];
1931};
1932
1933enum {
1934 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
1935 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
1936};
1937
1938enum {
1939 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
1940 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
1941};
1942
1943enum {
2be6967c
SM		 1944 MLX5_RX_HASH_FN_NONE = 0x0,
1945 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
1946 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 1947};
1948
1949enum {
1950 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
1951 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
1952};
1953
1954struct mlx5_ifc_tirc_bits {
1955 u8 reserved_0[0x20];
1956
1957 u8 disp_type[0x4];
1958 u8 reserved_1[0x1c];
1959
1960 u8 reserved_2[0x40];
1961
1962 u8 reserved_3[0x4];
1963 u8 lro_timeout_period_usecs[0x10];
1964 u8 lro_enable_mask[0x4];
1965 u8 lro_max_ip_payload_size[0x8];
1966
1967 u8 reserved_4[0x40];
1968
1969 u8 reserved_5[0x8];
1970 u8 inline_rqn[0x18];
1971
1972 u8 rx_hash_symmetric[0x1];
1973 u8 reserved_6[0x1];
1974 u8 tunneled_offload_en[0x1];
1975 u8 reserved_7[0x5];
1976 u8 indirect_table[0x18];
1977
1978 u8 rx_hash_fn[0x4];
1979 u8 reserved_8[0x2];
1980 u8 self_lb_block[0x2];
1981 u8 transport_domain[0x18];
1982
1983 u8 rx_hash_toeplitz_key[10][0x20];
1984
1985 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1986
1987 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1988
1989 u8 reserved_9[0x4c0];
1990};
1991
1992enum {
1993 MLX5_SRQC_STATE_GOOD = 0x0,
1994 MLX5_SRQC_STATE_ERROR = 0x1,
1995};
1996
1997struct mlx5_ifc_srqc_bits {
1998 u8 state[0x4];
1999 u8 log_srq_size[0x4];
2000 u8 reserved_0[0x18];
2001
2002 u8 wq_signature[0x1];
2003 u8 cont_srq[0x1];
2004 u8 reserved_1[0x1];
2005 u8 rlky[0x1];
2006 u8 reserved_2[0x1];
2007 u8 log_rq_stride[0x3];
2008 u8 xrcd[0x18];
2009
2010 u8 page_offset[0x6];
2011 u8 reserved_3[0x2];
2012 u8 cqn[0x18];
2013
2014 u8 reserved_4[0x20];
2015
2016 u8 reserved_5[0x2];
2017 u8 log_page_size[0x6];
2018 u8 reserved_6[0x18];
2019
2020 u8 reserved_7[0x20];
2021
2022 u8 reserved_8[0x8];
2023 u8 pd[0x18];
2024
2025 u8 lwm[0x10];
2026 u8 wqe_cnt[0x10];
2027
2028 u8 reserved_9[0x40];
2029
01949d01 2030 u8 dbr_addr[0x40];
e281682b 2031
01949d01 2032 u8 reserved_10[0x80];
e281682b
SM		 2033};
2034
2035enum {
2036 MLX5_SQC_STATE_RST = 0x0,
2037 MLX5_SQC_STATE_RDY = 0x1,
2038 MLX5_SQC_STATE_ERR = 0x3,
2039};
2040
2041struct mlx5_ifc_sqc_bits {
2042 u8 rlky[0x1];
2043 u8 cd_master[0x1];
2044 u8 fre[0x1];
2045 u8 flush_in_error_en[0x1];
2046 u8 reserved_0[0x4];
2047 u8 state[0x4];
2048 u8 reserved_1[0x14];
2049
2050 u8 reserved_2[0x8];
2051 u8 user_index[0x18];
2052
2053 u8 reserved_3[0x8];
2054 u8 cqn[0x18];
2055
2056 u8 reserved_4[0xa0];
2057
2058 u8 tis_lst_sz[0x10];
2059 u8 reserved_5[0x10];
2060
2061 u8 reserved_6[0x40];
2062
2063 u8 reserved_7[0x8];
2064 u8 tis_num_0[0x18];
2065
2066 struct mlx5_ifc_wq_bits wq;
2067};
2068
2069struct mlx5_ifc_rqtc_bits {
2070 u8 reserved_0[0xa0];
2071
2072 u8 reserved_1[0x10];
2073 u8 rqt_max_size[0x10];
2074
2075 u8 reserved_2[0x10];
2076 u8 rqt_actual_size[0x10];
2077
2078 u8 reserved_3[0x6a0];
2079
2080 struct mlx5_ifc_rq_num_bits rq_num[0];
2081};
2082
2083enum {
2084 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2085 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2086};
2087
2088enum {
2089 MLX5_RQC_STATE_RST = 0x0,
2090 MLX5_RQC_STATE_RDY = 0x1,
2091 MLX5_RQC_STATE_ERR = 0x3,
2092};
2093
2094struct mlx5_ifc_rqc_bits {
2095 u8 rlky[0x1];
2096 u8 reserved_0[0x2];
2097 u8 vsd[0x1];
2098 u8 mem_rq_type[0x4];
2099 u8 state[0x4];
2100 u8 reserved_1[0x1];
2101 u8 flush_in_error_en[0x1];
2102 u8 reserved_2[0x12];
2103
2104 u8 reserved_3[0x8];
2105 u8 user_index[0x18];
2106
2107 u8 reserved_4[0x8];
2108 u8 cqn[0x18];
2109
2110 u8 counter_set_id[0x8];
2111 u8 reserved_5[0x18];
2112
2113 u8 reserved_6[0x8];
2114 u8 rmpn[0x18];
2115
2116 u8 reserved_7[0xe0];
2117
2118 struct mlx5_ifc_wq_bits wq;
2119};
2120
2121enum {
2122 MLX5_RMPC_STATE_RDY = 0x1,
2123 MLX5_RMPC_STATE_ERR = 0x3,
2124};
2125
2126struct mlx5_ifc_rmpc_bits {
2127 u8 reserved_0[0x8];
2128 u8 state[0x4];
2129 u8 reserved_1[0x14];
2130
2131 u8 basic_cyclic_rcv_wqe[0x1];
2132 u8 reserved_2[0x1f];
2133
2134 u8 reserved_3[0x140];
2135
2136 struct mlx5_ifc_wq_bits wq;
2137};
2138
2139enum {
2140 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0,
2141};
2142
2143struct mlx5_ifc_nic_vport_context_bits {
2144 u8 reserved_0[0x1f];
2145 u8 roce_en[0x1];
2146
9efa7525
AS		 2147 u8 reserved_1[0x120];
2148
2149 u8 system_image_guid[0x40];
2150 u8 port_guid[0x40];
2151 u8 node_guid[0x40];
2152
2153 u8 reserved_5[0x140];
2154 u8 qkey_violation_counter[0x10];
2155 u8 reserved_6[0x430];
e281682b
SM		 2156
2157 u8 reserved_2[0x5];
2158 u8 allowed_list_type[0x3];
2159 u8 reserved_3[0xc];
2160 u8 allowed_list_size[0xc];
2161
2162 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2163
2164 u8 reserved_4[0x20];
2165
2166 u8 current_uc_mac_address[0][0x40];
2167};
2168
2169enum {
2170 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2171 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2172 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2173};
2174
2175struct mlx5_ifc_mkc_bits {
2176 u8 reserved_0[0x1];
2177 u8 free[0x1];
2178 u8 reserved_1[0xd];
2179 u8 small_fence_on_rdma_read_response[0x1];
2180 u8 umr_en[0x1];
2181 u8 a[0x1];
2182 u8 rw[0x1];
2183 u8 rr[0x1];
2184 u8 lw[0x1];
2185 u8 lr[0x1];
2186 u8 access_mode[0x2];
2187 u8 reserved_2[0x8];
2188
2189 u8 qpn[0x18];
2190 u8 mkey_7_0[0x8];
2191
2192 u8 reserved_3[0x20];
2193
2194 u8 length64[0x1];
2195 u8 bsf_en[0x1];
2196 u8 sync_umr[0x1];
2197 u8 reserved_4[0x2];
2198 u8 expected_sigerr_count[0x1];
2199 u8 reserved_5[0x1];
2200 u8 en_rinval[0x1];
2201 u8 pd[0x18];
2202
2203 u8 start_addr[0x40];
2204
2205 u8 len[0x40];
2206
2207 u8 bsf_octword_size[0x20];
2208
2209 u8 reserved_6[0x80];
2210
2211 u8 translations_octword_size[0x20];
2212
2213 u8 reserved_7[0x1b];
2214 u8 log_page_size[0x5];
2215
2216 u8 reserved_8[0x20];
2217};
2218
2219struct mlx5_ifc_pkey_bits {
2220 u8 reserved_0[0x10];
2221 u8 pkey[0x10];
2222};
2223
2224struct mlx5_ifc_array128_auto_bits {
2225 u8 array128_auto[16][0x8];
2226};
2227
2228struct mlx5_ifc_hca_vport_context_bits {
2229 u8 field_select[0x20];
2230
2231 u8 reserved_0[0xe0];
2232
2233 u8 sm_virt_aware[0x1];
2234 u8 has_smi[0x1];
2235 u8 has_raw[0x1];
2236 u8 grh_required[0x1];
707c4602
MD		 2237 u8 reserved_1[0xc];
2238 u8 port_physical_state[0x4];
2239 u8 vport_state_policy[0x4];
2240 u8 port_state[0x4];
e281682b
SM		 2241 u8 vport_state[0x4];
2242
707c4602
MD		 2243 u8 reserved_2[0x20];
2244
2245 u8 system_image_guid[0x40];
e281682b
SM		 2246
2247 u8 port_guid[0x40];
2248
2249 u8 node_guid[0x40];
2250
2251 u8 cap_mask1[0x20];
2252
2253 u8 cap_mask1_field_select[0x20];
2254
2255 u8 cap_mask2[0x20];
2256
2257 u8 cap_mask2_field_select[0x20];
2258
2259 u8 reserved_3[0x80];
2260
2261 u8 lid[0x10];
2262 u8 reserved_4[0x4];
2263 u8 init_type_reply[0x4];
2264 u8 lmc[0x3];
2265 u8 subnet_timeout[0x5];
2266
2267 u8 sm_lid[0x10];
2268 u8 sm_sl[0x4];
2269 u8 reserved_5[0xc];
2270
2271 u8 qkey_violation_counter[0x10];
2272 u8 pkey_violation_counter[0x10];
2273
2274 u8 reserved_6[0xca0];
2275};
2276
2277enum {
2278 MLX5_EQC_STATUS_OK = 0x0,
2279 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2280};
2281
2282enum {
2283 MLX5_EQC_ST_ARMED = 0x9,
2284 MLX5_EQC_ST_FIRED = 0xa,
2285};
2286
2287struct mlx5_ifc_eqc_bits {
2288 u8 status[0x4];
2289 u8 reserved_0[0x9];
2290 u8 ec[0x1];
2291 u8 oi[0x1];
2292 u8 reserved_1[0x5];
2293 u8 st[0x4];
2294 u8 reserved_2[0x8];
2295
2296 u8 reserved_3[0x20];
2297
2298 u8 reserved_4[0x14];
2299 u8 page_offset[0x6];
2300 u8 reserved_5[0x6];
2301
2302 u8 reserved_6[0x3];
2303 u8 log_eq_size[0x5];
2304 u8 uar_page[0x18];
2305
2306 u8 reserved_7[0x20];
2307
2308 u8 reserved_8[0x18];
2309 u8 intr[0x8];
2310
2311 u8 reserved_9[0x3];
2312 u8 log_page_size[0x5];
2313 u8 reserved_10[0x18];
2314
2315 u8 reserved_11[0x60];
2316
2317 u8 reserved_12[0x8];
2318 u8 consumer_counter[0x18];
2319
2320 u8 reserved_13[0x8];
2321 u8 producer_counter[0x18];
2322
2323 u8 reserved_14[0x80];
2324};
2325
2326enum {
2327 MLX5_DCTC_STATE_ACTIVE = 0x0,
2328 MLX5_DCTC_STATE_DRAINING = 0x1,
2329 MLX5_DCTC_STATE_DRAINED = 0x2,
2330};
2331
2332enum {
2333 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2334 MLX5_DCTC_CS_RES_NA = 0x1,
2335 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2336};
2337
2338enum {
2339 MLX5_DCTC_MTU_256_BYTES = 0x1,
2340 MLX5_DCTC_MTU_512_BYTES = 0x2,
2341 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2342 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2343 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2344};
2345
2346struct mlx5_ifc_dctc_bits {
2347 u8 reserved_0[0x4];
2348 u8 state[0x4];
2349 u8 reserved_1[0x18];
2350
2351 u8 reserved_2[0x8];
2352 u8 user_index[0x18];
2353
2354 u8 reserved_3[0x8];
2355 u8 cqn[0x18];
2356
2357 u8 counter_set_id[0x8];
2358 u8 atomic_mode[0x4];
2359 u8 rre[0x1];
2360 u8 rwe[0x1];
2361 u8 rae[0x1];
2362 u8 atomic_like_write_en[0x1];
2363 u8 latency_sensitive[0x1];
2364 u8 rlky[0x1];
2365 u8 free_ar[0x1];
2366 u8 reserved_4[0xd];
2367
2368 u8 reserved_5[0x8];
2369 u8 cs_res[0x8];
2370 u8 reserved_6[0x3];
2371 u8 min_rnr_nak[0x5];
2372 u8 reserved_7[0x8];
2373
2374 u8 reserved_8[0x8];
2375 u8 srqn[0x18];
2376
2377 u8 reserved_9[0x8];
2378 u8 pd[0x18];
2379
2380 u8 tclass[0x8];
2381 u8 reserved_10[0x4];
2382 u8 flow_label[0x14];
2383
2384 u8 dc_access_key[0x40];
2385
2386 u8 reserved_11[0x5];
2387 u8 mtu[0x3];
2388 u8 port[0x8];
2389 u8 pkey_index[0x10];
2390
2391 u8 reserved_12[0x8];
2392 u8 my_addr_index[0x8];
2393 u8 reserved_13[0x8];
2394 u8 hop_limit[0x8];
2395
2396 u8 dc_access_key_violation_count[0x20];
2397
2398 u8 reserved_14[0x14];
2399 u8 dei_cfi[0x1];
2400 u8 eth_prio[0x3];
2401 u8 ecn[0x2];
2402 u8 dscp[0x6];
2403
2404 u8 reserved_15[0x40];
2405};
2406
2407enum {
2408 MLX5_CQC_STATUS_OK = 0x0,
2409 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2410 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2411};
2412
2413enum {
2414 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2415 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2416};
2417
2418enum {
2419 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2420 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2421 MLX5_CQC_ST_FIRED = 0xa,
2422};
2423
2424struct mlx5_ifc_cqc_bits {
2425 u8 status[0x4];
2426 u8 reserved_0[0x4];
2427 u8 cqe_sz[0x3];
2428 u8 cc[0x1];
2429 u8 reserved_1[0x1];
2430 u8 scqe_break_moderation_en[0x1];
2431 u8 oi[0x1];
2432 u8 reserved_2[0x2];
2433 u8 cqe_zip_en[0x1];
2434 u8 mini_cqe_res_format[0x2];
2435 u8 st[0x4];
2436 u8 reserved_3[0x8];
2437
2438 u8 reserved_4[0x20];
2439
2440 u8 reserved_5[0x14];
2441 u8 page_offset[0x6];
2442 u8 reserved_6[0x6];
2443
2444 u8 reserved_7[0x3];
2445 u8 log_cq_size[0x5];
2446 u8 uar_page[0x18];
2447
2448 u8 reserved_8[0x4];
2449 u8 cq_period[0xc];
2450 u8 cq_max_count[0x10];
2451
2452 u8 reserved_9[0x18];
2453 u8 c_eqn[0x8];
2454
2455 u8 reserved_10[0x3];
2456 u8 log_page_size[0x5];
2457 u8 reserved_11[0x18];
2458
2459 u8 reserved_12[0x20];
2460
2461 u8 reserved_13[0x8];
2462 u8 last_notified_index[0x18];
2463
2464 u8 reserved_14[0x8];
2465 u8 last_solicit_index[0x18];
2466
2467 u8 reserved_15[0x8];
2468 u8 consumer_counter[0x18];
2469
2470 u8 reserved_16[0x8];
2471 u8 producer_counter[0x18];
2472
2473 u8 reserved_17[0x40];
2474
2475 u8 dbr_addr[0x40];
2476};
2477
2478union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2479 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2480 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2481 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2482 u8 reserved_0[0x800];
2483};
2484
2485struct mlx5_ifc_query_adapter_param_block_bits {
211e6c80 2486 u8 reserved_0[0xc0];
e281682b 2487
211e6c80
MD		 2488 u8 reserved_1[0x8];
2489 u8 ieee_vendor_id[0x18];
2490
2491 u8 reserved_2[0x10];
e281682b
SM		 2492 u8 vsd_vendor_id[0x10];
2493
2494 u8 vsd[208][0x8];
2495
2496 u8 vsd_contd_psid[16][0x8];
2497};
2498
2499union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2500 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2501 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2502 u8 reserved_0[0x20];
2503};
2504
2505union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2506 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2507 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2508 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2509 u8 reserved_0[0x20];
2510};
2511
2512union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2513 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2514 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2515 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2516 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2517 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2518 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2519 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2520 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2521 u8 reserved_0[0x7c0];
2522};
2523
2524union mlx5_ifc_event_auto_bits {
2525 struct mlx5_ifc_comp_event_bits comp_event;
2526 struct mlx5_ifc_dct_events_bits dct_events;
2527 struct mlx5_ifc_qp_events_bits qp_events;
2528 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2529 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2530 struct mlx5_ifc_cq_error_bits cq_error;
2531 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2532 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2533 struct mlx5_ifc_gpio_event_bits gpio_event;
2534 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2535 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2536 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2537 u8 reserved_0[0xe0];
2538};
2539
2540struct mlx5_ifc_health_buffer_bits {
2541 u8 reserved_0[0x100];
2542
2543 u8 assert_existptr[0x20];
2544
2545 u8 assert_callra[0x20];
2546
2547 u8 reserved_1[0x40];
2548
2549 u8 fw_version[0x20];
2550
2551 u8 hw_id[0x20];
2552
2553 u8 reserved_2[0x20];
2554
2555 u8 irisc_index[0x8];
2556 u8 synd[0x8];
2557 u8 ext_synd[0x10];
2558};
2559
2560struct mlx5_ifc_register_loopback_control_bits {
2561 u8 no_lb[0x1];
2562 u8 reserved_0[0x7];
2563 u8 port[0x8];
2564 u8 reserved_1[0x10];
2565
2566 u8 reserved_2[0x60];
2567};
2568
2569struct mlx5_ifc_teardown_hca_out_bits {
2570 u8 status[0x8];
2571 u8 reserved_0[0x18];
2572
2573 u8 syndrome[0x20];
2574
2575 u8 reserved_1[0x40];
2576};
2577
2578enum {
2579 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2580 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2581};
2582
2583struct mlx5_ifc_teardown_hca_in_bits {
2584 u8 opcode[0x10];
2585 u8 reserved_0[0x10];
2586
2587 u8 reserved_1[0x10];
2588 u8 op_mod[0x10];
2589
2590 u8 reserved_2[0x10];
2591 u8 profile[0x10];
2592
2593 u8 reserved_3[0x20];
2594};
2595
2596struct mlx5_ifc_sqerr2rts_qp_out_bits {
2597 u8 status[0x8];
2598 u8 reserved_0[0x18];
2599
2600 u8 syndrome[0x20];
2601
2602 u8 reserved_1[0x40];
2603};
2604
2605struct mlx5_ifc_sqerr2rts_qp_in_bits {
2606 u8 opcode[0x10];
2607 u8 reserved_0[0x10];
2608
2609 u8 reserved_1[0x10];
2610 u8 op_mod[0x10];
2611
2612 u8 reserved_2[0x8];
2613 u8 qpn[0x18];
2614
2615 u8 reserved_3[0x20];
2616
2617 u8 opt_param_mask[0x20];
2618
2619 u8 reserved_4[0x20];
2620
2621 struct mlx5_ifc_qpc_bits qpc;
2622
2623 u8 reserved_5[0x80];
2624};
2625
2626struct mlx5_ifc_sqd2rts_qp_out_bits {
2627 u8 status[0x8];
2628 u8 reserved_0[0x18];
2629
2630 u8 syndrome[0x20];
2631
2632 u8 reserved_1[0x40];
2633};
2634
2635struct mlx5_ifc_sqd2rts_qp_in_bits {
2636 u8 opcode[0x10];
2637 u8 reserved_0[0x10];
2638
2639 u8 reserved_1[0x10];
2640 u8 op_mod[0x10];
2641
2642 u8 reserved_2[0x8];
2643 u8 qpn[0x18];
2644
2645 u8 reserved_3[0x20];
2646
2647 u8 opt_param_mask[0x20];
2648
2649 u8 reserved_4[0x20];
2650
2651 struct mlx5_ifc_qpc_bits qpc;
2652
2653 u8 reserved_5[0x80];
2654};
2655
2656struct mlx5_ifc_set_roce_address_out_bits {
2657 u8 status[0x8];
2658 u8 reserved_0[0x18];
2659
2660 u8 syndrome[0x20];
2661
2662 u8 reserved_1[0x40];
2663};
2664
2665struct mlx5_ifc_set_roce_address_in_bits {
2666 u8 opcode[0x10];
2667 u8 reserved_0[0x10];
2668
2669 u8 reserved_1[0x10];
2670 u8 op_mod[0x10];
2671
2672 u8 roce_address_index[0x10];
2673 u8 reserved_2[0x10];
2674
2675 u8 reserved_3[0x20];
2676
2677 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2678};
2679
2680struct mlx5_ifc_set_mad_demux_out_bits {
2681 u8 status[0x8];
2682 u8 reserved_0[0x18];
2683
2684 u8 syndrome[0x20];
2685
2686 u8 reserved_1[0x40];
2687};
2688
2689enum {
2690 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
2691 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
2692};
2693
2694struct mlx5_ifc_set_mad_demux_in_bits {
2695 u8 opcode[0x10];
2696 u8 reserved_0[0x10];
2697
2698 u8 reserved_1[0x10];
2699 u8 op_mod[0x10];
2700
2701 u8 reserved_2[0x20];
2702
2703 u8 reserved_3[0x6];
2704 u8 demux_mode[0x2];
2705 u8 reserved_4[0x18];
2706};
2707
2708struct mlx5_ifc_set_l2_table_entry_out_bits {
2709 u8 status[0x8];
2710 u8 reserved_0[0x18];
2711
2712 u8 syndrome[0x20];
2713
2714 u8 reserved_1[0x40];
2715};
2716
2717struct mlx5_ifc_set_l2_table_entry_in_bits {
2718 u8 opcode[0x10];
2719 u8 reserved_0[0x10];
2720
2721 u8 reserved_1[0x10];
2722 u8 op_mod[0x10];
2723
2724 u8 reserved_2[0x60];
2725
2726 u8 reserved_3[0x8];
2727 u8 table_index[0x18];
2728
2729 u8 reserved_4[0x20];
2730
2731 u8 reserved_5[0x13];
2732 u8 vlan_valid[0x1];
2733 u8 vlan[0xc];
2734
2735 struct mlx5_ifc_mac_address_layout_bits mac_address;
2736
2737 u8 reserved_6[0xc0];
2738};
2739
2740struct mlx5_ifc_set_issi_out_bits {
2741 u8 status[0x8];
2742 u8 reserved_0[0x18];
2743
2744 u8 syndrome[0x20];
2745
2746 u8 reserved_1[0x40];
2747};
2748
2749struct mlx5_ifc_set_issi_in_bits {
2750 u8 opcode[0x10];
2751 u8 reserved_0[0x10];
2752
2753 u8 reserved_1[0x10];
2754 u8 op_mod[0x10];
2755
2756 u8 reserved_2[0x10];
2757 u8 current_issi[0x10];
2758
2759 u8 reserved_3[0x20];
2760};
2761
2762struct mlx5_ifc_set_hca_cap_out_bits {
2763 u8 status[0x8];
2764 u8 reserved_0[0x18];
2765
2766 u8 syndrome[0x20];
2767
2768 u8 reserved_1[0x40];
2769};
2770
2771struct mlx5_ifc_set_hca_cap_in_bits {
2772 u8 opcode[0x10];
2773 u8 reserved_0[0x10];
2774
2775 u8 reserved_1[0x10];
2776 u8 op_mod[0x10];
2777
2778 u8 reserved_2[0x40];
2779
2780 union mlx5_ifc_hca_cap_union_bits capability;
2781};
2782
2783struct mlx5_ifc_set_fte_out_bits {
2784 u8 status[0x8];
2785 u8 reserved_0[0x18];
2786
2787 u8 syndrome[0x20];
2788
2789 u8 reserved_1[0x40];
2790};
2791
2792struct mlx5_ifc_set_fte_in_bits {
2793 u8 opcode[0x10];
2794 u8 reserved_0[0x10];
2795
2796 u8 reserved_1[0x10];
2797 u8 op_mod[0x10];
2798
2799 u8 reserved_2[0x40];
2800
2801 u8 table_type[0x8];
2802 u8 reserved_3[0x18];
2803
2804 u8 reserved_4[0x8];
2805 u8 table_id[0x18];
2806
2807 u8 reserved_5[0x40];
2808
2809 u8 flow_index[0x20];
2810
2811 u8 reserved_6[0xe0];
2812
2813 struct mlx5_ifc_flow_context_bits flow_context;
2814};
2815
2816struct mlx5_ifc_rts2rts_qp_out_bits {
2817 u8 status[0x8];
2818 u8 reserved_0[0x18];
2819
2820 u8 syndrome[0x20];
2821
2822 u8 reserved_1[0x40];
2823};
2824
2825struct mlx5_ifc_rts2rts_qp_in_bits {
2826 u8 opcode[0x10];
2827 u8 reserved_0[0x10];
2828
2829 u8 reserved_1[0x10];
2830 u8 op_mod[0x10];
2831
2832 u8 reserved_2[0x8];
2833 u8 qpn[0x18];
2834
2835 u8 reserved_3[0x20];
2836
2837 u8 opt_param_mask[0x20];
2838
2839 u8 reserved_4[0x20];
2840
2841 struct mlx5_ifc_qpc_bits qpc;
2842
2843 u8 reserved_5[0x80];
2844};
2845
2846struct mlx5_ifc_rtr2rts_qp_out_bits {
2847 u8 status[0x8];
2848 u8 reserved_0[0x18];
2849
2850 u8 syndrome[0x20];
2851
2852 u8 reserved_1[0x40];
2853};
2854
2855struct mlx5_ifc_rtr2rts_qp_in_bits {
2856 u8 opcode[0x10];
2857 u8 reserved_0[0x10];
2858
2859 u8 reserved_1[0x10];
2860 u8 op_mod[0x10];
2861
2862 u8 reserved_2[0x8];
2863 u8 qpn[0x18];
2864
2865 u8 reserved_3[0x20];
2866
2867 u8 opt_param_mask[0x20];
2868
2869 u8 reserved_4[0x20];
2870
2871 struct mlx5_ifc_qpc_bits qpc;
2872
2873 u8 reserved_5[0x80];
2874};
2875
2876struct mlx5_ifc_rst2init_qp_out_bits {
2877 u8 status[0x8];
2878 u8 reserved_0[0x18];
2879
2880 u8 syndrome[0x20];
2881
2882 u8 reserved_1[0x40];
2883};
2884
2885struct mlx5_ifc_rst2init_qp_in_bits {
2886 u8 opcode[0x10];
2887 u8 reserved_0[0x10];
2888
2889 u8 reserved_1[0x10];
2890 u8 op_mod[0x10];
2891
2892 u8 reserved_2[0x8];
2893 u8 qpn[0x18];
2894
2895 u8 reserved_3[0x20];
2896
2897 u8 opt_param_mask[0x20];
2898
2899 u8 reserved_4[0x20];
2900
2901 struct mlx5_ifc_qpc_bits qpc;
2902
2903 u8 reserved_5[0x80];
2904};
2905
2906struct mlx5_ifc_query_xrc_srq_out_bits {
2907 u8 status[0x8];
2908 u8 reserved_0[0x18];
2909
2910 u8 syndrome[0x20];
2911
2912 u8 reserved_1[0x40];
2913
2914 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
2915
2916 u8 reserved_2[0x600];
2917
2918 u8 pas[0][0x40];
2919};
2920
2921struct mlx5_ifc_query_xrc_srq_in_bits {
2922 u8 opcode[0x10];
2923 u8 reserved_0[0x10];
2924
2925 u8 reserved_1[0x10];
2926 u8 op_mod[0x10];
2927
2928 u8 reserved_2[0x8];
2929 u8 xrc_srqn[0x18];
2930
2931 u8 reserved_3[0x20];
2932};
2933
2934enum {
2935 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
2936 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
2937};
2938
2939struct mlx5_ifc_query_vport_state_out_bits {
2940 u8 status[0x8];
2941 u8 reserved_0[0x18];
2942
2943 u8 syndrome[0x20];
2944
2945 u8 reserved_1[0x20];
2946
2947 u8 reserved_2[0x18];
2948 u8 admin_state[0x4];
2949 u8 state[0x4];
2950};
2951
2952enum {
2953 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
2954};
2955
2956struct mlx5_ifc_query_vport_state_in_bits {
2957 u8 opcode[0x10];
2958 u8 reserved_0[0x10];
2959
2960 u8 reserved_1[0x10];
2961 u8 op_mod[0x10];
2962
2963 u8 other_vport[0x1];
2964 u8 reserved_2[0xf];
2965 u8 vport_number[0x10];
2966
2967 u8 reserved_3[0x20];
2968};
2969
2970struct mlx5_ifc_query_vport_counter_out_bits {
2971 u8 status[0x8];
2972 u8 reserved_0[0x18];
2973
2974 u8 syndrome[0x20];
2975
2976 u8 reserved_1[0x40];
2977
2978 struct mlx5_ifc_traffic_counter_bits received_errors;
2979
2980 struct mlx5_ifc_traffic_counter_bits transmit_errors;
2981
2982 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
2983
2984 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
2985
2986 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
2987
2988 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
2989
2990 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
2991
2992 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
2993
2994 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
2995
2996 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
2997
2998 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
2999
3000 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3001
3002 u8 reserved_2[0xa00];
3003};
3004
3005enum {
3006 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3007};
3008
3009struct mlx5_ifc_query_vport_counter_in_bits {
3010 u8 opcode[0x10];
3011 u8 reserved_0[0x10];
3012
3013 u8 reserved_1[0x10];
3014 u8 op_mod[0x10];
3015
3016 u8 other_vport[0x1];
3017 u8 reserved_2[0xf];
3018 u8 vport_number[0x10];
3019
3020 u8 reserved_3[0x60];
3021
3022 u8 clear[0x1];
3023 u8 reserved_4[0x1f];
3024
3025 u8 reserved_5[0x20];
3026};
3027
3028struct mlx5_ifc_query_tis_out_bits {
3029 u8 status[0x8];
3030 u8 reserved_0[0x18];
3031
3032 u8 syndrome[0x20];
3033
3034 u8 reserved_1[0x40];
3035
3036 struct mlx5_ifc_tisc_bits tis_context;
3037};
3038
3039struct mlx5_ifc_query_tis_in_bits {
3040 u8 opcode[0x10];
3041 u8 reserved_0[0x10];
3042
3043 u8 reserved_1[0x10];
3044 u8 op_mod[0x10];
3045
3046 u8 reserved_2[0x8];
3047 u8 tisn[0x18];
3048
3049 u8 reserved_3[0x20];
3050};
3051
3052struct mlx5_ifc_query_tir_out_bits {
3053 u8 status[0x8];
3054 u8 reserved_0[0x18];
3055
3056 u8 syndrome[0x20];
3057
3058 u8 reserved_1[0xc0];
3059
3060 struct mlx5_ifc_tirc_bits tir_context;
3061};
3062
3063struct mlx5_ifc_query_tir_in_bits {
3064 u8 opcode[0x10];
3065 u8 reserved_0[0x10];
3066
3067 u8 reserved_1[0x10];
3068 u8 op_mod[0x10];
3069
3070 u8 reserved_2[0x8];
3071 u8 tirn[0x18];
3072
3073 u8 reserved_3[0x20];
3074};
3075
3076struct mlx5_ifc_query_srq_out_bits {
3077 u8 status[0x8];
3078 u8 reserved_0[0x18];
3079
3080 u8 syndrome[0x20];
3081
3082 u8 reserved_1[0x40];
3083
3084 struct mlx5_ifc_srqc_bits srq_context_entry;
3085
3086 u8 reserved_2[0x600];
3087
3088 u8 pas[0][0x40];
3089};
3090
3091struct mlx5_ifc_query_srq_in_bits {
3092 u8 opcode[0x10];
3093 u8 reserved_0[0x10];
3094
3095 u8 reserved_1[0x10];
3096 u8 op_mod[0x10];
3097
3098 u8 reserved_2[0x8];
3099 u8 srqn[0x18];
3100
3101 u8 reserved_3[0x20];
3102};
3103
3104struct mlx5_ifc_query_sq_out_bits {
3105 u8 status[0x8];
3106 u8 reserved_0[0x18];
3107
3108 u8 syndrome[0x20];
3109
3110 u8 reserved_1[0xc0];
3111
3112 struct mlx5_ifc_sqc_bits sq_context;
3113};
3114
3115struct mlx5_ifc_query_sq_in_bits {
3116 u8 opcode[0x10];
3117 u8 reserved_0[0x10];
3118
3119 u8 reserved_1[0x10];
3120 u8 op_mod[0x10];
3121
3122 u8 reserved_2[0x8];
3123 u8 sqn[0x18];
3124
3125 u8 reserved_3[0x20];
3126};
3127
3128struct mlx5_ifc_query_special_contexts_out_bits {
3129 u8 status[0x8];
3130 u8 reserved_0[0x18];
3131
3132 u8 syndrome[0x20];
3133
3134 u8 reserved_1[0x20];
3135
3136 u8 resd_lkey[0x20];
3137};
3138
3139struct mlx5_ifc_query_special_contexts_in_bits {
3140 u8 opcode[0x10];
3141 u8 reserved_0[0x10];
3142
3143 u8 reserved_1[0x10];
3144 u8 op_mod[0x10];
3145
3146 u8 reserved_2[0x40];
3147};
3148
3149struct mlx5_ifc_query_rqt_out_bits {
3150 u8 status[0x8];
3151 u8 reserved_0[0x18];
3152
3153 u8 syndrome[0x20];
3154
3155 u8 reserved_1[0xc0];
3156
3157 struct mlx5_ifc_rqtc_bits rqt_context;
3158};
3159
3160struct mlx5_ifc_query_rqt_in_bits {
3161 u8 opcode[0x10];
3162 u8 reserved_0[0x10];
3163
3164 u8 reserved_1[0x10];
3165 u8 op_mod[0x10];
3166
3167 u8 reserved_2[0x8];
3168 u8 rqtn[0x18];
3169
3170 u8 reserved_3[0x20];
3171};
3172
3173struct mlx5_ifc_query_rq_out_bits {
3174 u8 status[0x8];
3175 u8 reserved_0[0x18];
3176
3177 u8 syndrome[0x20];
3178
3179 u8 reserved_1[0xc0];
3180
3181 struct mlx5_ifc_rqc_bits rq_context;
3182};
3183
3184struct mlx5_ifc_query_rq_in_bits {
3185 u8 opcode[0x10];
3186 u8 reserved_0[0x10];
3187
3188 u8 reserved_1[0x10];
3189 u8 op_mod[0x10];
3190
3191 u8 reserved_2[0x8];
3192 u8 rqn[0x18];
3193
3194 u8 reserved_3[0x20];
3195};
3196
3197struct mlx5_ifc_query_roce_address_out_bits {
3198 u8 status[0x8];
3199 u8 reserved_0[0x18];
3200
3201 u8 syndrome[0x20];
3202
3203 u8 reserved_1[0x40];
3204
3205 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3206};
3207
3208struct mlx5_ifc_query_roce_address_in_bits {
3209 u8 opcode[0x10];
3210 u8 reserved_0[0x10];
3211
3212 u8 reserved_1[0x10];
3213 u8 op_mod[0x10];
3214
3215 u8 roce_address_index[0x10];
3216 u8 reserved_2[0x10];
3217
3218 u8 reserved_3[0x20];
3219};
3220
3221struct mlx5_ifc_query_rmp_out_bits {
3222 u8 status[0x8];
3223 u8 reserved_0[0x18];
3224
3225 u8 syndrome[0x20];
3226
3227 u8 reserved_1[0xc0];
3228
3229 struct mlx5_ifc_rmpc_bits rmp_context;
3230};
3231
3232struct mlx5_ifc_query_rmp_in_bits {
3233 u8 opcode[0x10];
3234 u8 reserved_0[0x10];
3235
3236 u8 reserved_1[0x10];
3237 u8 op_mod[0x10];
3238
3239 u8 reserved_2[0x8];
3240 u8 rmpn[0x18];
3241
3242 u8 reserved_3[0x20];
3243};
3244
3245struct mlx5_ifc_query_qp_out_bits {
3246 u8 status[0x8];
3247 u8 reserved_0[0x18];
3248
3249 u8 syndrome[0x20];
3250
3251 u8 reserved_1[0x40];
3252
3253 u8 opt_param_mask[0x20];
3254
3255 u8 reserved_2[0x20];
3256
3257 struct mlx5_ifc_qpc_bits qpc;
3258
3259 u8 reserved_3[0x80];
3260
3261 u8 pas[0][0x40];
3262};
3263
3264struct mlx5_ifc_query_qp_in_bits {
3265 u8 opcode[0x10];
3266 u8 reserved_0[0x10];
3267
3268 u8 reserved_1[0x10];
3269 u8 op_mod[0x10];
3270
3271 u8 reserved_2[0x8];
3272 u8 qpn[0x18];
3273
3274 u8 reserved_3[0x20];
3275};
3276
3277struct mlx5_ifc_query_q_counter_out_bits {
3278 u8 status[0x8];
3279 u8 reserved_0[0x18];
3280
3281 u8 syndrome[0x20];
3282
3283 u8 reserved_1[0x40];
3284
3285 u8 rx_write_requests[0x20];
3286
3287 u8 reserved_2[0x20];
3288
3289 u8 rx_read_requests[0x20];
3290
3291 u8 reserved_3[0x20];
3292
3293 u8 rx_atomic_requests[0x20];
3294
3295 u8 reserved_4[0x20];
3296
3297 u8 rx_dct_connect[0x20];
3298
3299 u8 reserved_5[0x20];
3300
3301 u8 out_of_buffer[0x20];
3302
3303 u8 reserved_6[0x20];
3304
3305 u8 out_of_sequence[0x20];
3306
3307 u8 reserved_7[0x620];
3308};
3309
3310struct mlx5_ifc_query_q_counter_in_bits {
3311 u8 opcode[0x10];
3312 u8 reserved_0[0x10];
3313
3314 u8 reserved_1[0x10];
3315 u8 op_mod[0x10];
3316
3317 u8 reserved_2[0x80];
3318
3319 u8 clear[0x1];
3320 u8 reserved_3[0x1f];
3321
3322 u8 reserved_4[0x18];
3323 u8 counter_set_id[0x8];
3324};
3325
3326struct mlx5_ifc_query_pages_out_bits {
3327 u8 status[0x8];
3328 u8 reserved_0[0x18];
3329
3330 u8 syndrome[0x20];
3331
3332 u8 reserved_1[0x10];
3333 u8 function_id[0x10];
3334
3335 u8 num_pages[0x20];
3336};
3337
3338enum {
3339 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3340 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3341 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3342};
3343
3344struct mlx5_ifc_query_pages_in_bits {
3345 u8 opcode[0x10];
3346 u8 reserved_0[0x10];
3347
3348 u8 reserved_1[0x10];
3349 u8 op_mod[0x10];
3350
3351 u8 reserved_2[0x10];
3352 u8 function_id[0x10];
3353
3354 u8 reserved_3[0x20];
3355};
3356
3357struct mlx5_ifc_query_nic_vport_context_out_bits {
3358 u8 status[0x8];
3359 u8 reserved_0[0x18];
3360
3361 u8 syndrome[0x20];
3362
3363 u8 reserved_1[0x40];
3364
3365 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3366};
3367
3368struct mlx5_ifc_query_nic_vport_context_in_bits {
3369 u8 opcode[0x10];
3370 u8 reserved_0[0x10];
3371
3372 u8 reserved_1[0x10];
3373 u8 op_mod[0x10];
3374
3375 u8 other_vport[0x1];
3376 u8 reserved_2[0xf];
3377 u8 vport_number[0x10];
3378
3379 u8 reserved_3[0x5];
3380 u8 allowed_list_type[0x3];
3381 u8 reserved_4[0x18];
3382};
3383
3384struct mlx5_ifc_query_mkey_out_bits {
3385 u8 status[0x8];
3386 u8 reserved_0[0x18];
3387
3388 u8 syndrome[0x20];
3389
3390 u8 reserved_1[0x40];
3391
3392 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3393
3394 u8 reserved_2[0x600];
3395
3396 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3397
3398 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3399};
3400
3401struct mlx5_ifc_query_mkey_in_bits {
3402 u8 opcode[0x10];
3403 u8 reserved_0[0x10];
3404
3405 u8 reserved_1[0x10];
3406 u8 op_mod[0x10];
3407
3408 u8 reserved_2[0x8];
3409 u8 mkey_index[0x18];
3410
3411 u8 pg_access[0x1];
3412 u8 reserved_3[0x1f];
3413};
3414
3415struct mlx5_ifc_query_mad_demux_out_bits {
3416 u8 status[0x8];
3417 u8 reserved_0[0x18];
3418
3419 u8 syndrome[0x20];
3420
3421 u8 reserved_1[0x40];
3422
3423 u8 mad_dumux_parameters_block[0x20];
3424};
3425
3426struct mlx5_ifc_query_mad_demux_in_bits {
3427 u8 opcode[0x10];
3428 u8 reserved_0[0x10];
3429
3430 u8 reserved_1[0x10];
3431 u8 op_mod[0x10];
3432
3433 u8 reserved_2[0x40];
3434};
3435
3436struct mlx5_ifc_query_l2_table_entry_out_bits {
3437 u8 status[0x8];
3438 u8 reserved_0[0x18];
3439
3440 u8 syndrome[0x20];
3441
3442 u8 reserved_1[0xa0];
3443
3444 u8 reserved_2[0x13];
3445 u8 vlan_valid[0x1];
3446 u8 vlan[0xc];
3447
3448 struct mlx5_ifc_mac_address_layout_bits mac_address;
3449
3450 u8 reserved_3[0xc0];
3451};
3452
3453struct mlx5_ifc_query_l2_table_entry_in_bits {
3454 u8 opcode[0x10];
3455 u8 reserved_0[0x10];
3456
3457 u8 reserved_1[0x10];
3458 u8 op_mod[0x10];
3459
3460 u8 reserved_2[0x60];
3461
3462 u8 reserved_3[0x8];
3463 u8 table_index[0x18];
3464
3465 u8 reserved_4[0x140];
3466};
3467
3468struct mlx5_ifc_query_issi_out_bits {
3469 u8 status[0x8];
3470 u8 reserved_0[0x18];
3471
3472 u8 syndrome[0x20];
3473
3474 u8 reserved_1[0x10];
3475 u8 current_issi[0x10];
3476
3477 u8 reserved_2[0xa0];
3478
3479 u8 supported_issi_reserved[76][0x8];
3480 u8 supported_issi_dw0[0x20];
3481};
3482
3483struct mlx5_ifc_query_issi_in_bits {
3484 u8 opcode[0x10];
3485 u8 reserved_0[0x10];
3486
3487 u8 reserved_1[0x10];
3488 u8 op_mod[0x10];
3489
3490 u8 reserved_2[0x40];
3491};
3492
3493struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3494 u8 status[0x8];
3495 u8 reserved_0[0x18];
3496
3497 u8 syndrome[0x20];
3498
3499 u8 reserved_1[0x40];
3500
3501 struct mlx5_ifc_pkey_bits pkey[0];
3502};
3503
3504struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3505 u8 opcode[0x10];
3506 u8 reserved_0[0x10];
3507
3508 u8 reserved_1[0x10];
3509 u8 op_mod[0x10];
3510
3511 u8 other_vport[0x1];
707c4602
MD		 3512 u8 reserved_2[0xb];
3513 u8 port_num[0x4];
e281682b
SM		 3514 u8 vport_number[0x10];
3515
3516 u8 reserved_3[0x10];
3517 u8 pkey_index[0x10];
3518};
3519
3520struct mlx5_ifc_query_hca_vport_gid_out_bits {
3521 u8 status[0x8];
3522 u8 reserved_0[0x18];
3523
3524 u8 syndrome[0x20];
3525
3526 u8 reserved_1[0x20];
3527
3528 u8 gids_num[0x10];
3529 u8 reserved_2[0x10];
3530
3531 struct mlx5_ifc_array128_auto_bits gid[0];
3532};
3533
3534struct mlx5_ifc_query_hca_vport_gid_in_bits {
3535 u8 opcode[0x10];
3536 u8 reserved_0[0x10];
3537
3538 u8 reserved_1[0x10];
3539 u8 op_mod[0x10];
3540
3541 u8 other_vport[0x1];
707c4602
MD		 3542 u8 reserved_2[0xb];
3543 u8 port_num[0x4];
e281682b
SM		 3544 u8 vport_number[0x10];
3545
3546 u8 reserved_3[0x10];
3547 u8 gid_index[0x10];
3548};
3549
3550struct mlx5_ifc_query_hca_vport_context_out_bits {
3551 u8 status[0x8];
3552 u8 reserved_0[0x18];
3553
3554 u8 syndrome[0x20];
3555
3556 u8 reserved_1[0x40];
3557
3558 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3559};
3560
3561struct mlx5_ifc_query_hca_vport_context_in_bits {
3562 u8 opcode[0x10];
3563 u8 reserved_0[0x10];
3564
3565 u8 reserved_1[0x10];
3566 u8 op_mod[0x10];
3567
3568 u8 other_vport[0x1];
707c4602
MD		 3569 u8 reserved_2[0xb];
3570 u8 port_num[0x4];
e281682b
SM		 3571 u8 vport_number[0x10];
3572
3573 u8 reserved_3[0x20];
3574};
3575
3576struct mlx5_ifc_query_hca_cap_out_bits {
3577 u8 status[0x8];
3578 u8 reserved_0[0x18];
3579
3580 u8 syndrome[0x20];
3581
3582 u8 reserved_1[0x40];
3583
3584 union mlx5_ifc_hca_cap_union_bits capability;
3585};
3586
3587struct mlx5_ifc_query_hca_cap_in_bits {
3588 u8 opcode[0x10];
3589 u8 reserved_0[0x10];
3590
3591 u8 reserved_1[0x10];
3592 u8 op_mod[0x10];
3593
3594 u8 reserved_2[0x40];
3595};
3596
3597struct mlx5_ifc_query_flow_table_out_bits {
3598 u8 status[0x8];
3599 u8 reserved_0[0x18];
3600
3601 u8 syndrome[0x20];
3602
3603 u8 reserved_1[0x80];
3604
3605 u8 reserved_2[0x8];
3606 u8 level[0x8];
3607 u8 reserved_3[0x8];
3608 u8 log_size[0x8];
3609
3610 u8 reserved_4[0x120];
3611};
3612
3613struct mlx5_ifc_query_flow_table_in_bits {
3614 u8 opcode[0x10];
3615 u8 reserved_0[0x10];
3616
3617 u8 reserved_1[0x10];
3618 u8 op_mod[0x10];
3619
3620 u8 reserved_2[0x40];
3621
3622 u8 table_type[0x8];
3623 u8 reserved_3[0x18];
3624
3625 u8 reserved_4[0x8];
3626 u8 table_id[0x18];
3627
3628 u8 reserved_5[0x140];
3629};
3630
3631struct mlx5_ifc_query_fte_out_bits {
3632 u8 status[0x8];
3633 u8 reserved_0[0x18];
3634
3635 u8 syndrome[0x20];
3636
3637 u8 reserved_1[0x1c0];
3638
3639 struct mlx5_ifc_flow_context_bits flow_context;
3640};
3641
3642struct mlx5_ifc_query_fte_in_bits {
3643 u8 opcode[0x10];
3644 u8 reserved_0[0x10];
3645
3646 u8 reserved_1[0x10];
3647 u8 op_mod[0x10];
3648
3649 u8 reserved_2[0x40];
3650
3651 u8 table_type[0x8];
3652 u8 reserved_3[0x18];
3653
3654 u8 reserved_4[0x8];
3655 u8 table_id[0x18];
3656
3657 u8 reserved_5[0x40];
3658
3659 u8 flow_index[0x20];
3660
3661 u8 reserved_6[0xe0];
3662};
3663
3664enum {
3665 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
3666 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
3667 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
3668};
3669
3670struct mlx5_ifc_query_flow_group_out_bits {
3671 u8 status[0x8];
3672 u8 reserved_0[0x18];
3673
3674 u8 syndrome[0x20];
3675
3676 u8 reserved_1[0xa0];
3677
3678 u8 start_flow_index[0x20];
3679
3680 u8 reserved_2[0x20];
3681
3682 u8 end_flow_index[0x20];
3683
3684 u8 reserved_3[0xa0];
3685
3686 u8 reserved_4[0x18];
3687 u8 match_criteria_enable[0x8];
3688
3689 struct mlx5_ifc_fte_match_param_bits match_criteria;
3690
3691 u8 reserved_5[0xe00];
3692};
3693
3694struct mlx5_ifc_query_flow_group_in_bits {
3695 u8 opcode[0x10];
3696 u8 reserved_0[0x10];
3697
3698 u8 reserved_1[0x10];
3699 u8 op_mod[0x10];
3700
3701 u8 reserved_2[0x40];
3702
3703 u8 table_type[0x8];
3704 u8 reserved_3[0x18];
3705
3706 u8 reserved_4[0x8];
3707 u8 table_id[0x18];
3708
3709 u8 group_id[0x20];
3710
3711 u8 reserved_5[0x120];
3712};
3713
3714struct mlx5_ifc_query_eq_out_bits {
3715 u8 status[0x8];
3716 u8 reserved_0[0x18];
3717
3718 u8 syndrome[0x20];
3719
3720 u8 reserved_1[0x40];
3721
3722 struct mlx5_ifc_eqc_bits eq_context_entry;
3723
3724 u8 reserved_2[0x40];
3725
3726 u8 event_bitmask[0x40];
3727
3728 u8 reserved_3[0x580];
3729
3730 u8 pas[0][0x40];
3731};
3732
3733struct mlx5_ifc_query_eq_in_bits {
3734 u8 opcode[0x10];
3735 u8 reserved_0[0x10];
3736
3737 u8 reserved_1[0x10];
3738 u8 op_mod[0x10];
3739
3740 u8 reserved_2[0x18];
3741 u8 eq_number[0x8];
3742
3743 u8 reserved_3[0x20];
3744};
3745
3746struct mlx5_ifc_query_dct_out_bits {
3747 u8 status[0x8];
3748 u8 reserved_0[0x18];
3749
3750 u8 syndrome[0x20];
3751
3752 u8 reserved_1[0x40];
3753
3754 struct mlx5_ifc_dctc_bits dct_context_entry;
3755
3756 u8 reserved_2[0x180];
3757};
3758
3759struct mlx5_ifc_query_dct_in_bits {
3760 u8 opcode[0x10];
3761 u8 reserved_0[0x10];
3762
3763 u8 reserved_1[0x10];
3764 u8 op_mod[0x10];
3765
3766 u8 reserved_2[0x8];
3767 u8 dctn[0x18];
3768
3769 u8 reserved_3[0x20];
3770};
3771
3772struct mlx5_ifc_query_cq_out_bits {
3773 u8 status[0x8];
3774 u8 reserved_0[0x18];
3775
3776 u8 syndrome[0x20];
3777
3778 u8 reserved_1[0x40];
3779
3780 struct mlx5_ifc_cqc_bits cq_context;
3781
3782 u8 reserved_2[0x600];
3783
3784 u8 pas[0][0x40];
3785};
3786
3787struct mlx5_ifc_query_cq_in_bits {
3788 u8 opcode[0x10];
3789 u8 reserved_0[0x10];
3790
3791 u8 reserved_1[0x10];
3792 u8 op_mod[0x10];
3793
3794 u8 reserved_2[0x8];
3795 u8 cqn[0x18];
3796
3797 u8 reserved_3[0x20];
3798};
3799
3800struct mlx5_ifc_query_cong_status_out_bits {
3801 u8 status[0x8];
3802 u8 reserved_0[0x18];
3803
3804 u8 syndrome[0x20];
3805
3806 u8 reserved_1[0x20];
3807
3808 u8 enable[0x1];
3809 u8 tag_enable[0x1];
3810 u8 reserved_2[0x1e];
3811};
3812
3813struct mlx5_ifc_query_cong_status_in_bits {
3814 u8 opcode[0x10];
3815 u8 reserved_0[0x10];
3816
3817 u8 reserved_1[0x10];
3818 u8 op_mod[0x10];
3819
3820 u8 reserved_2[0x18];
3821 u8 priority[0x4];
3822 u8 cong_protocol[0x4];
3823
3824 u8 reserved_3[0x20];
3825};
3826
3827struct mlx5_ifc_query_cong_statistics_out_bits {
3828 u8 status[0x8];
3829 u8 reserved_0[0x18];
3830
3831 u8 syndrome[0x20];
3832
3833 u8 reserved_1[0x40];
3834
3835 u8 cur_flows[0x20];
3836
3837 u8 sum_flows[0x20];
3838
3839 u8 cnp_ignored_high[0x20];
3840
3841 u8 cnp_ignored_low[0x20];
3842
3843 u8 cnp_handled_high[0x20];
3844
3845 u8 cnp_handled_low[0x20];
3846
3847 u8 reserved_2[0x100];
3848
3849 u8 time_stamp_high[0x20];
3850
3851 u8 time_stamp_low[0x20];
3852
3853 u8 accumulators_period[0x20];
3854
3855 u8 ecn_marked_roce_packets_high[0x20];
3856
3857 u8 ecn_marked_roce_packets_low[0x20];
3858
3859 u8 cnps_sent_high[0x20];
3860
3861 u8 cnps_sent_low[0x20];
3862
3863 u8 reserved_3[0x560];
3864};
3865
3866struct mlx5_ifc_query_cong_statistics_in_bits {
3867 u8 opcode[0x10];
3868 u8 reserved_0[0x10];
3869
3870 u8 reserved_1[0x10];
3871 u8 op_mod[0x10];
3872
3873 u8 clear[0x1];
3874 u8 reserved_2[0x1f];
3875
3876 u8 reserved_3[0x20];
3877};
3878
3879struct mlx5_ifc_query_cong_params_out_bits {
3880 u8 status[0x8];
3881 u8 reserved_0[0x18];
3882
3883 u8 syndrome[0x20];
3884
3885 u8 reserved_1[0x40];
3886
3887 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
3888};
3889
3890struct mlx5_ifc_query_cong_params_in_bits {
3891 u8 opcode[0x10];
3892 u8 reserved_0[0x10];
3893
3894 u8 reserved_1[0x10];
3895 u8 op_mod[0x10];
3896
3897 u8 reserved_2[0x1c];
3898 u8 cong_protocol[0x4];
3899
3900 u8 reserved_3[0x20];
3901};
3902
3903struct mlx5_ifc_query_adapter_out_bits {
3904 u8 status[0x8];
3905 u8 reserved_0[0x18];
3906
3907 u8 syndrome[0x20];
3908
3909 u8 reserved_1[0x40];
3910
3911 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
3912};
3913
3914struct mlx5_ifc_query_adapter_in_bits {
3915 u8 opcode[0x10];
3916 u8 reserved_0[0x10];
3917
3918 u8 reserved_1[0x10];
3919 u8 op_mod[0x10];
3920
3921 u8 reserved_2[0x40];
3922};
3923
3924struct mlx5_ifc_qp_2rst_out_bits {
3925 u8 status[0x8];
3926 u8 reserved_0[0x18];
3927
3928 u8 syndrome[0x20];
3929
3930 u8 reserved_1[0x40];
3931};
3932
3933struct mlx5_ifc_qp_2rst_in_bits {
3934 u8 opcode[0x10];
3935 u8 reserved_0[0x10];
3936
3937 u8 reserved_1[0x10];
3938 u8 op_mod[0x10];
3939
3940 u8 reserved_2[0x8];
3941 u8 qpn[0x18];
3942
3943 u8 reserved_3[0x20];
3944};
3945
3946struct mlx5_ifc_qp_2err_out_bits {
3947 u8 status[0x8];
3948 u8 reserved_0[0x18];
3949
3950 u8 syndrome[0x20];
3951
3952 u8 reserved_1[0x40];
3953};
3954
3955struct mlx5_ifc_qp_2err_in_bits {
3956 u8 opcode[0x10];
3957 u8 reserved_0[0x10];
3958
3959 u8 reserved_1[0x10];
3960 u8 op_mod[0x10];
3961
3962 u8 reserved_2[0x8];
3963 u8 qpn[0x18];
3964
3965 u8 reserved_3[0x20];
3966};
3967
3968struct mlx5_ifc_page_fault_resume_out_bits {
3969 u8 status[0x8];
3970 u8 reserved_0[0x18];
3971
3972 u8 syndrome[0x20];
3973
3974 u8 reserved_1[0x40];
3975};
3976
3977struct mlx5_ifc_page_fault_resume_in_bits {
3978 u8 opcode[0x10];
3979 u8 reserved_0[0x10];
3980
3981 u8 reserved_1[0x10];
3982 u8 op_mod[0x10];
3983
3984 u8 error[0x1];
3985 u8 reserved_2[0x4];
3986 u8 rdma[0x1];
3987 u8 read_write[0x1];
3988 u8 req_res[0x1];
3989 u8 qpn[0x18];
3990
3991 u8 reserved_3[0x20];
3992};
3993
3994struct mlx5_ifc_nop_out_bits {
3995 u8 status[0x8];
3996 u8 reserved_0[0x18];
3997
3998 u8 syndrome[0x20];
3999
4000 u8 reserved_1[0x40];
4001};
4002
4003struct mlx5_ifc_nop_in_bits {
4004 u8 opcode[0x10];
4005 u8 reserved_0[0x10];
4006
4007 u8 reserved_1[0x10];
4008 u8 op_mod[0x10];
4009
4010 u8 reserved_2[0x40];
4011};
4012
4013struct mlx5_ifc_modify_vport_state_out_bits {
4014 u8 status[0x8];
4015 u8 reserved_0[0x18];
4016
4017 u8 syndrome[0x20];
4018
4019 u8 reserved_1[0x40];
4020};
4021
4022struct mlx5_ifc_modify_vport_state_in_bits {
4023 u8 opcode[0x10];
4024 u8 reserved_0[0x10];
4025
4026 u8 reserved_1[0x10];
4027 u8 op_mod[0x10];
4028
4029 u8 other_vport[0x1];
4030 u8 reserved_2[0xf];
4031 u8 vport_number[0x10];
4032
4033 u8 reserved_3[0x18];
4034 u8 admin_state[0x4];
4035 u8 reserved_4[0x4];
4036};
4037
4038struct mlx5_ifc_modify_tis_out_bits {
4039 u8 status[0x8];
4040 u8 reserved_0[0x18];
4041
4042 u8 syndrome[0x20];
4043
4044 u8 reserved_1[0x40];
4045};
4046
4047struct mlx5_ifc_modify_tis_in_bits {
4048 u8 opcode[0x10];
4049 u8 reserved_0[0x10];
4050
4051 u8 reserved_1[0x10];
4052 u8 op_mod[0x10];
4053
4054 u8 reserved_2[0x8];
4055 u8 tisn[0x18];
4056
4057 u8 reserved_3[0x20];
4058
4059 u8 modify_bitmask[0x40];
4060
4061 u8 reserved_4[0x40];
4062
4063 struct mlx5_ifc_tisc_bits ctx;
4064};
4065
d9eea403 4066struct mlx5_ifc_modify_tir_bitmask_bits {
66189961 4067 u8 reserved_0[0x20];
d9eea403 4068
66189961
TT		 4069 u8 reserved_1[0x1b];
4070 u8 self_lb_en[0x1];
4071 u8 reserved_2[0x3];
d9eea403
AS		 4072 u8 lro[0x1];
4073};
4074
e281682b
SM		 4075struct mlx5_ifc_modify_tir_out_bits {
4076 u8 status[0x8];
4077 u8 reserved_0[0x18];
4078
4079 u8 syndrome[0x20];
4080
4081 u8 reserved_1[0x40];
4082};
4083
4084struct mlx5_ifc_modify_tir_in_bits {
4085 u8 opcode[0x10];
4086 u8 reserved_0[0x10];
4087
4088 u8 reserved_1[0x10];
4089 u8 op_mod[0x10];
4090
4091 u8 reserved_2[0x8];
4092 u8 tirn[0x18];
4093
4094 u8 reserved_3[0x20];
4095
d9eea403 4096 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b
SM		 4097
4098 u8 reserved_4[0x40];
4099
4100 struct mlx5_ifc_tirc_bits ctx;
4101};
4102
4103struct mlx5_ifc_modify_sq_out_bits {
4104 u8 status[0x8];
4105 u8 reserved_0[0x18];
4106
4107 u8 syndrome[0x20];
4108
4109 u8 reserved_1[0x40];
4110};
4111
4112struct mlx5_ifc_modify_sq_in_bits {
4113 u8 opcode[0x10];
4114 u8 reserved_0[0x10];
4115
4116 u8 reserved_1[0x10];
4117 u8 op_mod[0x10];
4118
4119 u8 sq_state[0x4];
4120 u8 reserved_2[0x4];
4121 u8 sqn[0x18];
4122
4123 u8 reserved_3[0x20];
4124
4125 u8 modify_bitmask[0x40];
4126
4127 u8 reserved_4[0x40];
4128
4129 struct mlx5_ifc_sqc_bits ctx;
4130};
4131
4132struct mlx5_ifc_modify_rqt_out_bits {
4133 u8 status[0x8];
4134 u8 reserved_0[0x18];
4135
4136 u8 syndrome[0x20];
4137
4138 u8 reserved_1[0x40];
4139};
4140
5c50368f
AS		 4141struct mlx5_ifc_rqt_bitmask_bits {
4142 u8 reserved[0x20];
4143
4144 u8 reserved1[0x1f];
4145 u8 rqn_list[0x1];
4146};
4147
e281682b
SM		 4148struct mlx5_ifc_modify_rqt_in_bits {
4149 u8 opcode[0x10];
4150 u8 reserved_0[0x10];
4151
4152 u8 reserved_1[0x10];
4153 u8 op_mod[0x10];
4154
4155 u8 reserved_2[0x8];
4156 u8 rqtn[0x18];
4157
4158 u8 reserved_3[0x20];
4159
5c50368f 4160 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b
SM		 4161
4162 u8 reserved_4[0x40];
4163
4164 struct mlx5_ifc_rqtc_bits ctx;
4165};
4166
4167struct mlx5_ifc_modify_rq_out_bits {
4168 u8 status[0x8];
4169 u8 reserved_0[0x18];
4170
4171 u8 syndrome[0x20];
4172
4173 u8 reserved_1[0x40];
4174};
4175
4176struct mlx5_ifc_modify_rq_in_bits {
4177 u8 opcode[0x10];
4178 u8 reserved_0[0x10];
4179
4180 u8 reserved_1[0x10];
4181 u8 op_mod[0x10];
4182
4183 u8 rq_state[0x4];
4184 u8 reserved_2[0x4];
4185 u8 rqn[0x18];
4186
4187 u8 reserved_3[0x20];
4188
4189 u8 modify_bitmask[0x40];
4190
4191 u8 reserved_4[0x40];
4192
4193 struct mlx5_ifc_rqc_bits ctx;
4194};
4195
4196struct mlx5_ifc_modify_rmp_out_bits {
4197 u8 status[0x8];
4198 u8 reserved_0[0x18];
4199
4200 u8 syndrome[0x20];
4201
4202 u8 reserved_1[0x40];
4203};
4204
01949d01
HA		 4205struct mlx5_ifc_rmp_bitmask_bits {
4206 u8 reserved[0x20];
4207
4208 u8 reserved1[0x1f];
4209 u8 lwm[0x1];
4210};
4211
e281682b
SM		 4212struct mlx5_ifc_modify_rmp_in_bits {
4213 u8 opcode[0x10];
4214 u8 reserved_0[0x10];
4215
4216 u8 reserved_1[0x10];
4217 u8 op_mod[0x10];
4218
4219 u8 rmp_state[0x4];
4220 u8 reserved_2[0x4];
4221 u8 rmpn[0x18];
4222
4223 u8 reserved_3[0x20];
4224
01949d01 4225 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b
SM		 4226
4227 u8 reserved_4[0x40];
4228
4229 struct mlx5_ifc_rmpc_bits ctx;
4230};
4231
4232struct mlx5_ifc_modify_nic_vport_context_out_bits {
4233 u8 status[0x8];
4234 u8 reserved_0[0x18];
4235
4236 u8 syndrome[0x20];
4237
4238 u8 reserved_1[0x40];
4239};
4240
4241struct mlx5_ifc_modify_nic_vport_field_select_bits {
4242 u8 reserved_0[0x1c];
4243 u8 permanent_address[0x1];
4244 u8 addresses_list[0x1];
4245 u8 roce_en[0x1];
4246 u8 reserved_1[0x1];
4247};
4248
4249struct mlx5_ifc_modify_nic_vport_context_in_bits {
4250 u8 opcode[0x10];
4251 u8 reserved_0[0x10];
4252
4253 u8 reserved_1[0x10];
4254 u8 op_mod[0x10];
4255
4256 u8 other_vport[0x1];
4257 u8 reserved_2[0xf];
4258 u8 vport_number[0x10];
4259
4260 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4261
4262 u8 reserved_3[0x780];
4263
4264 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4265};
4266
4267struct mlx5_ifc_modify_hca_vport_context_out_bits {
4268 u8 status[0x8];
4269 u8 reserved_0[0x18];
4270
4271 u8 syndrome[0x20];
4272
4273 u8 reserved_1[0x40];
4274};
4275
4276struct mlx5_ifc_modify_hca_vport_context_in_bits {
4277 u8 opcode[0x10];
4278 u8 reserved_0[0x10];
4279
4280 u8 reserved_1[0x10];
4281 u8 op_mod[0x10];
4282
4283 u8 other_vport[0x1];
707c4602
MD		 4284 u8 reserved_2[0xb];
4285 u8 port_num[0x4];
e281682b
SM		 4286 u8 vport_number[0x10];
4287
4288 u8 reserved_3[0x20];
4289
4290 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4291};
4292
4293struct mlx5_ifc_modify_cq_out_bits {
4294 u8 status[0x8];
4295 u8 reserved_0[0x18];
4296
4297 u8 syndrome[0x20];
4298
4299 u8 reserved_1[0x40];
4300};
4301
4302enum {
4303 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4304 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4305};
4306
4307struct mlx5_ifc_modify_cq_in_bits {
4308 u8 opcode[0x10];
4309 u8 reserved_0[0x10];
4310
4311 u8 reserved_1[0x10];
4312 u8 op_mod[0x10];
4313
4314 u8 reserved_2[0x8];
4315 u8 cqn[0x18];
4316
4317 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4318
4319 struct mlx5_ifc_cqc_bits cq_context;
4320
4321 u8 reserved_3[0x600];
4322
4323 u8 pas[0][0x40];
4324};
4325
4326struct mlx5_ifc_modify_cong_status_out_bits {
4327 u8 status[0x8];
4328 u8 reserved_0[0x18];
4329
4330 u8 syndrome[0x20];
4331
4332 u8 reserved_1[0x40];
4333};
4334
4335struct mlx5_ifc_modify_cong_status_in_bits {
4336 u8 opcode[0x10];
4337 u8 reserved_0[0x10];
4338
4339 u8 reserved_1[0x10];
4340 u8 op_mod[0x10];
4341
4342 u8 reserved_2[0x18];
4343 u8 priority[0x4];
4344 u8 cong_protocol[0x4];
4345
4346 u8 enable[0x1];
4347 u8 tag_enable[0x1];
4348 u8 reserved_3[0x1e];
4349};
4350
4351struct mlx5_ifc_modify_cong_params_out_bits {
4352 u8 status[0x8];
4353 u8 reserved_0[0x18];
4354
4355 u8 syndrome[0x20];
4356
4357 u8 reserved_1[0x40];
4358};
4359
4360struct mlx5_ifc_modify_cong_params_in_bits {
4361 u8 opcode[0x10];
4362 u8 reserved_0[0x10];
4363
4364 u8 reserved_1[0x10];
4365 u8 op_mod[0x10];
4366
4367 u8 reserved_2[0x1c];
4368 u8 cong_protocol[0x4];
4369
4370 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4371
4372 u8 reserved_3[0x80];
4373
4374 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4375};
4376
4377struct mlx5_ifc_manage_pages_out_bits {
4378 u8 status[0x8];
4379 u8 reserved_0[0x18];
4380
4381 u8 syndrome[0x20];
4382
4383 u8 output_num_entries[0x20];
4384
4385 u8 reserved_1[0x20];
4386
4387 u8 pas[0][0x40];
4388};
4389
4390enum {
4391 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4392 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4393 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4394};
4395
4396struct mlx5_ifc_manage_pages_in_bits {
4397 u8 opcode[0x10];
4398 u8 reserved_0[0x10];
4399
4400 u8 reserved_1[0x10];
4401 u8 op_mod[0x10];
4402
4403 u8 reserved_2[0x10];
4404 u8 function_id[0x10];
4405
4406 u8 input_num_entries[0x20];
4407
4408 u8 pas[0][0x40];
4409};
4410
4411struct mlx5_ifc_mad_ifc_out_bits {
4412 u8 status[0x8];
4413 u8 reserved_0[0x18];
4414
4415 u8 syndrome[0x20];
4416
4417 u8 reserved_1[0x40];
4418
4419 u8 response_mad_packet[256][0x8];
4420};
4421
4422struct mlx5_ifc_mad_ifc_in_bits {
4423 u8 opcode[0x10];
4424 u8 reserved_0[0x10];
4425
4426 u8 reserved_1[0x10];
4427 u8 op_mod[0x10];
4428
4429 u8 remote_lid[0x10];
4430 u8 reserved_2[0x8];
4431 u8 port[0x8];
4432
4433 u8 reserved_3[0x20];
4434
4435 u8 mad[256][0x8];
4436};
4437
4438struct mlx5_ifc_init_hca_out_bits {
4439 u8 status[0x8];
4440 u8 reserved_0[0x18];
4441
4442 u8 syndrome[0x20];
4443
4444 u8 reserved_1[0x40];
4445};
4446
4447struct mlx5_ifc_init_hca_in_bits {
4448 u8 opcode[0x10];
4449 u8 reserved_0[0x10];
4450
4451 u8 reserved_1[0x10];
4452 u8 op_mod[0x10];
4453
4454 u8 reserved_2[0x40];
4455};
4456
4457struct mlx5_ifc_init2rtr_qp_out_bits {
4458 u8 status[0x8];
4459 u8 reserved_0[0x18];
4460
4461 u8 syndrome[0x20];
4462
4463 u8 reserved_1[0x40];
4464};
4465
4466struct mlx5_ifc_init2rtr_qp_in_bits {
4467 u8 opcode[0x10];
4468 u8 reserved_0[0x10];
4469
4470 u8 reserved_1[0x10];
4471 u8 op_mod[0x10];
4472
4473 u8 reserved_2[0x8];
4474 u8 qpn[0x18];
4475
4476 u8 reserved_3[0x20];
4477
4478 u8 opt_param_mask[0x20];
4479
4480 u8 reserved_4[0x20];
4481
4482 struct mlx5_ifc_qpc_bits qpc;
4483
4484 u8 reserved_5[0x80];
4485};
4486
4487struct mlx5_ifc_init2init_qp_out_bits {
4488 u8 status[0x8];
4489 u8 reserved_0[0x18];
4490
4491 u8 syndrome[0x20];
4492
4493 u8 reserved_1[0x40];
4494};
4495
4496struct mlx5_ifc_init2init_qp_in_bits {
4497 u8 opcode[0x10];
4498 u8 reserved_0[0x10];
4499
4500 u8 reserved_1[0x10];
4501 u8 op_mod[0x10];
4502
4503 u8 reserved_2[0x8];
4504 u8 qpn[0x18];
4505
4506 u8 reserved_3[0x20];
4507
4508 u8 opt_param_mask[0x20];
4509
4510 u8 reserved_4[0x20];
4511
4512 struct mlx5_ifc_qpc_bits qpc;
4513
4514 u8 reserved_5[0x80];
4515};
4516
4517struct mlx5_ifc_get_dropped_packet_log_out_bits {
4518 u8 status[0x8];
4519 u8 reserved_0[0x18];
4520
4521 u8 syndrome[0x20];
4522
4523 u8 reserved_1[0x40];
4524
4525 u8 packet_headers_log[128][0x8];
4526
4527 u8 packet_syndrome[64][0x8];
4528};
4529
4530struct mlx5_ifc_get_dropped_packet_log_in_bits {
4531 u8 opcode[0x10];
4532 u8 reserved_0[0x10];
4533
4534 u8 reserved_1[0x10];
4535 u8 op_mod[0x10];
4536
4537 u8 reserved_2[0x40];
4538};
4539
4540struct mlx5_ifc_gen_eqe_in_bits {
4541 u8 opcode[0x10];
4542 u8 reserved_0[0x10];
4543
4544 u8 reserved_1[0x10];
4545 u8 op_mod[0x10];
4546
4547 u8 reserved_2[0x18];
4548 u8 eq_number[0x8];
4549
4550 u8 reserved_3[0x20];
4551
4552 u8 eqe[64][0x8];
4553};
4554
4555struct mlx5_ifc_gen_eq_out_bits {
4556 u8 status[0x8];
4557 u8 reserved_0[0x18];
4558
4559 u8 syndrome[0x20];
4560
4561 u8 reserved_1[0x40];
4562};
4563
4564struct mlx5_ifc_enable_hca_out_bits {
4565 u8 status[0x8];
4566 u8 reserved_0[0x18];
4567
4568 u8 syndrome[0x20];
4569
4570 u8 reserved_1[0x20];
4571};
4572
4573struct mlx5_ifc_enable_hca_in_bits {
4574 u8 opcode[0x10];
4575 u8 reserved_0[0x10];
4576
4577 u8 reserved_1[0x10];
4578 u8 op_mod[0x10];
4579
4580 u8 reserved_2[0x10];
4581 u8 function_id[0x10];
4582
4583 u8 reserved_3[0x20];
4584};
4585
4586struct mlx5_ifc_drain_dct_out_bits {
4587 u8 status[0x8];
4588 u8 reserved_0[0x18];
4589
4590 u8 syndrome[0x20];
4591
4592 u8 reserved_1[0x40];
4593};
4594
4595struct mlx5_ifc_drain_dct_in_bits {
4596 u8 opcode[0x10];
4597 u8 reserved_0[0x10];
4598
4599 u8 reserved_1[0x10];
4600 u8 op_mod[0x10];
4601
4602 u8 reserved_2[0x8];
4603 u8 dctn[0x18];
4604
4605 u8 reserved_3[0x20];
4606};
4607
4608struct mlx5_ifc_disable_hca_out_bits {
4609 u8 status[0x8];
4610 u8 reserved_0[0x18];
4611
4612 u8 syndrome[0x20];
4613
4614 u8 reserved_1[0x20];
4615};
4616
4617struct mlx5_ifc_disable_hca_in_bits {
4618 u8 opcode[0x10];
4619 u8 reserved_0[0x10];
4620
4621 u8 reserved_1[0x10];
4622 u8 op_mod[0x10];
4623
4624 u8 reserved_2[0x10];
4625 u8 function_id[0x10];
4626
4627 u8 reserved_3[0x20];
4628};
4629
4630struct mlx5_ifc_detach_from_mcg_out_bits {
4631 u8 status[0x8];
4632 u8 reserved_0[0x18];
4633
4634 u8 syndrome[0x20];
4635
4636 u8 reserved_1[0x40];
4637};
4638
4639struct mlx5_ifc_detach_from_mcg_in_bits {
4640 u8 opcode[0x10];
4641 u8 reserved_0[0x10];
4642
4643 u8 reserved_1[0x10];
4644 u8 op_mod[0x10];
4645
4646 u8 reserved_2[0x8];
4647 u8 qpn[0x18];
4648
4649 u8 reserved_3[0x20];
4650
4651 u8 multicast_gid[16][0x8];
4652};
4653
4654struct mlx5_ifc_destroy_xrc_srq_out_bits {
4655 u8 status[0x8];
4656 u8 reserved_0[0x18];
4657
4658 u8 syndrome[0x20];
4659
4660 u8 reserved_1[0x40];
4661};
4662
4663struct mlx5_ifc_destroy_xrc_srq_in_bits {
4664 u8 opcode[0x10];
4665 u8 reserved_0[0x10];
4666
4667 u8 reserved_1[0x10];
4668 u8 op_mod[0x10];
4669
4670 u8 reserved_2[0x8];
4671 u8 xrc_srqn[0x18];
4672
4673 u8 reserved_3[0x20];
4674};
4675
4676struct mlx5_ifc_destroy_tis_out_bits {
4677 u8 status[0x8];
4678 u8 reserved_0[0x18];
4679
4680 u8 syndrome[0x20];
4681
4682 u8 reserved_1[0x40];
4683};
4684
4685struct mlx5_ifc_destroy_tis_in_bits {
4686 u8 opcode[0x10];
4687 u8 reserved_0[0x10];
4688
4689 u8 reserved_1[0x10];
4690 u8 op_mod[0x10];
4691
4692 u8 reserved_2[0x8];
4693 u8 tisn[0x18];
4694
4695 u8 reserved_3[0x20];
4696};
4697
4698struct mlx5_ifc_destroy_tir_out_bits {
4699 u8 status[0x8];
4700 u8 reserved_0[0x18];
4701
4702 u8 syndrome[0x20];
4703
4704 u8 reserved_1[0x40];
4705};
4706
4707struct mlx5_ifc_destroy_tir_in_bits {
4708 u8 opcode[0x10];
4709 u8 reserved_0[0x10];
4710
4711 u8 reserved_1[0x10];
4712 u8 op_mod[0x10];
4713
4714 u8 reserved_2[0x8];
4715 u8 tirn[0x18];
4716
4717 u8 reserved_3[0x20];
4718};
4719
4720struct mlx5_ifc_destroy_srq_out_bits {
4721 u8 status[0x8];
4722 u8 reserved_0[0x18];
4723
4724 u8 syndrome[0x20];
4725
4726 u8 reserved_1[0x40];
4727};
4728
4729struct mlx5_ifc_destroy_srq_in_bits {
4730 u8 opcode[0x10];
4731 u8 reserved_0[0x10];
4732
4733 u8 reserved_1[0x10];
4734 u8 op_mod[0x10];
4735
4736 u8 reserved_2[0x8];
4737 u8 srqn[0x18];
4738
4739 u8 reserved_3[0x20];
4740};
4741
4742struct mlx5_ifc_destroy_sq_out_bits {
4743 u8 status[0x8];
4744 u8 reserved_0[0x18];
4745
4746 u8 syndrome[0x20];
4747
4748 u8 reserved_1[0x40];
4749};
4750
4751struct mlx5_ifc_destroy_sq_in_bits {
4752 u8 opcode[0x10];
4753 u8 reserved_0[0x10];
4754
4755 u8 reserved_1[0x10];
4756 u8 op_mod[0x10];
4757
4758 u8 reserved_2[0x8];
4759 u8 sqn[0x18];
4760
4761 u8 reserved_3[0x20];
4762};
4763
4764struct mlx5_ifc_destroy_rqt_out_bits {
4765 u8 status[0x8];
4766 u8 reserved_0[0x18];
4767
4768 u8 syndrome[0x20];
4769
4770 u8 reserved_1[0x40];
4771};
4772
4773struct mlx5_ifc_destroy_rqt_in_bits {
4774 u8 opcode[0x10];
4775 u8 reserved_0[0x10];
4776
4777 u8 reserved_1[0x10];
4778 u8 op_mod[0x10];
4779
4780 u8 reserved_2[0x8];
4781 u8 rqtn[0x18];
4782
4783 u8 reserved_3[0x20];
4784};
4785
4786struct mlx5_ifc_destroy_rq_out_bits {
4787 u8 status[0x8];
4788 u8 reserved_0[0x18];
4789
4790 u8 syndrome[0x20];
4791
4792 u8 reserved_1[0x40];
4793};
4794
4795struct mlx5_ifc_destroy_rq_in_bits {
4796 u8 opcode[0x10];
4797 u8 reserved_0[0x10];
4798
4799 u8 reserved_1[0x10];
4800 u8 op_mod[0x10];
4801
4802 u8 reserved_2[0x8];
4803 u8 rqn[0x18];
4804
4805 u8 reserved_3[0x20];
4806};
4807
4808struct mlx5_ifc_destroy_rmp_out_bits {
4809 u8 status[0x8];
4810 u8 reserved_0[0x18];
4811
4812 u8 syndrome[0x20];
4813
4814 u8 reserved_1[0x40];
4815};
4816
4817struct mlx5_ifc_destroy_rmp_in_bits {
4818 u8 opcode[0x10];
4819 u8 reserved_0[0x10];
4820
4821 u8 reserved_1[0x10];
4822 u8 op_mod[0x10];
4823
4824 u8 reserved_2[0x8];
4825 u8 rmpn[0x18];
4826
4827 u8 reserved_3[0x20];
4828};
4829
4830struct mlx5_ifc_destroy_qp_out_bits {
4831 u8 status[0x8];
4832 u8 reserved_0[0x18];
4833
4834 u8 syndrome[0x20];
4835
4836 u8 reserved_1[0x40];
4837};
4838
4839struct mlx5_ifc_destroy_qp_in_bits {
4840 u8 opcode[0x10];
4841 u8 reserved_0[0x10];
4842
4843 u8 reserved_1[0x10];
4844 u8 op_mod[0x10];
4845
4846 u8 reserved_2[0x8];
4847 u8 qpn[0x18];
4848
4849 u8 reserved_3[0x20];
4850};
4851
4852struct mlx5_ifc_destroy_psv_out_bits {
4853 u8 status[0x8];
4854 u8 reserved_0[0x18];
4855
4856 u8 syndrome[0x20];
4857
4858 u8 reserved_1[0x40];
4859};
4860
4861struct mlx5_ifc_destroy_psv_in_bits {
4862 u8 opcode[0x10];
4863 u8 reserved_0[0x10];
4864
4865 u8 reserved_1[0x10];
4866 u8 op_mod[0x10];
4867
4868 u8 reserved_2[0x8];
4869 u8 psvn[0x18];
4870
4871 u8 reserved_3[0x20];
4872};
4873
4874struct mlx5_ifc_destroy_mkey_out_bits {
4875 u8 status[0x8];
4876 u8 reserved_0[0x18];
4877
4878 u8 syndrome[0x20];
4879
4880 u8 reserved_1[0x40];
4881};
4882
4883struct mlx5_ifc_destroy_mkey_in_bits {
4884 u8 opcode[0x10];
4885 u8 reserved_0[0x10];
4886
4887 u8 reserved_1[0x10];
4888 u8 op_mod[0x10];
4889
4890 u8 reserved_2[0x8];
4891 u8 mkey_index[0x18];
4892
4893 u8 reserved_3[0x20];
4894};
4895
4896struct mlx5_ifc_destroy_flow_table_out_bits {
4897 u8 status[0x8];
4898 u8 reserved_0[0x18];
4899
4900 u8 syndrome[0x20];
4901
4902 u8 reserved_1[0x40];
4903};
4904
4905struct mlx5_ifc_destroy_flow_table_in_bits {
4906 u8 opcode[0x10];
4907 u8 reserved_0[0x10];
4908
4909 u8 reserved_1[0x10];
4910 u8 op_mod[0x10];
4911
4912 u8 reserved_2[0x40];
4913
4914 u8 table_type[0x8];
4915 u8 reserved_3[0x18];
4916
4917 u8 reserved_4[0x8];
4918 u8 table_id[0x18];
4919
4920 u8 reserved_5[0x140];
4921};
4922
4923struct mlx5_ifc_destroy_flow_group_out_bits {
4924 u8 status[0x8];
4925 u8 reserved_0[0x18];
4926
4927 u8 syndrome[0x20];
4928
4929 u8 reserved_1[0x40];
4930};
4931
4932struct mlx5_ifc_destroy_flow_group_in_bits {
4933 u8 opcode[0x10];
4934 u8 reserved_0[0x10];
4935
4936 u8 reserved_1[0x10];
4937 u8 op_mod[0x10];
4938
4939 u8 reserved_2[0x40];
4940
4941 u8 table_type[0x8];
4942 u8 reserved_3[0x18];
4943
4944 u8 reserved_4[0x8];
4945 u8 table_id[0x18];
4946
4947 u8 group_id[0x20];
4948
4949 u8 reserved_5[0x120];
4950};
4951
4952struct mlx5_ifc_destroy_eq_out_bits {
4953 u8 status[0x8];
4954 u8 reserved_0[0x18];
4955
4956 u8 syndrome[0x20];
4957
4958 u8 reserved_1[0x40];
4959};
4960
4961struct mlx5_ifc_destroy_eq_in_bits {
4962 u8 opcode[0x10];
4963 u8 reserved_0[0x10];
4964
4965 u8 reserved_1[0x10];
4966 u8 op_mod[0x10];
4967
4968 u8 reserved_2[0x18];
4969 u8 eq_number[0x8];
4970
4971 u8 reserved_3[0x20];
4972};
4973
4974struct mlx5_ifc_destroy_dct_out_bits {
4975 u8 status[0x8];
4976 u8 reserved_0[0x18];
4977
4978 u8 syndrome[0x20];
4979
4980 u8 reserved_1[0x40];
4981};
4982
4983struct mlx5_ifc_destroy_dct_in_bits {
4984 u8 opcode[0x10];
4985 u8 reserved_0[0x10];
4986
4987 u8 reserved_1[0x10];
4988 u8 op_mod[0x10];
4989
4990 u8 reserved_2[0x8];
4991 u8 dctn[0x18];
4992
4993 u8 reserved_3[0x20];
4994};
4995
4996struct mlx5_ifc_destroy_cq_out_bits {
4997 u8 status[0x8];
4998 u8 reserved_0[0x18];
4999
5000 u8 syndrome[0x20];
5001
5002 u8 reserved_1[0x40];
5003};
5004
5005struct mlx5_ifc_destroy_cq_in_bits {
5006 u8 opcode[0x10];
5007 u8 reserved_0[0x10];
5008
5009 u8 reserved_1[0x10];
5010 u8 op_mod[0x10];
5011
5012 u8 reserved_2[0x8];
5013 u8 cqn[0x18];
5014
5015 u8 reserved_3[0x20];
5016};
5017
5018struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5019 u8 status[0x8];
5020 u8 reserved_0[0x18];
5021
5022 u8 syndrome[0x20];
5023
5024 u8 reserved_1[0x40];
5025};
5026
5027struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5028 u8 opcode[0x10];
5029 u8 reserved_0[0x10];
5030
5031 u8 reserved_1[0x10];
5032 u8 op_mod[0x10];
5033
5034 u8 reserved_2[0x20];
5035
5036 u8 reserved_3[0x10];
5037 u8 vxlan_udp_port[0x10];
5038};
5039
5040struct mlx5_ifc_delete_l2_table_entry_out_bits {
5041 u8 status[0x8];
5042 u8 reserved_0[0x18];
5043
5044 u8 syndrome[0x20];
5045
5046 u8 reserved_1[0x40];
5047};
5048
5049struct mlx5_ifc_delete_l2_table_entry_in_bits {
5050 u8 opcode[0x10];
5051 u8 reserved_0[0x10];
5052
5053 u8 reserved_1[0x10];
5054 u8 op_mod[0x10];
5055
5056 u8 reserved_2[0x60];
5057
5058 u8 reserved_3[0x8];
5059 u8 table_index[0x18];
5060
5061 u8 reserved_4[0x140];
5062};
5063
5064struct mlx5_ifc_delete_fte_out_bits {
5065 u8 status[0x8];
5066 u8 reserved_0[0x18];
5067
5068 u8 syndrome[0x20];
5069
5070 u8 reserved_1[0x40];
5071};
5072
5073struct mlx5_ifc_delete_fte_in_bits {
5074 u8 opcode[0x10];
5075 u8 reserved_0[0x10];
5076
5077 u8 reserved_1[0x10];
5078 u8 op_mod[0x10];
5079
5080 u8 reserved_2[0x40];
5081
5082 u8 table_type[0x8];
5083 u8 reserved_3[0x18];
5084
5085 u8 reserved_4[0x8];
5086 u8 table_id[0x18];
5087
5088 u8 reserved_5[0x40];
5089
5090 u8 flow_index[0x20];
5091
5092 u8 reserved_6[0xe0];
5093};
5094
5095struct mlx5_ifc_dealloc_xrcd_out_bits {
5096 u8 status[0x8];
5097 u8 reserved_0[0x18];
5098
5099 u8 syndrome[0x20];
5100
5101 u8 reserved_1[0x40];
5102};
5103
5104struct mlx5_ifc_dealloc_xrcd_in_bits {
5105 u8 opcode[0x10];
5106 u8 reserved_0[0x10];
5107
5108 u8 reserved_1[0x10];
5109 u8 op_mod[0x10];
5110
5111 u8 reserved_2[0x8];
5112 u8 xrcd[0x18];
5113
5114 u8 reserved_3[0x20];
5115};
5116
5117struct mlx5_ifc_dealloc_uar_out_bits {
5118 u8 status[0x8];
5119 u8 reserved_0[0x18];
5120
5121 u8 syndrome[0x20];
5122
5123 u8 reserved_1[0x40];
5124};
5125
5126struct mlx5_ifc_dealloc_uar_in_bits {
5127 u8 opcode[0x10];
5128 u8 reserved_0[0x10];
5129
5130 u8 reserved_1[0x10];
5131 u8 op_mod[0x10];
5132
5133 u8 reserved_2[0x8];
5134 u8 uar[0x18];
5135
5136 u8 reserved_3[0x20];
5137};
5138
5139struct mlx5_ifc_dealloc_transport_domain_out_bits {
5140 u8 status[0x8];
5141 u8 reserved_0[0x18];
5142
5143 u8 syndrome[0x20];
5144
5145 u8 reserved_1[0x40];
5146};
5147
5148struct mlx5_ifc_dealloc_transport_domain_in_bits {
5149 u8 opcode[0x10];
5150 u8 reserved_0[0x10];
5151
5152 u8 reserved_1[0x10];
5153 u8 op_mod[0x10];
5154
5155 u8 reserved_2[0x8];
5156 u8 transport_domain[0x18];
5157
5158 u8 reserved_3[0x20];
5159};
5160
5161struct mlx5_ifc_dealloc_q_counter_out_bits {
5162 u8 status[0x8];
5163 u8 reserved_0[0x18];
5164
5165 u8 syndrome[0x20];
5166
5167 u8 reserved_1[0x40];
5168};
5169
5170struct mlx5_ifc_dealloc_q_counter_in_bits {
5171 u8 opcode[0x10];
5172 u8 reserved_0[0x10];
5173
5174 u8 reserved_1[0x10];
5175 u8 op_mod[0x10];
5176
5177 u8 reserved_2[0x18];
5178 u8 counter_set_id[0x8];
5179
5180 u8 reserved_3[0x20];
5181};
5182
5183struct mlx5_ifc_dealloc_pd_out_bits {
5184 u8 status[0x8];
5185 u8 reserved_0[0x18];
5186
5187 u8 syndrome[0x20];
5188
5189 u8 reserved_1[0x40];
5190};
5191
5192struct mlx5_ifc_dealloc_pd_in_bits {
5193 u8 opcode[0x10];
5194 u8 reserved_0[0x10];
5195
5196 u8 reserved_1[0x10];
5197 u8 op_mod[0x10];
5198
5199 u8 reserved_2[0x8];
5200 u8 pd[0x18];
5201
5202 u8 reserved_3[0x20];
5203};
5204
5205struct mlx5_ifc_create_xrc_srq_out_bits {
5206 u8 status[0x8];
5207 u8 reserved_0[0x18];
5208
5209 u8 syndrome[0x20];
5210
5211 u8 reserved_1[0x8];
5212 u8 xrc_srqn[0x18];
5213
5214 u8 reserved_2[0x20];
5215};
5216
5217struct mlx5_ifc_create_xrc_srq_in_bits {
5218 u8 opcode[0x10];
5219 u8 reserved_0[0x10];
5220
5221 u8 reserved_1[0x10];
5222 u8 op_mod[0x10];
5223
5224 u8 reserved_2[0x40];
5225
5226 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5227
5228 u8 reserved_3[0x600];
5229
5230 u8 pas[0][0x40];
5231};
5232
5233struct mlx5_ifc_create_tis_out_bits {
5234 u8 status[0x8];
5235 u8 reserved_0[0x18];
5236
5237 u8 syndrome[0x20];
5238
5239 u8 reserved_1[0x8];
5240 u8 tisn[0x18];
5241
5242 u8 reserved_2[0x20];
5243};
5244
5245struct mlx5_ifc_create_tis_in_bits {
5246 u8 opcode[0x10];
5247 u8 reserved_0[0x10];
5248
5249 u8 reserved_1[0x10];
5250 u8 op_mod[0x10];
5251
5252 u8 reserved_2[0xc0];
5253
5254 struct mlx5_ifc_tisc_bits ctx;
5255};
5256
5257struct mlx5_ifc_create_tir_out_bits {
5258 u8 status[0x8];
5259 u8 reserved_0[0x18];
5260
5261 u8 syndrome[0x20];
5262
5263 u8 reserved_1[0x8];
5264 u8 tirn[0x18];
5265
5266 u8 reserved_2[0x20];
5267};
5268
5269struct mlx5_ifc_create_tir_in_bits {
5270 u8 opcode[0x10];
5271 u8 reserved_0[0x10];
5272
5273 u8 reserved_1[0x10];
5274 u8 op_mod[0x10];
5275
5276 u8 reserved_2[0xc0];
5277
5278 struct mlx5_ifc_tirc_bits ctx;
5279};
5280
5281struct mlx5_ifc_create_srq_out_bits {
5282 u8 status[0x8];
5283 u8 reserved_0[0x18];
5284
5285 u8 syndrome[0x20];
5286
5287 u8 reserved_1[0x8];
5288 u8 srqn[0x18];
5289
5290 u8 reserved_2[0x20];
5291};
5292
5293struct mlx5_ifc_create_srq_in_bits {
5294 u8 opcode[0x10];
5295 u8 reserved_0[0x10];
5296
5297 u8 reserved_1[0x10];
5298 u8 op_mod[0x10];
5299
5300 u8 reserved_2[0x40];
5301
5302 struct mlx5_ifc_srqc_bits srq_context_entry;
5303
5304 u8 reserved_3[0x600];
5305
5306 u8 pas[0][0x40];
5307};
5308
5309struct mlx5_ifc_create_sq_out_bits {
5310 u8 status[0x8];
5311 u8 reserved_0[0x18];
5312
5313 u8 syndrome[0x20];
5314
5315 u8 reserved_1[0x8];
5316 u8 sqn[0x18];
5317
5318 u8 reserved_2[0x20];
5319};
5320
5321struct mlx5_ifc_create_sq_in_bits {
5322 u8 opcode[0x10];
5323 u8 reserved_0[0x10];
5324
5325 u8 reserved_1[0x10];
5326 u8 op_mod[0x10];
5327
5328 u8 reserved_2[0xc0];
5329
5330 struct mlx5_ifc_sqc_bits ctx;
5331};
5332
5333struct mlx5_ifc_create_rqt_out_bits {
5334 u8 status[0x8];
5335 u8 reserved_0[0x18];
5336
5337 u8 syndrome[0x20];
5338
5339 u8 reserved_1[0x8];
5340 u8 rqtn[0x18];
5341
5342 u8 reserved_2[0x20];
5343};
5344
5345struct mlx5_ifc_create_rqt_in_bits {
5346 u8 opcode[0x10];
5347 u8 reserved_0[0x10];
5348
5349 u8 reserved_1[0x10];
5350 u8 op_mod[0x10];
5351
5352 u8 reserved_2[0xc0];
5353
5354 struct mlx5_ifc_rqtc_bits rqt_context;
5355};
5356
5357struct mlx5_ifc_create_rq_out_bits {
5358 u8 status[0x8];
5359 u8 reserved_0[0x18];
5360
5361 u8 syndrome[0x20];
5362
5363 u8 reserved_1[0x8];
5364 u8 rqn[0x18];
5365
5366 u8 reserved_2[0x20];
5367};
5368
5369struct mlx5_ifc_create_rq_in_bits {
5370 u8 opcode[0x10];
5371 u8 reserved_0[0x10];
5372
5373 u8 reserved_1[0x10];
5374 u8 op_mod[0x10];
5375
5376 u8 reserved_2[0xc0];
5377
5378 struct mlx5_ifc_rqc_bits ctx;
5379};
5380
5381struct mlx5_ifc_create_rmp_out_bits {
5382 u8 status[0x8];
5383 u8 reserved_0[0x18];
5384
5385 u8 syndrome[0x20];
5386
5387 u8 reserved_1[0x8];
5388 u8 rmpn[0x18];
5389
5390 u8 reserved_2[0x20];
5391};
5392
5393struct mlx5_ifc_create_rmp_in_bits {
5394 u8 opcode[0x10];
5395 u8 reserved_0[0x10];
5396
5397 u8 reserved_1[0x10];
5398 u8 op_mod[0x10];
5399
5400 u8 reserved_2[0xc0];
5401
5402 struct mlx5_ifc_rmpc_bits ctx;
5403};
5404
5405struct mlx5_ifc_create_qp_out_bits {
5406 u8 status[0x8];
5407 u8 reserved_0[0x18];
5408
5409 u8 syndrome[0x20];
5410
5411 u8 reserved_1[0x8];
5412 u8 qpn[0x18];
5413
5414 u8 reserved_2[0x20];
5415};
5416
5417struct mlx5_ifc_create_qp_in_bits {
5418 u8 opcode[0x10];
5419 u8 reserved_0[0x10];
5420
5421 u8 reserved_1[0x10];
5422 u8 op_mod[0x10];
5423
5424 u8 reserved_2[0x40];
5425
5426 u8 opt_param_mask[0x20];
5427
5428 u8 reserved_3[0x20];
5429
5430 struct mlx5_ifc_qpc_bits qpc;
5431
5432 u8 reserved_4[0x80];
5433
5434 u8 pas[0][0x40];
5435};
5436
5437struct mlx5_ifc_create_psv_out_bits {
5438 u8 status[0x8];
5439 u8 reserved_0[0x18];
5440
5441 u8 syndrome[0x20];
5442
5443 u8 reserved_1[0x40];
5444
5445 u8 reserved_2[0x8];
5446 u8 psv0_index[0x18];
5447
5448 u8 reserved_3[0x8];
5449 u8 psv1_index[0x18];
5450
5451 u8 reserved_4[0x8];
5452 u8 psv2_index[0x18];
5453
5454 u8 reserved_5[0x8];
5455 u8 psv3_index[0x18];
5456};
5457
5458struct mlx5_ifc_create_psv_in_bits {
5459 u8 opcode[0x10];
5460 u8 reserved_0[0x10];
5461
5462 u8 reserved_1[0x10];
5463 u8 op_mod[0x10];
5464
5465 u8 num_psv[0x4];
5466 u8 reserved_2[0x4];
5467 u8 pd[0x18];
5468
5469 u8 reserved_3[0x20];
5470};
5471
5472struct mlx5_ifc_create_mkey_out_bits {
5473 u8 status[0x8];
5474 u8 reserved_0[0x18];
5475
5476 u8 syndrome[0x20];
5477
5478 u8 reserved_1[0x8];
5479 u8 mkey_index[0x18];
5480
5481 u8 reserved_2[0x20];
5482};
5483
5484struct mlx5_ifc_create_mkey_in_bits {
5485 u8 opcode[0x10];
5486 u8 reserved_0[0x10];
5487
5488 u8 reserved_1[0x10];
5489 u8 op_mod[0x10];
5490
5491 u8 reserved_2[0x20];
5492
5493 u8 pg_access[0x1];
5494 u8 reserved_3[0x1f];
5495
5496 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5497
5498 u8 reserved_4[0x80];
5499
5500 u8 translations_octword_actual_size[0x20];
5501
5502 u8 reserved_5[0x560];
5503
5504 u8 klm_pas_mtt[0][0x20];
5505};
5506
5507struct mlx5_ifc_create_flow_table_out_bits {
5508 u8 status[0x8];
5509 u8 reserved_0[0x18];
5510
5511 u8 syndrome[0x20];
5512
5513 u8 reserved_1[0x8];
5514 u8 table_id[0x18];
5515
5516 u8 reserved_2[0x20];
5517};
5518
5519struct mlx5_ifc_create_flow_table_in_bits {
5520 u8 opcode[0x10];
5521 u8 reserved_0[0x10];
5522
5523 u8 reserved_1[0x10];
5524 u8 op_mod[0x10];
5525
5526 u8 reserved_2[0x40];
5527
5528 u8 table_type[0x8];
5529 u8 reserved_3[0x18];
5530
5531 u8 reserved_4[0x20];
5532
5533 u8 reserved_5[0x8];
5534 u8 level[0x8];
5535 u8 reserved_6[0x8];
5536 u8 log_size[0x8];
5537
5538 u8 reserved_7[0x120];
5539};
5540
5541struct mlx5_ifc_create_flow_group_out_bits {
5542 u8 status[0x8];
5543 u8 reserved_0[0x18];
5544
5545 u8 syndrome[0x20];
5546
5547 u8 reserved_1[0x8];
5548 u8 group_id[0x18];
5549
5550 u8 reserved_2[0x20];
5551};
5552
5553enum {
5554 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5555 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5556 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5557};
5558
5559struct mlx5_ifc_create_flow_group_in_bits {
5560 u8 opcode[0x10];
5561 u8 reserved_0[0x10];
5562
5563 u8 reserved_1[0x10];
5564 u8 op_mod[0x10];
5565
5566 u8 reserved_2[0x40];
5567
5568 u8 table_type[0x8];
5569 u8 reserved_3[0x18];
5570
5571 u8 reserved_4[0x8];
5572 u8 table_id[0x18];
5573
5574 u8 reserved_5[0x20];
5575
5576 u8 start_flow_index[0x20];
5577
5578 u8 reserved_6[0x20];
5579
5580 u8 end_flow_index[0x20];
5581
5582 u8 reserved_7[0xa0];
5583
5584 u8 reserved_8[0x18];
5585 u8 match_criteria_enable[0x8];
5586
5587 struct mlx5_ifc_fte_match_param_bits match_criteria;
5588
5589 u8 reserved_9[0xe00];
5590};
5591
5592struct mlx5_ifc_create_eq_out_bits {
5593 u8 status[0x8];
5594 u8 reserved_0[0x18];
5595
5596 u8 syndrome[0x20];
5597
5598 u8 reserved_1[0x18];
5599 u8 eq_number[0x8];
5600
5601 u8 reserved_2[0x20];
5602};
5603
5604struct mlx5_ifc_create_eq_in_bits {
5605 u8 opcode[0x10];
5606 u8 reserved_0[0x10];
5607
5608 u8 reserved_1[0x10];
5609 u8 op_mod[0x10];
5610
5611 u8 reserved_2[0x40];
5612
5613 struct mlx5_ifc_eqc_bits eq_context_entry;
5614
5615 u8 reserved_3[0x40];
5616
5617 u8 event_bitmask[0x40];
5618
5619 u8 reserved_4[0x580];
5620
5621 u8 pas[0][0x40];
5622};
5623
5624struct mlx5_ifc_create_dct_out_bits {
5625 u8 status[0x8];
5626 u8 reserved_0[0x18];
5627
5628 u8 syndrome[0x20];
5629
5630 u8 reserved_1[0x8];
5631 u8 dctn[0x18];
5632
5633 u8 reserved_2[0x20];
5634};
5635
5636struct mlx5_ifc_create_dct_in_bits {
5637 u8 opcode[0x10];
5638 u8 reserved_0[0x10];
5639
5640 u8 reserved_1[0x10];
5641 u8 op_mod[0x10];
5642
5643 u8 reserved_2[0x40];
5644
5645 struct mlx5_ifc_dctc_bits dct_context_entry;
5646
5647 u8 reserved_3[0x180];
5648};
5649
5650struct mlx5_ifc_create_cq_out_bits {
5651 u8 status[0x8];
5652 u8 reserved_0[0x18];
5653
5654 u8 syndrome[0x20];
5655
5656 u8 reserved_1[0x8];
5657 u8 cqn[0x18];
5658
5659 u8 reserved_2[0x20];
5660};
5661
5662struct mlx5_ifc_create_cq_in_bits {
5663 u8 opcode[0x10];
5664 u8 reserved_0[0x10];
5665
5666 u8 reserved_1[0x10];
5667 u8 op_mod[0x10];
5668
5669 u8 reserved_2[0x40];
5670
5671 struct mlx5_ifc_cqc_bits cq_context;
5672
5673 u8 reserved_3[0x600];
5674
5675 u8 pas[0][0x40];
5676};
5677
5678struct mlx5_ifc_config_int_moderation_out_bits {
5679 u8 status[0x8];
5680 u8 reserved_0[0x18];
5681
5682 u8 syndrome[0x20];
5683
5684 u8 reserved_1[0x4];
5685 u8 min_delay[0xc];
5686 u8 int_vector[0x10];
5687
5688 u8 reserved_2[0x20];
5689};
5690
5691enum {
5692 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
5693 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
5694};
5695
5696struct mlx5_ifc_config_int_moderation_in_bits {
5697 u8 opcode[0x10];
5698 u8 reserved_0[0x10];
5699
5700 u8 reserved_1[0x10];
5701 u8 op_mod[0x10];
5702
5703 u8 reserved_2[0x4];
5704 u8 min_delay[0xc];
5705 u8 int_vector[0x10];
5706
5707 u8 reserved_3[0x20];
5708};
5709
5710struct mlx5_ifc_attach_to_mcg_out_bits {
5711 u8 status[0x8];
5712 u8 reserved_0[0x18];
5713
5714 u8 syndrome[0x20];
5715
5716 u8 reserved_1[0x40];
5717};
5718
5719struct mlx5_ifc_attach_to_mcg_in_bits {
5720 u8 opcode[0x10];
5721 u8 reserved_0[0x10];
5722
5723 u8 reserved_1[0x10];
5724 u8 op_mod[0x10];
5725
5726 u8 reserved_2[0x8];
5727 u8 qpn[0x18];
5728
5729 u8 reserved_3[0x20];
5730
5731 u8 multicast_gid[16][0x8];
5732};
5733
5734struct mlx5_ifc_arm_xrc_srq_out_bits {
5735 u8 status[0x8];
5736 u8 reserved_0[0x18];
5737
5738 u8 syndrome[0x20];
5739
5740 u8 reserved_1[0x40];
5741};
5742
5743enum {
5744 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
5745};
5746
5747struct mlx5_ifc_arm_xrc_srq_in_bits {
5748 u8 opcode[0x10];
5749 u8 reserved_0[0x10];
5750
5751 u8 reserved_1[0x10];
5752 u8 op_mod[0x10];
5753
5754 u8 reserved_2[0x8];
5755 u8 xrc_srqn[0x18];
5756
5757 u8 reserved_3[0x10];
5758 u8 lwm[0x10];
5759};
5760
5761struct mlx5_ifc_arm_rq_out_bits {
5762 u8 status[0x8];
5763 u8 reserved_0[0x18];
5764
5765 u8 syndrome[0x20];
5766
5767 u8 reserved_1[0x40];
5768};
5769
5770enum {
5771 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1,
5772};
5773
5774struct mlx5_ifc_arm_rq_in_bits {
5775 u8 opcode[0x10];
5776 u8 reserved_0[0x10];
5777
5778 u8 reserved_1[0x10];
5779 u8 op_mod[0x10];
5780
5781 u8 reserved_2[0x8];
5782 u8 srq_number[0x18];
5783
5784 u8 reserved_3[0x10];
5785 u8 lwm[0x10];
5786};
5787
5788struct mlx5_ifc_arm_dct_out_bits {
5789 u8 status[0x8];
5790 u8 reserved_0[0x18];
5791
5792 u8 syndrome[0x20];
5793
5794 u8 reserved_1[0x40];
5795};
5796
5797struct mlx5_ifc_arm_dct_in_bits {
5798 u8 opcode[0x10];
5799 u8 reserved_0[0x10];
5800
5801 u8 reserved_1[0x10];
5802 u8 op_mod[0x10];
5803
5804 u8 reserved_2[0x8];
5805 u8 dct_number[0x18];
5806
5807 u8 reserved_3[0x20];
5808};
5809
5810struct mlx5_ifc_alloc_xrcd_out_bits {
5811 u8 status[0x8];
5812 u8 reserved_0[0x18];
5813
5814 u8 syndrome[0x20];
5815
5816 u8 reserved_1[0x8];
5817 u8 xrcd[0x18];
5818
5819 u8 reserved_2[0x20];
5820};
5821
5822struct mlx5_ifc_alloc_xrcd_in_bits {
5823 u8 opcode[0x10];
5824 u8 reserved_0[0x10];
5825
5826 u8 reserved_1[0x10];
5827 u8 op_mod[0x10];
5828
5829 u8 reserved_2[0x40];
5830};
5831
5832struct mlx5_ifc_alloc_uar_out_bits {
5833 u8 status[0x8];
5834 u8 reserved_0[0x18];
5835
5836 u8 syndrome[0x20];
5837
5838 u8 reserved_1[0x8];
5839 u8 uar[0x18];
5840
5841 u8 reserved_2[0x20];
5842};
5843
5844struct mlx5_ifc_alloc_uar_in_bits {
5845 u8 opcode[0x10];
5846 u8 reserved_0[0x10];
5847
5848 u8 reserved_1[0x10];
5849 u8 op_mod[0x10];
5850
5851 u8 reserved_2[0x40];
5852};
5853
5854struct mlx5_ifc_alloc_transport_domain_out_bits {
5855 u8 status[0x8];
5856 u8 reserved_0[0x18];
5857
5858 u8 syndrome[0x20];
5859
5860 u8 reserved_1[0x8];
5861 u8 transport_domain[0x18];
5862
5863 u8 reserved_2[0x20];
5864};
5865
5866struct mlx5_ifc_alloc_transport_domain_in_bits {
5867 u8 opcode[0x10];
5868 u8 reserved_0[0x10];
5869
5870 u8 reserved_1[0x10];
5871 u8 op_mod[0x10];
5872
5873 u8 reserved_2[0x40];
5874};
5875
5876struct mlx5_ifc_alloc_q_counter_out_bits {
5877 u8 status[0x8];
5878 u8 reserved_0[0x18];
5879
5880 u8 syndrome[0x20];
5881
5882 u8 reserved_1[0x18];
5883 u8 counter_set_id[0x8];
5884
5885 u8 reserved_2[0x20];
5886};
5887
5888struct mlx5_ifc_alloc_q_counter_in_bits {
5889 u8 opcode[0x10];
5890 u8 reserved_0[0x10];
5891
5892 u8 reserved_1[0x10];
5893 u8 op_mod[0x10];
5894
5895 u8 reserved_2[0x40];
5896};
5897
5898struct mlx5_ifc_alloc_pd_out_bits {
5899 u8 status[0x8];
5900 u8 reserved_0[0x18];
5901
5902 u8 syndrome[0x20];
5903
5904 u8 reserved_1[0x8];
5905 u8 pd[0x18];
5906
5907 u8 reserved_2[0x20];
5908};
5909
5910struct mlx5_ifc_alloc_pd_in_bits {
5911 u8 opcode[0x10];
5912 u8 reserved_0[0x10];
5913
5914 u8 reserved_1[0x10];
5915 u8 op_mod[0x10];
5916
5917 u8 reserved_2[0x40];
5918};
5919
5920struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
5921 u8 status[0x8];
5922 u8 reserved_0[0x18];
5923
5924 u8 syndrome[0x20];
5925
5926 u8 reserved_1[0x40];
5927};
5928
5929struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
5930 u8 opcode[0x10];
5931 u8 reserved_0[0x10];
5932
5933 u8 reserved_1[0x10];
5934 u8 op_mod[0x10];
5935
5936 u8 reserved_2[0x20];
5937
5938 u8 reserved_3[0x10];
5939 u8 vxlan_udp_port[0x10];
5940};
5941
5942struct mlx5_ifc_access_register_out_bits {
5943 u8 status[0x8];
5944 u8 reserved_0[0x18];
5945
5946 u8 syndrome[0x20];
5947
5948 u8 reserved_1[0x40];
5949
5950 u8 register_data[0][0x20];
5951};
5952
5953enum {
5954 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
5955 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
5956};
5957
5958struct mlx5_ifc_access_register_in_bits {
5959 u8 opcode[0x10];
5960 u8 reserved_0[0x10];
5961
5962 u8 reserved_1[0x10];
5963 u8 op_mod[0x10];
5964
5965 u8 reserved_2[0x10];
5966 u8 register_id[0x10];
5967
5968 u8 argument[0x20];
5969
5970 u8 register_data[0][0x20];
5971};
5972
5973struct mlx5_ifc_sltp_reg_bits {
5974 u8 status[0x4];
5975 u8 version[0x4];
5976 u8 local_port[0x8];
5977 u8 pnat[0x2];
5978 u8 reserved_0[0x2];
5979 u8 lane[0x4];
5980 u8 reserved_1[0x8];
5981
5982 u8 reserved_2[0x20];
5983
5984 u8 reserved_3[0x7];
5985 u8 polarity[0x1];
5986 u8 ob_tap0[0x8];
5987 u8 ob_tap1[0x8];
5988 u8 ob_tap2[0x8];
5989
5990 u8 reserved_4[0xc];
5991 u8 ob_preemp_mode[0x4];
5992 u8 ob_reg[0x8];
5993 u8 ob_bias[0x8];
5994
5995 u8 reserved_5[0x20];
5996};
5997
5998struct mlx5_ifc_slrg_reg_bits {
5999 u8 status[0x4];
6000 u8 version[0x4];
6001 u8 local_port[0x8];
6002 u8 pnat[0x2];
6003 u8 reserved_0[0x2];
6004 u8 lane[0x4];
6005 u8 reserved_1[0x8];
6006
6007 u8 time_to_link_up[0x10];
6008 u8 reserved_2[0xc];
6009 u8 grade_lane_speed[0x4];
6010
6011 u8 grade_version[0x8];
6012 u8 grade[0x18];
6013
6014 u8 reserved_3[0x4];
6015 u8 height_grade_type[0x4];
6016 u8 height_grade[0x18];
6017
6018 u8 height_dz[0x10];
6019 u8 height_dv[0x10];
6020
6021 u8 reserved_4[0x10];
6022 u8 height_sigma[0x10];
6023
6024 u8 reserved_5[0x20];
6025
6026 u8 reserved_6[0x4];
6027 u8 phase_grade_type[0x4];
6028 u8 phase_grade[0x18];
6029
6030 u8 reserved_7[0x8];
6031 u8 phase_eo_pos[0x8];
6032 u8 reserved_8[0x8];
6033 u8 phase_eo_neg[0x8];
6034
6035 u8 ffe_set_tested[0x10];
6036 u8 test_errors_per_lane[0x10];
6037};
6038
6039struct mlx5_ifc_pvlc_reg_bits {
6040 u8 reserved_0[0x8];
6041 u8 local_port[0x8];
6042 u8 reserved_1[0x10];
6043
6044 u8 reserved_2[0x1c];
6045 u8 vl_hw_cap[0x4];
6046
6047 u8 reserved_3[0x1c];
6048 u8 vl_admin[0x4];
6049
6050 u8 reserved_4[0x1c];
6051 u8 vl_operational[0x4];
6052};
6053
6054struct mlx5_ifc_pude_reg_bits {
6055 u8 swid[0x8];
6056 u8 local_port[0x8];
6057 u8 reserved_0[0x4];
6058 u8 admin_status[0x4];
6059 u8 reserved_1[0x4];
6060 u8 oper_status[0x4];
6061
6062 u8 reserved_2[0x60];
6063};
6064
6065struct mlx5_ifc_ptys_reg_bits {
6066 u8 reserved_0[0x8];
6067 u8 local_port[0x8];
6068 u8 reserved_1[0xd];
6069 u8 proto_mask[0x3];
6070
6071 u8 reserved_2[0x40];
6072
6073 u8 eth_proto_capability[0x20];
6074
6075 u8 ib_link_width_capability[0x10];
6076 u8 ib_proto_capability[0x10];
6077
6078 u8 reserved_3[0x20];
6079
6080 u8 eth_proto_admin[0x20];
6081
6082 u8 ib_link_width_admin[0x10];
6083 u8 ib_proto_admin[0x10];
6084
6085 u8 reserved_4[0x20];
6086
6087 u8 eth_proto_oper[0x20];
6088
6089 u8 ib_link_width_oper[0x10];
6090 u8 ib_proto_oper[0x10];
6091
6092 u8 reserved_5[0x20];
6093
6094 u8 eth_proto_lp_advertise[0x20];
6095
6096 u8 reserved_6[0x60];
6097};
6098
6099struct mlx5_ifc_ptas_reg_bits {
6100 u8 reserved_0[0x20];
6101
6102 u8 algorithm_options[0x10];
6103 u8 reserved_1[0x4];
6104 u8 repetitions_mode[0x4];
6105 u8 num_of_repetitions[0x8];
6106
6107 u8 grade_version[0x8];
6108 u8 height_grade_type[0x4];
6109 u8 phase_grade_type[0x4];
6110 u8 height_grade_weight[0x8];
6111 u8 phase_grade_weight[0x8];
6112
6113 u8 gisim_measure_bits[0x10];
6114 u8 adaptive_tap_measure_bits[0x10];
6115
6116 u8 ber_bath_high_error_threshold[0x10];
6117 u8 ber_bath_mid_error_threshold[0x10];
6118
6119 u8 ber_bath_low_error_threshold[0x10];
6120 u8 one_ratio_high_threshold[0x10];
6121
6122 u8 one_ratio_high_mid_threshold[0x10];
6123 u8 one_ratio_low_mid_threshold[0x10];
6124
6125 u8 one_ratio_low_threshold[0x10];
6126 u8 ndeo_error_threshold[0x10];
6127
6128 u8 mixer_offset_step_size[0x10];
6129 u8 reserved_2[0x8];
6130 u8 mix90_phase_for_voltage_bath[0x8];
6131
6132 u8 mixer_offset_start[0x10];
6133 u8 mixer_offset_end[0x10];
6134
6135 u8 reserved_3[0x15];
6136 u8 ber_test_time[0xb];
6137};
6138
6139struct mlx5_ifc_pspa_reg_bits {
6140 u8 swid[0x8];
6141 u8 local_port[0x8];
6142 u8 sub_port[0x8];
6143 u8 reserved_0[0x8];
6144
6145 u8 reserved_1[0x20];
6146};
6147
6148struct mlx5_ifc_pqdr_reg_bits {
6149 u8 reserved_0[0x8];
6150 u8 local_port[0x8];
6151 u8 reserved_1[0x5];
6152 u8 prio[0x3];
6153 u8 reserved_2[0x6];
6154 u8 mode[0x2];
6155
6156 u8 reserved_3[0x20];
6157
6158 u8 reserved_4[0x10];
6159 u8 min_threshold[0x10];
6160
6161 u8 reserved_5[0x10];
6162 u8 max_threshold[0x10];
6163
6164 u8 reserved_6[0x10];
6165 u8 mark_probability_denominator[0x10];
6166
6167 u8 reserved_7[0x60];
6168};
6169
6170struct mlx5_ifc_ppsc_reg_bits {
6171 u8 reserved_0[0x8];
6172 u8 local_port[0x8];
6173 u8 reserved_1[0x10];
6174
6175 u8 reserved_2[0x60];
6176
6177 u8 reserved_3[0x1c];
6178 u8 wrps_admin[0x4];
6179
6180 u8 reserved_4[0x1c];
6181 u8 wrps_status[0x4];
6182
6183 u8 reserved_5[0x8];
6184 u8 up_threshold[0x8];
6185 u8 reserved_6[0x8];
6186 u8 down_threshold[0x8];
6187
6188 u8 reserved_7[0x20];
6189
6190 u8 reserved_8[0x1c];
6191 u8 srps_admin[0x4];
6192
6193 u8 reserved_9[0x1c];
6194 u8 srps_status[0x4];
6195
6196 u8 reserved_10[0x40];
6197};
6198
6199struct mlx5_ifc_pplr_reg_bits {
6200 u8 reserved_0[0x8];
6201 u8 local_port[0x8];
6202 u8 reserved_1[0x10];
6203
6204 u8 reserved_2[0x8];
6205 u8 lb_cap[0x8];
6206 u8 reserved_3[0x8];
6207 u8 lb_en[0x8];
6208};
6209
6210struct mlx5_ifc_pplm_reg_bits {
6211 u8 reserved_0[0x8];
6212 u8 local_port[0x8];
6213 u8 reserved_1[0x10];
6214
6215 u8 reserved_2[0x20];
6216
6217 u8 port_profile_mode[0x8];
6218 u8 static_port_profile[0x8];
6219 u8 active_port_profile[0x8];
6220 u8 reserved_3[0x8];
6221
6222 u8 retransmission_active[0x8];
6223 u8 fec_mode_active[0x18];
6224
6225 u8 reserved_4[0x20];
6226};
6227
6228struct mlx5_ifc_ppcnt_reg_bits {
6229 u8 swid[0x8];
6230 u8 local_port[0x8];
6231 u8 pnat[0x2];
6232 u8 reserved_0[0x8];
6233 u8 grp[0x6];
6234
6235 u8 clr[0x1];
6236 u8 reserved_1[0x1c];
6237 u8 prio_tc[0x3];
6238
6239 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6240};
6241
6242struct mlx5_ifc_ppad_reg_bits {
6243 u8 reserved_0[0x3];
6244 u8 single_mac[0x1];
6245 u8 reserved_1[0x4];
6246 u8 local_port[0x8];
6247 u8 mac_47_32[0x10];
6248
6249 u8 mac_31_0[0x20];
6250
6251 u8 reserved_2[0x40];
6252};
6253
6254struct mlx5_ifc_pmtu_reg_bits {
6255 u8 reserved_0[0x8];
6256 u8 local_port[0x8];
6257 u8 reserved_1[0x10];
6258
6259 u8 max_mtu[0x10];
6260 u8 reserved_2[0x10];
6261
6262 u8 admin_mtu[0x10];
6263 u8 reserved_3[0x10];
6264
6265 u8 oper_mtu[0x10];
6266 u8 reserved_4[0x10];
6267};
6268
6269struct mlx5_ifc_pmpr_reg_bits {
6270 u8 reserved_0[0x8];
6271 u8 module[0x8];
6272 u8 reserved_1[0x10];
6273
6274 u8 reserved_2[0x18];
6275 u8 attenuation_5g[0x8];
6276
6277 u8 reserved_3[0x18];
6278 u8 attenuation_7g[0x8];
6279
6280 u8 reserved_4[0x18];
6281 u8 attenuation_12g[0x8];
6282};
6283
6284struct mlx5_ifc_pmpe_reg_bits {
6285 u8 reserved_0[0x8];
6286 u8 module[0x8];
6287 u8 reserved_1[0xc];
6288 u8 module_status[0x4];
6289
6290 u8 reserved_2[0x60];
6291};
6292
6293struct mlx5_ifc_pmpc_reg_bits {
6294 u8 module_state_updated[32][0x8];
6295};
6296
6297struct mlx5_ifc_pmlpn_reg_bits {
6298 u8 reserved_0[0x4];
6299 u8 mlpn_status[0x4];
6300 u8 local_port[0x8];
6301 u8 reserved_1[0x10];
6302
6303 u8 e[0x1];
6304 u8 reserved_2[0x1f];
6305};
6306
6307struct mlx5_ifc_pmlp_reg_bits {
6308 u8 rxtx[0x1];
6309 u8 reserved_0[0x7];
6310 u8 local_port[0x8];
6311 u8 reserved_1[0x8];
6312 u8 width[0x8];
6313
6314 u8 lane0_module_mapping[0x20];
6315
6316 u8 lane1_module_mapping[0x20];
6317
6318 u8 lane2_module_mapping[0x20];
6319
6320 u8 lane3_module_mapping[0x20];
6321
6322 u8 reserved_2[0x160];
6323};
6324
6325struct mlx5_ifc_pmaos_reg_bits {
6326 u8 reserved_0[0x8];
6327 u8 module[0x8];
6328 u8 reserved_1[0x4];
6329 u8 admin_status[0x4];
6330 u8 reserved_2[0x4];
6331 u8 oper_status[0x4];
6332
6333 u8 ase[0x1];
6334 u8 ee[0x1];
6335 u8 reserved_3[0x1c];
6336 u8 e[0x2];
6337
6338 u8 reserved_4[0x40];
6339};
6340
6341struct mlx5_ifc_plpc_reg_bits {
6342 u8 reserved_0[0x4];
6343 u8 profile_id[0xc];
6344 u8 reserved_1[0x4];
6345 u8 proto_mask[0x4];
6346 u8 reserved_2[0x8];
6347
6348 u8 reserved_3[0x10];
6349 u8 lane_speed[0x10];
6350
6351 u8 reserved_4[0x17];
6352 u8 lpbf[0x1];
6353 u8 fec_mode_policy[0x8];
6354
6355 u8 retransmission_capability[0x8];
6356 u8 fec_mode_capability[0x18];
6357
6358 u8 retransmission_support_admin[0x8];
6359 u8 fec_mode_support_admin[0x18];
6360
6361 u8 retransmission_request_admin[0x8];
6362 u8 fec_mode_request_admin[0x18];
6363
6364 u8 reserved_5[0x80];
6365};
6366
6367struct mlx5_ifc_plib_reg_bits {
6368 u8 reserved_0[0x8];
6369 u8 local_port[0x8];
6370 u8 reserved_1[0x8];
6371 u8 ib_port[0x8];
6372
6373 u8 reserved_2[0x60];
6374};
6375
6376struct mlx5_ifc_plbf_reg_bits {
6377 u8 reserved_0[0x8];
6378 u8 local_port[0x8];
6379 u8 reserved_1[0xd];
6380 u8 lbf_mode[0x3];
6381
6382 u8 reserved_2[0x20];
6383};
6384
6385struct mlx5_ifc_pipg_reg_bits {
6386 u8 reserved_0[0x8];
6387 u8 local_port[0x8];
6388 u8 reserved_1[0x10];
6389
6390 u8 dic[0x1];
6391 u8 reserved_2[0x19];
6392 u8 ipg[0x4];
6393 u8 reserved_3[0x2];
6394};
6395
6396struct mlx5_ifc_pifr_reg_bits {
6397 u8 reserved_0[0x8];
6398 u8 local_port[0x8];
6399 u8 reserved_1[0x10];
6400
6401 u8 reserved_2[0xe0];
6402
6403 u8 port_filter[8][0x20];
6404
6405 u8 port_filter_update_en[8][0x20];
6406};
6407
6408struct mlx5_ifc_pfcc_reg_bits {
6409 u8 reserved_0[0x8];
6410 u8 local_port[0x8];
6411 u8 reserved_1[0x10];
6412
6413 u8 ppan[0x4];
6414 u8 reserved_2[0x4];
6415 u8 prio_mask_tx[0x8];
6416 u8 reserved_3[0x8];
6417 u8 prio_mask_rx[0x8];
6418
6419 u8 pptx[0x1];
6420 u8 aptx[0x1];
6421 u8 reserved_4[0x6];
6422 u8 pfctx[0x8];
6423 u8 reserved_5[0x10];
6424
6425 u8 pprx[0x1];
6426 u8 aprx[0x1];
6427 u8 reserved_6[0x6];
6428 u8 pfcrx[0x8];
6429 u8 reserved_7[0x10];
6430
6431 u8 reserved_8[0x80];
6432};
6433
6434struct mlx5_ifc_pelc_reg_bits {
6435 u8 op[0x4];
6436 u8 reserved_0[0x4];
6437 u8 local_port[0x8];
6438 u8 reserved_1[0x10];
6439
6440 u8 op_admin[0x8];
6441 u8 op_capability[0x8];
6442 u8 op_request[0x8];
6443 u8 op_active[0x8];
6444
6445 u8 admin[0x40];
6446
6447 u8 capability[0x40];
6448
6449 u8 request[0x40];
6450
6451 u8 active[0x40];
6452
6453 u8 reserved_2[0x80];
6454};
6455
6456struct mlx5_ifc_peir_reg_bits {
6457 u8 reserved_0[0x8];
6458 u8 local_port[0x8];
6459 u8 reserved_1[0x10];
6460
6461 u8 reserved_2[0xc];
6462 u8 error_count[0x4];
6463 u8 reserved_3[0x10];
6464
6465 u8 reserved_4[0xc];
6466 u8 lane[0x4];
6467 u8 reserved_5[0x8];
6468 u8 error_type[0x8];
6469};
6470
6471struct mlx5_ifc_pcap_reg_bits {
6472 u8 reserved_0[0x8];
6473 u8 local_port[0x8];
6474 u8 reserved_1[0x10];
6475
6476 u8 port_capability_mask[4][0x20];
6477};
6478
6479struct mlx5_ifc_paos_reg_bits {
6480 u8 swid[0x8];
6481 u8 local_port[0x8];
6482 u8 reserved_0[0x4];
6483 u8 admin_status[0x4];
6484 u8 reserved_1[0x4];
6485 u8 oper_status[0x4];
6486
6487 u8 ase[0x1];
6488 u8 ee[0x1];
6489 u8 reserved_2[0x1c];
6490 u8 e[0x2];
6491
6492 u8 reserved_3[0x40];
6493};
6494
6495struct mlx5_ifc_pamp_reg_bits {
6496 u8 reserved_0[0x8];
6497 u8 opamp_group[0x8];
6498 u8 reserved_1[0xc];
6499 u8 opamp_group_type[0x4];
6500
6501 u8 start_index[0x10];
6502 u8 reserved_2[0x4];
6503 u8 num_of_indices[0xc];
6504
6505 u8 index_data[18][0x10];
6506};
6507
6508struct mlx5_ifc_lane_2_module_mapping_bits {
6509 u8 reserved_0[0x6];
6510 u8 rx_lane[0x2];
6511 u8 reserved_1[0x6];
6512 u8 tx_lane[0x2];
6513 u8 reserved_2[0x8];
6514 u8 module[0x8];
6515};
6516
6517struct mlx5_ifc_bufferx_reg_bits {
6518 u8 reserved_0[0x6];
6519 u8 lossy[0x1];
6520 u8 epsb[0x1];
6521 u8 reserved_1[0xc];
6522 u8 size[0xc];
6523
6524 u8 xoff_threshold[0x10];
6525 u8 xon_threshold[0x10];
6526};
6527
6528struct mlx5_ifc_set_node_in_bits {
6529 u8 node_description[64][0x8];
6530};
6531
6532struct mlx5_ifc_register_power_settings_bits {
6533 u8 reserved_0[0x18];
6534 u8 power_settings_level[0x8];
6535
6536 u8 reserved_1[0x60];
6537};
6538
6539struct mlx5_ifc_register_host_endianness_bits {
6540 u8 he[0x1];
6541 u8 reserved_0[0x1f];
6542
6543 u8 reserved_1[0x60];
6544};
6545
6546struct mlx5_ifc_umr_pointer_desc_argument_bits {
6547 u8 reserved_0[0x20];
6548
6549 u8 mkey[0x20];
6550
6551 u8 addressh_63_32[0x20];
6552
6553 u8 addressl_31_0[0x20];
6554};
6555
6556struct mlx5_ifc_ud_adrs_vector_bits {
6557 u8 dc_key[0x40];
6558
6559 u8 ext[0x1];
6560 u8 reserved_0[0x7];
6561 u8 destination_qp_dct[0x18];
6562
6563 u8 static_rate[0x4];
6564 u8 sl_eth_prio[0x4];
6565 u8 fl[0x1];
6566 u8 mlid[0x7];
6567 u8 rlid_udp_sport[0x10];
6568
6569 u8 reserved_1[0x20];
6570
6571 u8 rmac_47_16[0x20];
6572
6573 u8 rmac_15_0[0x10];
6574 u8 tclass[0x8];
6575 u8 hop_limit[0x8];
6576
6577 u8 reserved_2[0x1];
6578 u8 grh[0x1];
6579 u8 reserved_3[0x2];
6580 u8 src_addr_index[0x8];
6581 u8 flow_label[0x14];
6582
6583 u8 rgid_rip[16][0x8];
6584};
6585
6586struct mlx5_ifc_pages_req_event_bits {
6587 u8 reserved_0[0x10];
6588 u8 function_id[0x10];
6589
6590 u8 num_pages[0x20];
6591
6592 u8 reserved_1[0xa0];
6593};
6594
6595struct mlx5_ifc_eqe_bits {
6596 u8 reserved_0[0x8];
6597 u8 event_type[0x8];
6598 u8 reserved_1[0x8];
6599 u8 event_sub_type[0x8];
6600
6601 u8 reserved_2[0xe0];
6602
6603 union mlx5_ifc_event_auto_bits event_data;
6604
6605 u8 reserved_3[0x10];
6606 u8 signature[0x8];
6607 u8 reserved_4[0x7];
6608 u8 owner[0x1];
6609};
6610
6611enum {
6612 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
6613};
6614
6615struct mlx5_ifc_cmd_queue_entry_bits {
6616 u8 type[0x8];
6617 u8 reserved_0[0x18];
6618
6619 u8 input_length[0x20];
6620
6621 u8 input_mailbox_pointer_63_32[0x20];
6622
6623 u8 input_mailbox_pointer_31_9[0x17];
6624 u8 reserved_1[0x9];
6625
6626 u8 command_input_inline_data[16][0x8];
6627
6628 u8 command_output_inline_data[16][0x8];
6629
6630 u8 output_mailbox_pointer_63_32[0x20];
6631
6632 u8 output_mailbox_pointer_31_9[0x17];
6633 u8 reserved_2[0x9];
6634
6635 u8 output_length[0x20];
6636
6637 u8 token[0x8];
6638 u8 signature[0x8];
6639 u8 reserved_3[0x8];
6640 u8 status[0x7];
6641 u8 ownership[0x1];
6642};
6643
6644struct mlx5_ifc_cmd_out_bits {
6645 u8 status[0x8];
6646 u8 reserved_0[0x18];
6647
6648 u8 syndrome[0x20];
6649
6650 u8 command_output[0x20];
6651};
6652
6653struct mlx5_ifc_cmd_in_bits {
6654 u8 opcode[0x10];
6655 u8 reserved_0[0x10];
6656
6657 u8 reserved_1[0x10];
6658 u8 op_mod[0x10];
6659
6660 u8 command[0][0x20];
6661};
6662
6663struct mlx5_ifc_cmd_if_box_bits {
6664 u8 mailbox_data[512][0x8];
6665
6666 u8 reserved_0[0x180];
6667
6668 u8 next_pointer_63_32[0x20];
6669
6670 u8 next_pointer_31_10[0x16];
6671 u8 reserved_1[0xa];
6672
6673 u8 block_number[0x20];
6674
6675 u8 reserved_2[0x8];
6676 u8 token[0x8];
6677 u8 ctrl_signature[0x8];
6678 u8 signature[0x8];
6679};
6680
6681struct mlx5_ifc_mtt_bits {
6682 u8 ptag_63_32[0x20];
6683
6684 u8 ptag_31_8[0x18];
6685 u8 reserved_0[0x6];
6686 u8 wr_en[0x1];
6687 u8 rd_en[0x1];
6688};
6689
6690enum {
6691 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
6692 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
6693 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
6694};
6695
6696enum {
6697 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
6698 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
6699 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
6700};
6701
6702enum {
6703 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
6704 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
6705 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
6706 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
6707 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
6708 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
6709 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
6710 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
6711 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
6712 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
6713 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
6714};
6715
6716struct mlx5_ifc_initial_seg_bits {
6717 u8 fw_rev_minor[0x10];
6718 u8 fw_rev_major[0x10];
6719
6720 u8 cmd_interface_rev[0x10];
6721 u8 fw_rev_subminor[0x10];
6722
6723 u8 reserved_0[0x40];
6724
6725 u8 cmdq_phy_addr_63_32[0x20];
6726
6727 u8 cmdq_phy_addr_31_12[0x14];
6728 u8 reserved_1[0x2];
6729 u8 nic_interface[0x2];
6730 u8 log_cmdq_size[0x4];
6731 u8 log_cmdq_stride[0x4];
6732
6733 u8 command_doorbell_vector[0x20];
6734
6735 u8 reserved_2[0xf00];
6736
6737 u8 initializing[0x1];
6738 u8 reserved_3[0x4];
6739 u8 nic_interface_supported[0x3];
6740 u8 reserved_4[0x18];
6741
6742 struct mlx5_ifc_health_buffer_bits health_buffer;
6743
6744 u8 no_dram_nic_offset[0x20];
6745
6746 u8 reserved_5[0x6e40];
6747
6748 u8 reserved_6[0x1f];
6749 u8 clear_int[0x1];
6750
6751 u8 health_syndrome[0x8];
6752 u8 health_counter[0x18];
6753
6754 u8 reserved_7[0x17fc0];
6755};
6756
6757union mlx5_ifc_ports_control_registers_document_bits {
6758 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
6759 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
6760 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
6761 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
6762 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
6763 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
6764 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
6765 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
6766 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
6767 struct mlx5_ifc_pamp_reg_bits pamp_reg;
6768 struct mlx5_ifc_paos_reg_bits paos_reg;
6769 struct mlx5_ifc_pcap_reg_bits pcap_reg;
6770 struct mlx5_ifc_peir_reg_bits peir_reg;
6771 struct mlx5_ifc_pelc_reg_bits pelc_reg;
6772 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
6773 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
6774 struct mlx5_ifc_pifr_reg_bits pifr_reg;
6775 struct mlx5_ifc_pipg_reg_bits pipg_reg;
6776 struct mlx5_ifc_plbf_reg_bits plbf_reg;
6777 struct mlx5_ifc_plib_reg_bits plib_reg;
6778 struct mlx5_ifc_plpc_reg_bits plpc_reg;
6779 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
6780 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
6781 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
6782 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
6783 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
6784 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
6785 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
6786 struct mlx5_ifc_ppad_reg_bits ppad_reg;
6787 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
6788 struct mlx5_ifc_pplm_reg_bits pplm_reg;
6789 struct mlx5_ifc_pplr_reg_bits pplr_reg;
6790 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
6791 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
6792 struct mlx5_ifc_pspa_reg_bits pspa_reg;
6793 struct mlx5_ifc_ptas_reg_bits ptas_reg;
6794 struct mlx5_ifc_ptys_reg_bits ptys_reg;
6795 struct mlx5_ifc_pude_reg_bits pude_reg;
6796 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
6797 struct mlx5_ifc_slrg_reg_bits slrg_reg;
6798 struct mlx5_ifc_sltp_reg_bits sltp_reg;
6799 u8 reserved_0[0x60e0];
6800};
6801
6802union mlx5_ifc_debug_enhancements_document_bits {
6803 struct mlx5_ifc_health_buffer_bits health_buffer;
6804 u8 reserved_0[0x200];
6805};
6806
6807union mlx5_ifc_uplink_pci_interface_document_bits {
6808 struct mlx5_ifc_initial_seg_bits initial_seg;
6809 u8 reserved_0[0x20060];
b775516b
EC		 6810};
6811
d29b796a 6812#endif /* MLX5_IFC_H */
Linux kernel - Deliverables
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