Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/include/linux/mmc/host.h | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * Host driver specific definitions. | |
9 | */ | |
10 | #ifndef LINUX_MMC_HOST_H | |
11 | #define LINUX_MMC_HOST_H | |
12 | ||
af8350c7 | 13 | #include <linux/leds.h> |
a7d1a1eb | 14 | #include <linux/mutex.h> |
d43c36dc | 15 | #include <linux/sched.h> |
313162d0 | 16 | #include <linux/device.h> |
1b676f70 | 17 | #include <linux/fault-inject.h> |
af8350c7 | 18 | |
aaac1b47 | 19 | #include <linux/mmc/core.h> |
da68c4eb | 20 | #include <linux/mmc/pm.h> |
1da177e4 LT |
21 | |
22 | struct mmc_ios { | |
23 | unsigned int clock; /* clock rate */ | |
24 | unsigned short vdd; | |
25 | ||
4be34c99 | 26 | /* vdd stores the bit number of the selected voltage range from below. */ |
1da177e4 LT |
27 | |
28 | unsigned char bus_mode; /* command output mode */ | |
29 | ||
30 | #define MMC_BUSMODE_OPENDRAIN 1 | |
31 | #define MMC_BUSMODE_PUSHPULL 2 | |
32 | ||
865e9f13 PO |
33 | unsigned char chip_select; /* SPI chip select */ |
34 | ||
35 | #define MMC_CS_DONTCARE 0 | |
36 | #define MMC_CS_HIGH 1 | |
37 | #define MMC_CS_LOW 2 | |
38 | ||
1da177e4 LT |
39 | unsigned char power_mode; /* power supply mode */ |
40 | ||
41 | #define MMC_POWER_OFF 0 | |
42 | #define MMC_POWER_UP 1 | |
43 | #define MMC_POWER_ON 2 | |
f218278a PO |
44 | |
45 | unsigned char bus_width; /* data bus width */ | |
46 | ||
47 | #define MMC_BUS_WIDTH_1 0 | |
48 | #define MMC_BUS_WIDTH_4 2 | |
b30f8af3 | 49 | #define MMC_BUS_WIDTH_8 3 |
cd9277c0 PO |
50 | |
51 | unsigned char timing; /* timing specification used */ | |
52 | ||
53 | #define MMC_TIMING_LEGACY 0 | |
54 | #define MMC_TIMING_MMC_HS 1 | |
55 | #define MMC_TIMING_SD_HS 2 | |
ed9dbb6e KL |
56 | #define MMC_TIMING_UHS_SDR12 3 |
57 | #define MMC_TIMING_UHS_SDR25 4 | |
58 | #define MMC_TIMING_UHS_SDR50 5 | |
59 | #define MMC_TIMING_UHS_SDR104 6 | |
60 | #define MMC_TIMING_UHS_DDR50 7 | |
61 | #define MMC_TIMING_MMC_HS200 8 | |
0f8d8ea6 | 62 | |
0f8d8ea6 | 63 | #define MMC_SDR_MODE 0 |
49e3b5a4 AH |
64 | #define MMC_1_2V_DDR_MODE 1 |
65 | #define MMC_1_8V_DDR_MODE 2 | |
a4924c71 G |
66 | #define MMC_1_2V_SDR_MODE 3 |
67 | #define MMC_1_8V_SDR_MODE 4 | |
f2119df6 AN |
68 | |
69 | unsigned char signal_voltage; /* signalling voltage (1.8V or 3.3V) */ | |
70 | ||
71 | #define MMC_SIGNAL_VOLTAGE_330 0 | |
72 | #define MMC_SIGNAL_VOLTAGE_180 1 | |
4c4cb171 | 73 | #define MMC_SIGNAL_VOLTAGE_120 2 |
d6d50a15 AN |
74 | |
75 | unsigned char drv_type; /* driver type (A, B, C, D) */ | |
76 | ||
77 | #define MMC_SET_DRIVER_TYPE_B 0 | |
78 | #define MMC_SET_DRIVER_TYPE_A 1 | |
79 | #define MMC_SET_DRIVER_TYPE_C 2 | |
80 | #define MMC_SET_DRIVER_TYPE_D 3 | |
1da177e4 LT |
81 | }; |
82 | ||
83 | struct mmc_host_ops { | |
8ea926b2 | 84 | /* |
907d2e7c AH |
85 | * 'enable' is called when the host is claimed and 'disable' is called |
86 | * when the host is released. 'enable' and 'disable' are deprecated. | |
8ea926b2 AH |
87 | */ |
88 | int (*enable)(struct mmc_host *host); | |
907d2e7c | 89 | int (*disable)(struct mmc_host *host); |
aa8b683a PF |
90 | /* |
91 | * It is optional for the host to implement pre_req and post_req in | |
92 | * order to support double buffering of requests (prepare one | |
93 | * request while another request is active). | |
7c8a2829 PF |
94 | * pre_req() must always be followed by a post_req(). |
95 | * To undo a call made to pre_req(), call post_req() with | |
96 | * a nonzero err condition. | |
aa8b683a PF |
97 | */ |
98 | void (*post_req)(struct mmc_host *host, struct mmc_request *req, | |
99 | int err); | |
100 | void (*pre_req)(struct mmc_host *host, struct mmc_request *req, | |
101 | bool is_first_req); | |
1da177e4 | 102 | void (*request)(struct mmc_host *host, struct mmc_request *req); |
28f52482 AV |
103 | /* |
104 | * Avoid calling these three functions too often or in a "fast path", | |
105 | * since underlaying controller might implement them in an expensive | |
106 | * and/or slow way. | |
107 | * | |
108 | * Also note that these functions might sleep, so don't call them | |
109 | * in the atomic contexts! | |
08f80bb5 AV |
110 | * |
111 | * Return values for the get_ro callback should be: | |
112 | * 0 for a read/write card | |
113 | * 1 for a read-only card | |
114 | * -ENOSYS when not supported (equal to NULL callback) | |
115 | * or a negative errno value when something bad happened | |
116 | * | |
ee63a7d2 | 117 | * Return values for the get_cd callback should be: |
08f80bb5 AV |
118 | * 0 for a absent card |
119 | * 1 for a present card | |
120 | * -ENOSYS when not supported (equal to NULL callback) | |
121 | * or a negative errno value when something bad happened | |
28f52482 | 122 | */ |
1da177e4 | 123 | void (*set_ios)(struct mmc_host *host, struct mmc_ios *ios); |
a00fc090 | 124 | int (*get_ro)(struct mmc_host *host); |
28f52482 AV |
125 | int (*get_cd)(struct mmc_host *host); |
126 | ||
17b759af | 127 | void (*enable_sdio_irq)(struct mmc_host *host, int enable); |
3fcb027d DM |
128 | |
129 | /* optional callback for HC quirks */ | |
130 | void (*init_card)(struct mmc_host *host, struct mmc_card *card); | |
f2119df6 AN |
131 | |
132 | int (*start_signal_voltage_switch)(struct mmc_host *host, struct mmc_ios *ios); | |
a4924c71 | 133 | |
d887874e JR |
134 | /* Check if the card is pulling dat[0:3] low */ |
135 | int (*card_busy)(struct mmc_host *host); | |
136 | ||
a4924c71 G |
137 | /* The tuning command opcode value is different for SD and eMMC cards */ |
138 | int (*execute_tuning)(struct mmc_host *host, u32 opcode); | |
ca8e99b3 | 139 | int (*select_drive_strength)(unsigned int max_dtr, int host_drv, int card_drv); |
b2499518 | 140 | void (*hw_reset)(struct mmc_host *host); |
9f1fb60a | 141 | void (*card_event)(struct mmc_host *host); |
1da177e4 LT |
142 | }; |
143 | ||
144 | struct mmc_card; | |
145 | struct device; | |
146 | ||
aa8b683a PF |
147 | struct mmc_async_req { |
148 | /* active mmc request */ | |
149 | struct mmc_request *mrq; | |
150 | /* | |
151 | * Check error status of completed mmc request. | |
152 | * Returns 0 if success otherwise non zero. | |
153 | */ | |
154 | int (*err_check) (struct mmc_card *, struct mmc_async_req *); | |
155 | }; | |
156 | ||
27410ee7 GL |
157 | /** |
158 | * struct mmc_slot - MMC slot functions | |
159 | * | |
160 | * @cd_irq: MMC/SD-card slot hotplug detection IRQ or -EINVAL | |
a7d1a1eb | 161 | * @lock: protect the @handler_priv pointer |
27410ee7 GL |
162 | * @handler_priv: MMC/SD-card slot context |
163 | * | |
164 | * Some MMC/SD host controllers implement slot-functions like card and | |
165 | * write-protect detection natively. However, a large number of controllers | |
166 | * leave these functions to the CPU. This struct provides a hook to attach | |
167 | * such slot-function drivers. | |
168 | */ | |
169 | struct mmc_slot { | |
170 | int cd_irq; | |
a7d1a1eb | 171 | struct mutex lock; |
b67e1980 GL |
172 | void *handler_priv; |
173 | }; | |
174 | ||
2220eedf KD |
175 | /** |
176 | * mmc_context_info - synchronization details for mmc context | |
177 | * @is_done_rcv wake up reason was done request | |
178 | * @is_new_req wake up reason was new request | |
179 | * @is_waiting_last_req mmc context waiting for single running request | |
180 | * @wait wait queue | |
181 | * @lock lock to protect data fields | |
182 | */ | |
183 | struct mmc_context_info { | |
184 | bool is_done_rcv; | |
185 | bool is_new_req; | |
186 | bool is_waiting_last_req; | |
187 | wait_queue_head_t wait; | |
188 | spinlock_t lock; | |
189 | }; | |
190 | ||
e137788d GL |
191 | struct regulator; |
192 | ||
193 | struct mmc_supply { | |
194 | struct regulator *vmmc; /* Card power supply */ | |
195 | struct regulator *vqmmc; /* Optional Vccq supply */ | |
196 | }; | |
197 | ||
1da177e4 | 198 | struct mmc_host { |
fcaf71fd GKH |
199 | struct device *parent; |
200 | struct device class_dev; | |
dce77377 | 201 | int index; |
f57b225e | 202 | const struct mmc_host_ops *ops; |
1da177e4 LT |
203 | unsigned int f_min; |
204 | unsigned int f_max; | |
88ae8b86 | 205 | unsigned int f_init; |
1da177e4 | 206 | u32 ocr_avail; |
8f230f45 TI |
207 | u32 ocr_avail_sdio; /* SDIO-specific OCR */ |
208 | u32 ocr_avail_sd; /* SD-specific OCR */ | |
209 | u32 ocr_avail_mmc; /* MMC-specific OCR */ | |
4c2ef25f | 210 | struct notifier_block pm_notify; |
55c4665e AL |
211 | u32 max_current_330; |
212 | u32 max_current_300; | |
213 | u32 max_current_180; | |
1da177e4 | 214 | |
55556da0 | 215 | #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ |
f74d132c PO |
216 | #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ |
217 | #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ | |
218 | #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ | |
219 | #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ | |
220 | #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ | |
221 | #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ | |
222 | #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ | |
223 | #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ | |
224 | #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ | |
225 | #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ | |
226 | #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ | |
227 | #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ | |
228 | #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ | |
229 | #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ | |
230 | #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ | |
231 | #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ | |
232 | ||
5f1a4dd0 | 233 | u32 caps; /* Host capabilities */ |
f218278a PO |
234 | |
235 | #define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */ | |
23af6039 PO |
236 | #define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */ |
237 | #define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */ | |
238 | #define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */ | |
239 | #define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */ | |
240 | #define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */ | |
b30f8af3 | 241 | #define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */ |
c4d770d7 | 242 | #define MMC_CAP_AGGRESSIVE_PM (1 << 7) /* Suspend (e)MMC/SD at idle */ |
9feae246 | 243 | #define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */ |
b1ebe384 | 244 | #define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */ |
dfe86cba | 245 | #define MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */ |
dfc13e84 HP |
246 | #define MMC_CAP_1_8V_DDR (1 << 11) /* can support */ |
247 | /* DDR mode at 1.8V */ | |
248 | #define MMC_CAP_1_2V_DDR (1 << 12) /* can support */ | |
249 | /* DDR mode at 1.2V */ | |
ed919b01 | 250 | #define MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */ |
22113efd | 251 | #define MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */ |
f2119df6 AN |
252 | #define MMC_CAP_UHS_SDR12 (1 << 15) /* Host supports UHS SDR12 mode */ |
253 | #define MMC_CAP_UHS_SDR25 (1 << 16) /* Host supports UHS SDR25 mode */ | |
254 | #define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */ | |
255 | #define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */ | |
256 | #define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */ | |
d6d50a15 AN |
257 | #define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */ |
258 | #define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */ | |
259 | #define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */ | |
d0c97cfb | 260 | #define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */ |
b2499518 | 261 | #define MMC_CAP_HW_RESET (1 << 31) /* Hardware reset */ |
f218278a | 262 | |
5f1a4dd0 | 263 | u32 caps2; /* More host capabilities */ |
f7c56ef2 AH |
264 | |
265 | #define MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */ | |
881d1c25 | 266 | #define MMC_CAP2_CACHE_CTRL (1 << 1) /* Allow cache control */ |
53275c21 | 267 | #define MMC_CAP2_FULL_PWR_CYCLE (1 << 2) /* Can do full power cycle */ |
2bf22b39 | 268 | #define MMC_CAP2_NO_MULTI_READ (1 << 3) /* Multiblock reads don't work */ |
aa9df4fb | 269 | #define MMC_CAP2_NO_SLEEP_CMD (1 << 4) /* Don't allow sleep command */ |
a4924c71 G |
270 | #define MMC_CAP2_HS200_1_8V_SDR (1 << 5) /* can support */ |
271 | #define MMC_CAP2_HS200_1_2V_SDR (1 << 6) /* can support */ | |
272 | #define MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR | \ | |
273 | MMC_CAP2_HS200_1_2V_SDR) | |
6e8201f5 | 274 | #define MMC_CAP2_BROKEN_VOLTAGE (1 << 7) /* Use the broken voltage */ |
83bb24aa | 275 | #define MMC_CAP2_HC_ERASE_SZ (1 << 9) /* High-capacity erase size */ |
5c08d7fa GL |
276 | #define MMC_CAP2_CD_ACTIVE_HIGH (1 << 10) /* Card-detect signal active high */ |
277 | #define MMC_CAP2_RO_ACTIVE_HIGH (1 << 11) /* Write-protect signal active high */ | |
abd9ac14 SJ |
278 | #define MMC_CAP2_PACKED_RD (1 << 12) /* Allow packed read */ |
279 | #define MMC_CAP2_PACKED_WR (1 << 13) /* Allow packed write */ | |
280 | #define MMC_CAP2_PACKED_CMD (MMC_CAP2_PACKED_RD | \ | |
281 | MMC_CAP2_PACKED_WR) | |
0d3e3350 | 282 | #define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14) /* Don't power up before scan */ |
775a9362 | 283 | #define MMC_CAP2_SANITIZE (1 << 15) /* Support Sanitize */ |
f7c56ef2 | 284 | |
da68c4eb NP |
285 | mmc_pm_flag_t pm_caps; /* supported pm features */ |
286 | ||
04566831 LW |
287 | #ifdef CONFIG_MMC_CLKGATE |
288 | int clk_requests; /* internal reference counter */ | |
289 | unsigned int clk_delay; /* number of MCI clk hold cycles */ | |
290 | bool clk_gated; /* clock gated */ | |
597dd9d7 | 291 | struct delayed_work clk_gate_work; /* delayed clock gate */ |
04566831 LW |
292 | unsigned int clk_old; /* old clock value cache */ |
293 | spinlock_t clk_lock; /* lock for clk fields */ | |
86f315bb | 294 | struct mutex clk_gate_mutex; /* mutex for clock gating */ |
597dd9d7 SRT |
295 | struct device_attribute clkgate_delay_attr; |
296 | unsigned long clkgate_delay; | |
04566831 LW |
297 | #endif |
298 | ||
1da177e4 LT |
299 | /* host specific block data */ |
300 | unsigned int max_seg_size; /* see blk_queue_max_segment_size */ | |
a36274e0 | 301 | unsigned short max_segs; /* see blk_queue_max_segments */ |
1da177e4 | 302 | unsigned short unused; |
55db890a | 303 | unsigned int max_req_size; /* maximum number of bytes in one req */ |
fe4a3c7a | 304 | unsigned int max_blk_size; /* maximum size of one mmc block */ |
55db890a | 305 | unsigned int max_blk_count; /* maximum number of blocks in one req */ |
e056a1b5 | 306 | unsigned int max_discard_to; /* max. discard timeout in ms */ |
1da177e4 LT |
307 | |
308 | /* private data */ | |
7ea239d9 PO |
309 | spinlock_t lock; /* lock for claim and bus ops */ |
310 | ||
1da177e4 LT |
311 | struct mmc_ios ios; /* current io bus settings */ |
312 | u32 ocr; /* the current OCR setting */ | |
313 | ||
97018580 DB |
314 | /* group bitfields together to minimize padding */ |
315 | unsigned int use_spi_crc:1; | |
316 | unsigned int claimed:1; /* host exclusively claimed */ | |
317 | unsigned int bus_dead:1; /* bus has been released */ | |
318 | #ifdef CONFIG_MMC_DEBUG | |
319 | unsigned int removed:1; /* host is being removed */ | |
320 | #endif | |
321 | ||
4c2ef25f | 322 | int rescan_disable; /* disable card detection */ |
3339d1e3 | 323 | int rescan_entered; /* used with nonremovable devices */ |
8ea926b2 | 324 | |
b855885e | 325 | struct mmc_card *card; /* device attached to this host */ |
1da177e4 LT |
326 | |
327 | wait_queue_head_t wq; | |
319a3f14 AH |
328 | struct task_struct *claimer; /* task that has host claimed */ |
329 | int claim_cnt; /* "claim" nesting count */ | |
f22ee4ed | 330 | |
c4028958 | 331 | struct delayed_work detect; |
d3049504 | 332 | int detect_change; /* card detect flag */ |
27410ee7 | 333 | struct mmc_slot slot; |
01357dca | 334 | |
7ea239d9 PO |
335 | const struct mmc_bus_ops *bus_ops; /* current bus driver */ |
336 | unsigned int bus_refs; /* reference counter */ | |
7ea239d9 | 337 | |
d1496c39 NP |
338 | unsigned int sdio_irqs; |
339 | struct task_struct *sdio_irq_thread; | |
bbbc4c4d | 340 | bool sdio_irq_pending; |
d1496c39 NP |
341 | atomic_t sdio_irq_thread_abort; |
342 | ||
da68c4eb NP |
343 | mmc_pm_flag_t pm_flags; /* requested pm features */ |
344 | ||
af8350c7 | 345 | struct led_trigger *led; /* activity led */ |
af8350c7 | 346 | |
99fc5131 LW |
347 | #ifdef CONFIG_REGULATOR |
348 | bool regulator_enabled; /* regulator state */ | |
349 | #endif | |
e137788d | 350 | struct mmc_supply supply; |
99fc5131 | 351 | |
6edd8ee6 HS |
352 | struct dentry *debugfs_root; |
353 | ||
aa8b683a | 354 | struct mmc_async_req *areq; /* active async req */ |
2220eedf | 355 | struct mmc_context_info context_info; /* async synchronization info */ |
aa8b683a | 356 | |
1b676f70 PF |
357 | #ifdef CONFIG_FAIL_MMC_REQUEST |
358 | struct fault_attr fail_mmc_request; | |
359 | #endif | |
360 | ||
df16219f GC |
361 | unsigned int actual_clock; /* Actual HC clock rate */ |
362 | ||
eed222ac AL |
363 | unsigned int slotno; /* used for sdio acpi binding */ |
364 | ||
01357dca | 365 | unsigned long private[0] ____cacheline_aligned; |
1da177e4 LT |
366 | }; |
367 | ||
8c9beb11 GL |
368 | struct mmc_host *mmc_alloc_host(int extra, struct device *); |
369 | int mmc_add_host(struct mmc_host *); | |
370 | void mmc_remove_host(struct mmc_host *); | |
371 | void mmc_free_host(struct mmc_host *); | |
ec0a7517 | 372 | int mmc_of_parse(struct mmc_host *host); |
1da177e4 | 373 | |
01357dca RK |
374 | static inline void *mmc_priv(struct mmc_host *host) |
375 | { | |
376 | return (void *)host->private; | |
377 | } | |
378 | ||
97018580 DB |
379 | #define mmc_host_is_spi(host) ((host)->caps & MMC_CAP_SPI) |
380 | ||
fcaf71fd | 381 | #define mmc_dev(x) ((x)->parent) |
11354d03 | 382 | #define mmc_classdev(x) (&(x)->class_dev) |
d1b26863 | 383 | #define mmc_hostname(x) (dev_name(&(x)->class_dev)) |
1da177e4 | 384 | |
8c9beb11 GL |
385 | int mmc_suspend_host(struct mmc_host *); |
386 | int mmc_resume_host(struct mmc_host *); | |
1da177e4 | 387 | |
8c9beb11 GL |
388 | int mmc_power_save_host(struct mmc_host *host); |
389 | int mmc_power_restore_host(struct mmc_host *host); | |
eae1aeee | 390 | |
8c9beb11 GL |
391 | void mmc_detect_change(struct mmc_host *, unsigned long delay); |
392 | void mmc_request_done(struct mmc_host *, struct mmc_request *); | |
1da177e4 | 393 | |
8c9beb11 | 394 | int mmc_cache_ctrl(struct mmc_host *, u8); |
881d1c25 | 395 | |
17b759af NP |
396 | static inline void mmc_signal_sdio_irq(struct mmc_host *host) |
397 | { | |
398 | host->ops->enable_sdio_irq(host, 0); | |
bbbc4c4d | 399 | host->sdio_irq_pending = true; |
17b759af NP |
400 | wake_up_process(host->sdio_irq_thread); |
401 | } | |
402 | ||
99fc5131 | 403 | #ifdef CONFIG_REGULATOR |
5c13941a | 404 | int mmc_regulator_get_ocrmask(struct regulator *supply); |
99fc5131 LW |
405 | int mmc_regulator_set_ocr(struct mmc_host *mmc, |
406 | struct regulator *supply, | |
407 | unsigned short vdd_bit); | |
e137788d | 408 | int mmc_regulator_get_supply(struct mmc_host *mmc); |
99fc5131 LW |
409 | #else |
410 | static inline int mmc_regulator_get_ocrmask(struct regulator *supply) | |
411 | { | |
412 | return 0; | |
413 | } | |
414 | ||
415 | static inline int mmc_regulator_set_ocr(struct mmc_host *mmc, | |
416 | struct regulator *supply, | |
417 | unsigned short vdd_bit) | |
418 | { | |
419 | return 0; | |
420 | } | |
e137788d GL |
421 | |
422 | static inline int mmc_regulator_get_supply(struct mmc_host *mmc) | |
423 | { | |
424 | return 0; | |
425 | } | |
99fc5131 | 426 | #endif |
5c13941a | 427 | |
4c2ef25f | 428 | int mmc_pm_notify(struct notifier_block *notify_block, unsigned long, void *); |
8ea926b2 | 429 | |
71d7d3d1 | 430 | /* Module parameter */ |
90ab5ee9 | 431 | extern bool mmc_assume_removable; |
71d7d3d1 MF |
432 | |
433 | static inline int mmc_card_is_removable(struct mmc_host *host) | |
434 | { | |
435 | return !(host->caps & MMC_CAP_NONREMOVABLE) && mmc_assume_removable; | |
436 | } | |
437 | ||
a5e9425d | 438 | static inline int mmc_card_keep_power(struct mmc_host *host) |
080bc977 OBC |
439 | { |
440 | return host->pm_flags & MMC_PM_KEEP_POWER; | |
441 | } | |
442 | ||
6b93d01f OBC |
443 | static inline int mmc_card_wake_sdio_irq(struct mmc_host *host) |
444 | { | |
445 | return host->pm_flags & MMC_PM_WAKE_SDIO_IRQ; | |
446 | } | |
d0c97cfb AW |
447 | |
448 | static inline int mmc_host_cmd23(struct mmc_host *host) | |
449 | { | |
450 | return host->caps & MMC_CAP_CMD23; | |
451 | } | |
f7c56ef2 AH |
452 | |
453 | static inline int mmc_boot_partition_access(struct mmc_host *host) | |
454 | { | |
455 | return !(host->caps2 & MMC_CAP2_BOOTPART_NOACC); | |
456 | } | |
457 | ||
41875e38 SRT |
458 | static inline int mmc_host_uhs(struct mmc_host *host) |
459 | { | |
460 | return host->caps & | |
461 | (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | | |
462 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | | |
463 | MMC_CAP_UHS_DDR50); | |
464 | } | |
465 | ||
ce39f9d1 SJ |
466 | static inline int mmc_host_packed_wr(struct mmc_host *host) |
467 | { | |
468 | return host->caps2 & MMC_CAP2_PACKED_WR; | |
469 | } | |
470 | ||
2c4967f7 SRT |
471 | #ifdef CONFIG_MMC_CLKGATE |
472 | void mmc_host_clk_hold(struct mmc_host *host); | |
473 | void mmc_host_clk_release(struct mmc_host *host); | |
474 | unsigned int mmc_host_clk_rate(struct mmc_host *host); | |
475 | ||
476 | #else | |
477 | static inline void mmc_host_clk_hold(struct mmc_host *host) | |
478 | { | |
479 | } | |
480 | ||
481 | static inline void mmc_host_clk_release(struct mmc_host *host) | |
482 | { | |
483 | } | |
484 | ||
485 | static inline unsigned int mmc_host_clk_rate(struct mmc_host *host) | |
486 | { | |
487 | return host->ios.clock; | |
488 | } | |
489 | #endif | |
100e9186 | 490 | #endif /* LINUX_MMC_HOST_H */ |