[deliverable/linux.git] / include / linux / mmc / sh_mmcif.h

/*
 * include/linux/mmc/sh_mmcif.h
 *
 * platform data for eMMC driver
 *
 * Copyright (C) 2010 Renesas Solutions Corp.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 *
 */

#ifndef __SH_MMCIF_H__
#define __SH_MMCIF_H__

#include <linux/platform_device.h>
#include <linux/io.h>

/*
 * MMCIF : CE_CLK_CTRL [19:16]
 * 1000 : Peripheral clock / 512
 * 0111 : Peripheral clock / 256
 * 0110 : Peripheral clock / 128
 * 0101 : Peripheral clock / 64
 * 0100 : Peripheral clock / 32
 * 0011 : Peripheral clock / 16
 * 0010 : Peripheral clock / 8
 * 0001 : Peripheral clock / 4
 * 0000 : Peripheral clock / 2
 * 1111 : Peripheral clock (sup_pclk set '1')
 */

struct sh_mmcif_plat_data {
	void (*set_pwr)(struct platform_device *pdev, int state);
	void (*down_pwr)(struct platform_device *pdev);
	int (*get_cd)(struct platform_device *pdef);
	u8	sup_pclk;	/* 1 :SH7757, 0: SH7724/SH7372 */
	unsigned long caps;
	u32	ocr;
};

#define MMCIF_CE_CMD_SET	0x00000000
#define MMCIF_CE_ARG		0x00000008
#define MMCIF_CE_ARG_CMD12	0x0000000C
#define MMCIF_CE_CMD_CTRL	0x00000010
#define MMCIF_CE_BLOCK_SET	0x00000014
#define MMCIF_CE_CLK_CTRL	0x00000018
#define MMCIF_CE_BUF_ACC	0x0000001C
#define MMCIF_CE_RESP3		0x00000020
#define MMCIF_CE_RESP2		0x00000024
#define MMCIF_CE_RESP1		0x00000028
#define MMCIF_CE_RESP0		0x0000002C
#define MMCIF_CE_RESP_CMD12	0x00000030
#define MMCIF_CE_DATA		0x00000034
#define MMCIF_CE_INT		0x00000040
#define MMCIF_CE_INT_MASK	0x00000044
#define MMCIF_CE_HOST_STS1	0x00000048
#define MMCIF_CE_HOST_STS2	0x0000004C
#define MMCIF_CE_VERSION	0x0000007C

/* CE_BUF_ACC */
#define BUF_ACC_DMAWEN		(1 << 25)
#define BUF_ACC_DMAREN		(1 << 24)
#define BUF_ACC_BUSW_32		(0 << 17)
#define BUF_ACC_BUSW_16		(1 << 17)
#define BUF_ACC_ATYP		(1 << 16)

/* CE_CLK_CTRL */
#define CLK_ENABLE		(1 << 24) /* 1: output mmc clock */
#define CLK_CLEAR		((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
#define CLK_SUP_PCLK		((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
#define CLKDIV_4		(1<<16) /* mmc clock frequency.
					 * n: bus clock/(2^(n+1)) */
#define CLKDIV_256		(7<<16) /* mmc clock frequency. (see above) */
#define SRSPTO_256		((1 << 13) | (0 << 12)) /* resp timeout */
#define SRBSYTO_29		((1 << 11) | (1 << 10) |	\
				 (1 << 9) | (1 << 8)) /* resp busy timeout */
#define SRWDTO_29		((1 << 7) | (1 << 6) |		\
				 (1 << 5) | (1 << 4)) /* read/write timeout */
#define SCCSTO_29		((1 << 3) | (1 << 2) |		\
				 (1 << 1) | (1 << 0)) /* ccs timeout */

/* CE_VERSION */
#define SOFT_RST_ON		(1 << 31)
#define SOFT_RST_OFF		0

static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
{
	return readl(addr + reg);
}

static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
{
	writel(val, addr + reg);
}

#define SH_MMCIF_BBS 512 /* boot block size */

enum { MMCIF_PROGRESS_ENTER, MMCIF_PROGRESS_INIT,
       MMCIF_PROGRESS_LOAD, MMCIF_PROGRESS_DONE };

static inline void sh_mmcif_boot_cmd_send(void __iomem *base,
					  unsigned long cmd, unsigned long arg)
{
	sh_mmcif_writel(base, MMCIF_CE_INT, 0);
	sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
	sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
}

static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
{
	unsigned long tmp;
	int cnt;

	for (cnt = 0; cnt < 1000000; cnt++) {
		tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
		if (tmp & mask) {
			sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
			return 0;
		}
	}

	return -1;
}

static inline int sh_mmcif_boot_cmd(void __iomem *base,
				    unsigned long cmd, unsigned long arg)
{
	sh_mmcif_boot_cmd_send(base, cmd, arg);
	return sh_mmcif_boot_cmd_poll(base, 0x00010000);
}

static inline int sh_mmcif_boot_do_read_single(void __iomem *base,
					       unsigned int block_nr,
					       unsigned long *buf)
{
	int k;

	/* CMD13 - Status */
	sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);

	if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)
		return -1;

	/* CMD17 - Read */
	sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);
	if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)
		return -1;

	for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
		buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);

	return 0;
}

static inline int sh_mmcif_boot_do_read(void __iomem *base,
					unsigned long first_block,
					unsigned long nr_blocks,
					void *buf)
{
	unsigned long k;
	int ret = 0;

	/* CMD16 - Set the block size */
	sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);

	for (k = 0; !ret && k < nr_blocks; k++)
		ret = sh_mmcif_boot_do_read_single(base, first_block + k,
						   buf + (k * SH_MMCIF_BBS));

	return ret;
}

static inline void sh_mmcif_boot_init(void __iomem *base)
{
	/* reset */
	sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);
	sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);

	/* byte swap */
	sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);

	/* Set block size in MMCIF hardware */
	sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);

	/* Enable the clock, set it to Bus clock/256 (about 325Khz). */
	sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
			CLK_ENABLE | CLKDIV_256 | SRSPTO_256 |
			SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);

	/* CMD0 */
	sh_mmcif_boot_cmd(base, 0x00000040, 0);

	/* CMD1 - Get OCR */
	do {
		sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */
	} while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)
		 != 0x80000000);

	/* CMD2 - Get CID */
	sh_mmcif_boot_cmd(base, 0x02806040, 0);

	/* CMD3 - Set card relative address */
	sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
}

static inline void sh_mmcif_boot_slurp(void __iomem *base,
				       unsigned char *buf,
				       unsigned long no_bytes)
{
	unsigned long tmp;

	/* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
	sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
			CLK_ENABLE | CLKDIV_4 | SRSPTO_256 |
			SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);

	/* CMD9 - Get CSD */
	sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);

	/* CMD7 - Select the card */
	sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);

	tmp = no_bytes / SH_MMCIF_BBS;
	tmp += (no_bytes % SH_MMCIF_BBS) ? 1 : 0;

	sh_mmcif_boot_do_read(base, 512, tmp, buf);
}

#endif /* __SH_MMCIF_H__ */
Commit	Line	Data
fdc50a94 YG	1	/*
	2	* include/linux/mmc/sh_mmcif.h
	3	*
	4	* platform data for eMMC driver
	5	*
	6	* Copyright (C) 2010 Renesas Solutions Corp.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License.
	11	*
	12	*/
	13
	14	#ifndef __SH_MMCIF_H__
	15	#define __SH_MMCIF_H__
	16
487d9fc5 MD	17	#include <linux/platform_device.h>
	18	#include <linux/io.h>
	19
fdc50a94 YG	20	/*
	21	* MMCIF : CE_CLK_CTRL [19:16]
	22	* 1000 : Peripheral clock / 512
	23	* 0111 : Peripheral clock / 256
	24	* 0110 : Peripheral clock / 128
	25	* 0101 : Peripheral clock / 64
	26	* 0100 : Peripheral clock / 32
	27	* 0011 : Peripheral clock / 16
	28	* 0010 : Peripheral clock / 8
	29	* 0001 : Peripheral clock / 4
	30	* 0000 : Peripheral clock / 2
	31	* 1111 : Peripheral clock (sup_pclk set '1')
	32	*/
	33
	34	struct sh_mmcif_plat_data {
	35	void (set_pwr)(struct platform_device pdev, int state);
	36	void (down_pwr)(struct platform_device pdev);
777271d0	37	int (get_cd)(struct platform_device pdef);
fdc50a94 YG	38	u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */
	39	unsigned long caps;
	40	u32 ocr;
	41	};
	42
487d9fc5 MD	43	#define MMCIF_CE_CMD_SET 0x00000000
	44	#define MMCIF_CE_ARG 0x00000008
	45	#define MMCIF_CE_ARG_CMD12 0x0000000C
	46	#define MMCIF_CE_CMD_CTRL 0x00000010
	47	#define MMCIF_CE_BLOCK_SET 0x00000014
	48	#define MMCIF_CE_CLK_CTRL 0x00000018
	49	#define MMCIF_CE_BUF_ACC 0x0000001C
	50	#define MMCIF_CE_RESP3 0x00000020
	51	#define MMCIF_CE_RESP2 0x00000024
	52	#define MMCIF_CE_RESP1 0x00000028
	53	#define MMCIF_CE_RESP0 0x0000002C
	54	#define MMCIF_CE_RESP_CMD12 0x00000030
	55	#define MMCIF_CE_DATA 0x00000034
	56	#define MMCIF_CE_INT 0x00000040
	57	#define MMCIF_CE_INT_MASK 0x00000044
	58	#define MMCIF_CE_HOST_STS1 0x00000048
	59	#define MMCIF_CE_HOST_STS2 0x0000004C
	60	#define MMCIF_CE_VERSION 0x0000007C
	61
da1d39e3 SH	62	/* CE_BUF_ACC */
	63	#define BUF_ACC_DMAWEN (1 << 25)
	64	#define BUF_ACC_DMAREN (1 << 24)
	65	#define BUF_ACC_BUSW_32 (0 << 17)
	66	#define BUF_ACC_BUSW_16 (1 << 17)
	67	#define BUF_ACC_ATYP (1 << 16)
	68
	69	/* CE_CLK_CTRL */
	70	#define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
	71	#define CLK_CLEAR ((1 << 19) \| (1 << 18) \| (1 << 17) \| (1 << 16))
	72	#define CLK_SUP_PCLK ((1 << 19) \| (1 << 18) \| (1 << 17) \| (1 << 16))
22efa0fe SH	73	#define CLKDIV_4 (1<<16) /* mmc clock frequency.
	74	* n: bus clock/(2^(n+1)) */
	75	#define CLKDIV_256 (7<<16) /* mmc clock frequency. (see above) */
da1d39e3 SH	76	#define SRSPTO_256 ((1 << 13) \| (0 << 12)) /* resp timeout */
	77	#define SRBSYTO_29 ((1 << 11) \| (1 << 10) \| \
	78	(1 << 9) \| (1 << 8)) /* resp busy timeout */
	79	#define SRWDTO_29 ((1 << 7) \| (1 << 6) \| \
	80	(1 << 5) \| (1 << 4)) /* read/write timeout */
	81	#define SCCSTO_29 ((1 << 3) \| (1 << 2) \| \
	82	(1 << 1) \| (1 << 0)) /* ccs timeout */
	83
	84	/* CE_VERSION */
	85	#define SOFT_RST_ON (1 << 31)
1ae0affe	86	#define SOFT_RST_OFF 0
da1d39e3	87
2f6ba579	88	static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
487d9fc5 MD	89	{
	90	return readl(addr + reg);
	91	}
	92
2f6ba579	93	static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
487d9fc5 MD	94	{
	95	writel(val, addr + reg);
	96	}
	97
8a768952 MD	98	#define SH_MMCIF_BBS 512 /* boot block size */
8a768952 MD	99
9f843706 SH	100	enum { MMCIF_PROGRESS_ENTER, MMCIF_PROGRESS_INIT,
	101	MMCIF_PROGRESS_LOAD, MMCIF_PROGRESS_DONE };
	102
2f6ba579	103	static inline void sh_mmcif_boot_cmd_send(void __iomem *base,
8a768952 MD	104	unsigned long cmd, unsigned long arg)
	105	{
	106	sh_mmcif_writel(base, MMCIF_CE_INT, 0);
	107	sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
	108	sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
	109	}
	110
2f6ba579	111	static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
8a768952 MD	112	{
	113	unsigned long tmp;
	114	int cnt;
	115
	116	for (cnt = 0; cnt < 1000000; cnt++) {
	117	tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
	118	if (tmp & mask) {
	119	sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
	120	return 0;
	121	}
	122	}
	123
	124	return -1;
	125	}
	126
2f6ba579	127	static inline int sh_mmcif_boot_cmd(void __iomem *base,
8a768952 MD	128	unsigned long cmd, unsigned long arg)
	129	{
	130	sh_mmcif_boot_cmd_send(base, cmd, arg);
	131	return sh_mmcif_boot_cmd_poll(base, 0x00010000);
	132	}
	133
2f6ba579	134	static inline int sh_mmcif_boot_do_read_single(void __iomem *base,
8a768952 MD	135	unsigned int block_nr,
	136	unsigned long *buf)
	137	{
	138	int k;
	139
	140	/* CMD13 - Status */
	141	sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);
	142
	143	if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)
	144	return -1;
	145
	146	/* CMD17 - Read */
	147	sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);
	148	if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)
	149	return -1;
	150
	151	for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
	152	buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);
	153
	154	return 0;
	155	}
	156
2f6ba579	157	static inline int sh_mmcif_boot_do_read(void __iomem *base,
8a768952 MD	158	unsigned long first_block,
	159	unsigned long nr_blocks,
	160	void *buf)
	161	{
	162	unsigned long k;
	163	int ret = 0;
	164
	165	/* CMD16 - Set the block size */
	166	sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);
	167
	168	for (k = 0; !ret && k < nr_blocks; k++)
	169	ret = sh_mmcif_boot_do_read_single(base, first_block + k,
	170	buf + (k * SH_MMCIF_BBS));
	171
	172	return ret;
	173	}
	174
2f6ba579	175	static inline void sh_mmcif_boot_init(void __iomem *base)
8a768952	176	{
8a768952	177	/* reset */
1ae0affe SH	178	sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);
1ae0affe SH	179	sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);
8a768952 MD	180
8a768952 MD	181	/* byte swap */
da1d39e3	182	sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
8a768952 MD	183
	184	/* Set block size in MMCIF hardware */
	185	sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
	186
22efa0fe	187	/* Enable the clock, set it to Bus clock/256 (about 325Khz). */
da1d39e3	188	sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
22efa0fe SH	189	CLK_ENABLE \| CLKDIV_256 \| SRSPTO_256 \|
22efa0fe SH	190	SRBSYTO_29 \| SRWDTO_29 \| SCCSTO_29);
8a768952 MD	191
	192	/* CMD0 */
	193	sh_mmcif_boot_cmd(base, 0x00000040, 0);
	194
	195	/* CMD1 - Get OCR */
	196	do {
	197	sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */
	198	} while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)
	199	!= 0x80000000);
	200
	201	/* CMD2 - Get CID */
	202	sh_mmcif_boot_cmd(base, 0x02806040, 0);
	203
	204	/* CMD3 - Set card relative address */
	205	sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
	206	}
	207
2f6ba579	208	static inline void sh_mmcif_boot_slurp(void __iomem *base,
8a768952 MD	209	unsigned char *buf,
	210	unsigned long no_bytes)
	211	{
	212	unsigned long tmp;
	213
	214	/* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
22efa0fe SH	215	sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
	216	CLK_ENABLE \| CLKDIV_4 \| SRSPTO_256 \|
	217	SRBSYTO_29 \| SRWDTO_29 \| SCCSTO_29);
8a768952 MD	218
	219	/* CMD9 - Get CSD */
	220	sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
	221
	222	/* CMD7 - Select the card */
	223	sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
	224
	225	tmp = no_bytes / SH_MMCIF_BBS;
	226	tmp += (no_bytes % SH_MMCIF_BBS) ? 1 : 0;
	227
	228	sh_mmcif_boot_do_read(base, 512, tmp, buf);
	229	}
	230
fdc50a94	231	#endif /* __SH_MMCIF_H__ */