[deliverable/linux.git] / include / linux / mtd / fsmc.h

/*
 * incude/mtd/fsmc.h
 *
 * ST Microelectronics
 * Flexible Static Memory Controller (FSMC)
 * platform data interface and header file
 *
 * Copyright © 2010 ST Microelectronics
 * Vipin Kumar <vipin.kumar@st.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#ifndef __MTD_FSMC_H
#define __MTD_FSMC_H

#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/types.h>
#include <linux/mtd/partitions.h>
#include <asm/param.h>

#define FSMC_NAND_BW8		1
#define FSMC_NAND_BW16		2

#define FSMC_MAX_NOR_BANKS	4
#define FSMC_MAX_NAND_BANKS	4

#define FSMC_FLASH_WIDTH8	1
#define FSMC_FLASH_WIDTH16	2

struct fsmc_nor_bank_regs {
	uint32_t ctrl;
	uint32_t ctrl_tim;
};

/* ctrl register definitions */
#define BANK_ENABLE		(1 << 0)
#define MUXED			(1 << 1)
#define NOR_DEV			(2 << 2)
#define WIDTH_8			(0 << 4)
#define WIDTH_16		(1 << 4)
#define RSTPWRDWN		(1 << 6)
#define WPROT			(1 << 7)
#define WRT_ENABLE		(1 << 12)
#define WAIT_ENB		(1 << 13)

/* ctrl_tim register definitions */

struct fsmc_nand_bank_regs {
	uint32_t pc;
	uint32_t sts;
	uint32_t comm;
	uint32_t attrib;
	uint32_t ioata;
	uint32_t ecc1;
	uint32_t ecc2;
	uint32_t ecc3;
};

#define FSMC_NOR_REG_SIZE	0x40

struct fsmc_regs {
	struct fsmc_nor_bank_regs nor_bank_regs[FSMC_MAX_NOR_BANKS];
	uint8_t reserved_1[0x40 - 0x20];
	struct fsmc_nand_bank_regs bank_regs[FSMC_MAX_NAND_BANKS];
	uint8_t reserved_2[0xfe0 - 0xc0];
	uint32_t peripid0;			/* 0xfe0 */
	uint32_t peripid1;			/* 0xfe4 */
	uint32_t peripid2;			/* 0xfe8 */
	uint32_t peripid3;			/* 0xfec */
	uint32_t pcellid0;			/* 0xff0 */
	uint32_t pcellid1;			/* 0xff4 */
	uint32_t pcellid2;			/* 0xff8 */
	uint32_t pcellid3;			/* 0xffc */
};

#define FSMC_BUSY_WAIT_TIMEOUT	(1 * HZ)

/* pc register definitions */
#define FSMC_RESET		(1 << 0)
#define FSMC_WAITON		(1 << 1)
#define FSMC_ENABLE		(1 << 2)
#define FSMC_DEVTYPE_NAND	(1 << 3)
#define FSMC_DEVWID_8		(0 << 4)
#define FSMC_DEVWID_16		(1 << 4)
#define FSMC_ECCEN		(1 << 6)
#define FSMC_ECCPLEN_512	(0 << 7)
#define FSMC_ECCPLEN_256	(1 << 7)
#define FSMC_TCLR_1		(1)
#define FSMC_TCLR_SHIFT		(9)
#define FSMC_TCLR_MASK		(0xF)
#define FSMC_TAR_1		(1)
#define FSMC_TAR_SHIFT		(13)
#define FSMC_TAR_MASK		(0xF)

/* sts register definitions */
#define FSMC_CODE_RDY		(1 << 15)

/* comm register definitions */
#define FSMC_TSET_0		0
#define FSMC_TSET_SHIFT		0
#define FSMC_TSET_MASK		0xFF
#define FSMC_TWAIT_6		6
#define FSMC_TWAIT_SHIFT	8
#define FSMC_TWAIT_MASK		0xFF
#define FSMC_THOLD_4		4
#define FSMC_THOLD_SHIFT	16
#define FSMC_THOLD_MASK		0xFF
#define FSMC_THIZ_1		1
#define FSMC_THIZ_SHIFT		24
#define FSMC_THIZ_MASK		0xFF

/*
 * There are 13 bytes of ecc for every 512 byte block in FSMC version 8
 * and it has to be read consecutively and immediately after the 512
 * byte data block for hardware to generate the error bit offsets
 * Managing the ecc bytes in the following way is easier. This way is
 * similar to oobfree structure maintained already in u-boot nand driver
 */
#define MAX_ECCPLACE_ENTRIES	32

struct fsmc_nand_eccplace {
	uint8_t offset;
	uint8_t length;
};

struct fsmc_eccplace {
	struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES];
};

struct fsmc_nand_timings {
	uint8_t tclr;
	uint8_t tar;
	uint8_t thiz;
	uint8_t thold;
	uint8_t twait;
	uint8_t tset;
};

enum access_mode {
	USE_DMA_ACCESS = 1,
	USE_WORD_ACCESS,
};

/**
 * fsmc_nand_platform_data - platform specific NAND controller config
 * @partitions: partition table for the platform, use a default fallback
 * if this is NULL
 * @nr_partitions: the number of partitions in the previous entry
 * @options: different options for the driver
 * @width: bus width
 * @bank: default bank
 * @select_bank: callback to select a certain bank, this is
 * platform-specific. If the controller only supports one bank
 * this may be set to NULL
 */
struct fsmc_nand_platform_data {
	struct fsmc_nand_timings *nand_timings;
	struct mtd_partition	*partitions;
	unsigned int		nr_partitions;
	unsigned int		options;
	unsigned int		width;
	unsigned int		bank;

	/* CLE, ALE offsets */
	unsigned long           cle_off;
	unsigned long           ale_off;
	enum access_mode	mode;

	void			(*select_bank)(uint32_t bank, uint32_t busw);
};

extern int __init fsmc_nor_init(struct platform_device *pdev,
		unsigned long base, uint32_t bank, uint32_t width);
extern void __init fsmc_init_board_info(struct platform_device *pdev,
		struct mtd_partition *partitions, unsigned int nr_partitions,
		unsigned int width);

#endif /* __MTD_FSMC_H */
Commit	Line	Data
6c009ab8 LW	1	/*
	2	* incude/mtd/fsmc.h
	3	*
	4	* ST Microelectronics
	5	* Flexible Static Memory Controller (FSMC)
	6	* platform data interface and header file
	7	*
	8	* Copyright © 2010 ST Microelectronics
	9	* Vipin Kumar <vipin.kumar@st.com>
	10	*
	11	* This file is licensed under the terms of the GNU General Public
	12	* License version 2. This program is licensed "as is" without any
	13	* warranty of any kind, whether express or implied.
	14	*/
	15
	16	#ifndef __MTD_FSMC_H
	17	#define __MTD_FSMC_H
	18
65ab220c	19	#include <linux/io.h>
6c009ab8 LW	20	#include <linux/platform_device.h>
	21	#include <linux/mtd/physmap.h>
	22	#include <linux/types.h>
	23	#include <linux/mtd/partitions.h>
	24	#include <asm/param.h>
	25
	26	#define FSMC_NAND_BW8 1
	27	#define FSMC_NAND_BW16 2
	28
6c009ab8 LW	29	#define FSMC_MAX_NOR_BANKS 4
	30	#define FSMC_MAX_NAND_BANKS 4
	31
	32	#define FSMC_FLASH_WIDTH8 1
	33	#define FSMC_FLASH_WIDTH16 2
	34
	35	struct fsmc_nor_bank_regs {
	36	uint32_t ctrl;
	37	uint32_t ctrl_tim;
	38	};
	39
	40	/* ctrl register definitions */
	41	#define BANK_ENABLE (1 << 0)
	42	#define MUXED (1 << 1)
	43	#define NOR_DEV (2 << 2)
	44	#define WIDTH_8 (0 << 4)
	45	#define WIDTH_16 (1 << 4)
	46	#define RSTPWRDWN (1 << 6)
	47	#define WPROT (1 << 7)
	48	#define WRT_ENABLE (1 << 12)
	49	#define WAIT_ENB (1 << 13)
	50
	51	/* ctrl_tim register definitions */
	52
b5602e86	53	struct fsmc_nand_bank_regs {
6c009ab8 LW	54	uint32_t pc;
	55	uint32_t sts;
	56	uint32_t comm;
	57	uint32_t attrib;
	58	uint32_t ioata;
	59	uint32_t ecc1;
	60	uint32_t ecc2;
	61	uint32_t ecc3;
	62	};
	63
	64	#define FSMC_NOR_REG_SIZE 0x40
	65
	66	struct fsmc_regs {
	67	struct fsmc_nor_bank_regs nor_bank_regs[FSMC_MAX_NOR_BANKS];
	68	uint8_t reserved_1[0x40 - 0x20];
b5602e86	69	struct fsmc_nand_bank_regs bank_regs[FSMC_MAX_NAND_BANKS];
6c009ab8 LW	70	uint8_t reserved_2[0xfe0 - 0xc0];
	71	uint32_t peripid0; /* 0xfe0 */
	72	uint32_t peripid1; /* 0xfe4 */
	73	uint32_t peripid2; /* 0xfe8 */
	74	uint32_t peripid3; /* 0xfec */
	75	uint32_t pcellid0; /* 0xff0 */
	76	uint32_t pcellid1; /* 0xff4 */
	77	uint32_t pcellid2; /* 0xff8 */
	78	uint32_t pcellid3; /* 0xffc */
	79	};
	80
	81	#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
	82
	83	/* pc register definitions */
	84	#define FSMC_RESET (1 << 0)
	85	#define FSMC_WAITON (1 << 1)
	86	#define FSMC_ENABLE (1 << 2)
	87	#define FSMC_DEVTYPE_NAND (1 << 3)
	88	#define FSMC_DEVWID_8 (0 << 4)
	89	#define FSMC_DEVWID_16 (1 << 4)
	90	#define FSMC_ECCEN (1 << 6)
	91	#define FSMC_ECCPLEN_512 (0 << 7)
	92	#define FSMC_ECCPLEN_256 (1 << 7)
e2f6bce8 VK	93	#define FSMC_TCLR_1 (1)
	94	#define FSMC_TCLR_SHIFT (9)
	95	#define FSMC_TCLR_MASK (0xF)
	96	#define FSMC_TAR_1 (1)
	97	#define FSMC_TAR_SHIFT (13)
	98	#define FSMC_TAR_MASK (0xF)
6c009ab8 LW	99
	100	/* sts register definitions */
	101	#define FSMC_CODE_RDY (1 << 15)
	102
	103	/* comm register definitions */
e2f6bce8 VK	104	#define FSMC_TSET_0 0
	105	#define FSMC_TSET_SHIFT 0
	106	#define FSMC_TSET_MASK 0xFF
	107	#define FSMC_TWAIT_6 6
	108	#define FSMC_TWAIT_SHIFT 8
	109	#define FSMC_TWAIT_MASK 0xFF
	110	#define FSMC_THOLD_4 4
	111	#define FSMC_THOLD_SHIFT 16
	112	#define FSMC_THOLD_MASK 0xFF
	113	#define FSMC_THIZ_1 1
	114	#define FSMC_THIZ_SHIFT 24
	115	#define FSMC_THIZ_MASK 0xFF
6c009ab8	116
6c009ab8 LW	117	/*
	118	* There are 13 bytes of ecc for every 512 byte block in FSMC version 8
	119	* and it has to be read consecutively and immediately after the 512
	120	* byte data block for hardware to generate the error bit offsets
	121	* Managing the ecc bytes in the following way is easier. This way is
	122	* similar to oobfree structure maintained already in u-boot nand driver
	123	*/
	124	#define MAX_ECCPLACE_ENTRIES 32
	125
	126	struct fsmc_nand_eccplace {
	127	uint8_t offset;
	128	uint8_t length;
	129	};
	130
	131	struct fsmc_eccplace {
	132	struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES];
	133	};
	134
e2f6bce8 VK	135	struct fsmc_nand_timings {
	136	uint8_t tclr;
	137	uint8_t tar;
	138	uint8_t thiz;
	139	uint8_t thold;
	140	uint8_t twait;
	141	uint8_t tset;
	142	};
	143
604e7544 VK	144	enum access_mode {
	145	USE_DMA_ACCESS = 1,
	146	USE_WORD_ACCESS,
	147	};
	148
6c009ab8 LW	149	/**
	150	* fsmc_nand_platform_data - platform specific NAND controller config
	151	* @partitions: partition table for the platform, use a default fallback
	152	* if this is NULL
	153	* @nr_partitions: the number of partitions in the previous entry
	154	* @options: different options for the driver
	155	* @width: bus width
	156	* @bank: default bank
	157	* @select_bank: callback to select a certain bank, this is
	158	* platform-specific. If the controller only supports one bank
	159	* this may be set to NULL
	160	*/
	161	struct fsmc_nand_platform_data {
e2f6bce8	162	struct fsmc_nand_timings *nand_timings;
6c009ab8 LW	163	struct mtd_partition *partitions;
	164	unsigned int nr_partitions;
	165	unsigned int options;
	166	unsigned int width;
	167	unsigned int bank;
b2acc92e SH	168
	169	/* CLE, ALE offsets */
	170	unsigned long cle_off;
	171	unsigned long ale_off;
604e7544	172	enum access_mode mode;
b2acc92e	173
6c009ab8 LW	174	void (*select_bank)(uint32_t bank, uint32_t busw);
	175	};
	176
	177	extern int __init fsmc_nor_init(struct platform_device *pdev,
	178	unsigned long base, uint32_t bank, uint32_t width);
	179	extern void __init fsmc_init_board_info(struct platform_device *pdev,
	180	struct mtd_partition *partitions, unsigned int nr_partitions,
	181	unsigned int width);
	182
	183	#endif /* __MTD_FSMC_H */