[deliverable/linux.git] / include / linux / mtd / fsmc.h

/*
 * incude/mtd/fsmc.h
 *
 * ST Microelectronics
 * Flexible Static Memory Controller (FSMC)
 * platform data interface and header file
 *
 * Copyright © 2010 ST Microelectronics
 * Vipin Kumar <vipin.kumar@st.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#ifndef __MTD_FSMC_H
#define __MTD_FSMC_H

#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/types.h>
#include <linux/mtd/partitions.h>
#include <asm/param.h>

#define FSMC_NAND_BW8		1
#define FSMC_NAND_BW16		2

/*
 * The placement of the Command Latch Enable (CLE) and
 * Address Latch Enable (ALE) is twised around in the
 * SPEAR310 implementation.
 */
#if defined(CONFIG_MACH_SPEAR310)
#define PLAT_NAND_CLE		(1 << 17)
#define PLAT_NAND_ALE		(1 << 16)
#else
#define PLAT_NAND_CLE		(1 << 16)
#define PLAT_NAND_ALE		(1 << 17)
#endif

#define FSMC_MAX_NOR_BANKS	4
#define FSMC_MAX_NAND_BANKS	4

#define FSMC_FLASH_WIDTH8	1
#define FSMC_FLASH_WIDTH16	2

struct fsmc_nor_bank_regs {
	uint32_t ctrl;
	uint32_t ctrl_tim;
};

/* ctrl register definitions */
#define BANK_ENABLE		(1 << 0)
#define MUXED			(1 << 1)
#define NOR_DEV			(2 << 2)
#define WIDTH_8			(0 << 4)
#define WIDTH_16		(1 << 4)
#define RSTPWRDWN		(1 << 6)
#define WPROT			(1 << 7)
#define WRT_ENABLE		(1 << 12)
#define WAIT_ENB		(1 << 13)

/* ctrl_tim register definitions */

struct fsms_nand_bank_regs {
	uint32_t pc;
	uint32_t sts;
	uint32_t comm;
	uint32_t attrib;
	uint32_t ioata;
	uint32_t ecc1;
	uint32_t ecc2;
	uint32_t ecc3;
};

#define FSMC_NOR_REG_SIZE	0x40

struct fsmc_regs {
	struct fsmc_nor_bank_regs nor_bank_regs[FSMC_MAX_NOR_BANKS];
	uint8_t reserved_1[0x40 - 0x20];
	struct fsms_nand_bank_regs bank_regs[FSMC_MAX_NAND_BANKS];
	uint8_t reserved_2[0xfe0 - 0xc0];
	uint32_t peripid0;			/* 0xfe0 */
	uint32_t peripid1;			/* 0xfe4 */
	uint32_t peripid2;			/* 0xfe8 */
	uint32_t peripid3;			/* 0xfec */
	uint32_t pcellid0;			/* 0xff0 */
	uint32_t pcellid1;			/* 0xff4 */
	uint32_t pcellid2;			/* 0xff8 */
	uint32_t pcellid3;			/* 0xffc */
};

#define FSMC_BUSY_WAIT_TIMEOUT	(1 * HZ)

/* pc register definitions */
#define FSMC_RESET		(1 << 0)
#define FSMC_WAITON		(1 << 1)
#define FSMC_ENABLE		(1 << 2)
#define FSMC_DEVTYPE_NAND	(1 << 3)
#define FSMC_DEVWID_8		(0 << 4)
#define FSMC_DEVWID_16		(1 << 4)
#define FSMC_ECCEN		(1 << 6)
#define FSMC_ECCPLEN_512	(0 << 7)
#define FSMC_ECCPLEN_256	(1 << 7)
#define FSMC_TCLR_1		(1 << 9)
#define FSMC_TAR_1		(1 << 13)

/* sts register definitions */
#define FSMC_CODE_RDY		(1 << 15)

/* comm register definitions */
#define FSMC_TSET_0		(0 << 0)
#define FSMC_TWAIT_6		(6 << 8)
#define FSMC_THOLD_4		(4 << 16)
#define FSMC_THIZ_1		(1 << 24)

/* peripid2 register definitions */
#define FSMC_REVISION_MSK	(0xf)
#define FSMC_REVISION_SHFT	(0x4)

#define FSMC_VER1		1
#define FSMC_VER2		2
#define FSMC_VER3		3
#define FSMC_VER4		4
#define FSMC_VER5		5
#define FSMC_VER6		6
#define FSMC_VER7		7
#define FSMC_VER8		8

static inline uint32_t get_fsmc_version(struct fsmc_regs *regs)
{
	return (readl(&regs->peripid2) >> FSMC_REVISION_SHFT) &
				FSMC_REVISION_MSK;
}

/*
 * There are 13 bytes of ecc for every 512 byte block in FSMC version 8
 * and it has to be read consecutively and immediately after the 512
 * byte data block for hardware to generate the error bit offsets
 * Managing the ecc bytes in the following way is easier. This way is
 * similar to oobfree structure maintained already in u-boot nand driver
 */
#define MAX_ECCPLACE_ENTRIES	32

struct fsmc_nand_eccplace {
	uint8_t offset;
	uint8_t length;
};

struct fsmc_eccplace {
	struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES];
};

/**
 * fsmc_nand_platform_data - platform specific NAND controller config
 * @partitions: partition table for the platform, use a default fallback
 * if this is NULL
 * @nr_partitions: the number of partitions in the previous entry
 * @options: different options for the driver
 * @width: bus width
 * @bank: default bank
 * @select_bank: callback to select a certain bank, this is
 * platform-specific. If the controller only supports one bank
 * this may be set to NULL
 */
struct fsmc_nand_platform_data {
	struct mtd_partition	*partitions;
	unsigned int		nr_partitions;
	unsigned int		options;
	unsigned int		width;
	unsigned int		bank;
	void			(*select_bank)(uint32_t bank, uint32_t busw);
};

extern int __init fsmc_nor_init(struct platform_device *pdev,
		unsigned long base, uint32_t bank, uint32_t width);
extern void __init fsmc_init_board_info(struct platform_device *pdev,
		struct mtd_partition *partitions, unsigned int nr_partitions,
		unsigned int width);

#endif /* __MTD_FSMC_H */
Commit	Line	Data
6c009ab8 LW	1	/*
	2	* incude/mtd/fsmc.h
	3	*
	4	* ST Microelectronics
	5	* Flexible Static Memory Controller (FSMC)
	6	* platform data interface and header file
	7	*
	8	* Copyright © 2010 ST Microelectronics
	9	* Vipin Kumar <vipin.kumar@st.com>
	10	*
	11	* This file is licensed under the terms of the GNU General Public
	12	* License version 2. This program is licensed "as is" without any
	13	* warranty of any kind, whether express or implied.
	14	*/
	15
	16	#ifndef __MTD_FSMC_H
	17	#define __MTD_FSMC_H
	18
	19	#include <linux/platform_device.h>
	20	#include <linux/mtd/physmap.h>
	21	#include <linux/types.h>
	22	#include <linux/mtd/partitions.h>
	23	#include <asm/param.h>
	24
	25	#define FSMC_NAND_BW8 1
	26	#define FSMC_NAND_BW16 2
	27
	28	/*
	29	* The placement of the Command Latch Enable (CLE) and
	30	* Address Latch Enable (ALE) is twised around in the
	31	* SPEAR310 implementation.
	32	*/
	33	#if defined(CONFIG_MACH_SPEAR310)
	34	#define PLAT_NAND_CLE (1 << 17)
	35	#define PLAT_NAND_ALE (1 << 16)
	36	#else
	37	#define PLAT_NAND_CLE (1 << 16)
	38	#define PLAT_NAND_ALE (1 << 17)
	39	#endif
	40
	41	#define FSMC_MAX_NOR_BANKS 4
	42	#define FSMC_MAX_NAND_BANKS 4
	43
	44	#define FSMC_FLASH_WIDTH8 1
	45	#define FSMC_FLASH_WIDTH16 2
	46
	47	struct fsmc_nor_bank_regs {
	48	uint32_t ctrl;
	49	uint32_t ctrl_tim;
	50	};
	51
	52	/* ctrl register definitions */
	53	#define BANK_ENABLE (1 << 0)
	54	#define MUXED (1 << 1)
	55	#define NOR_DEV (2 << 2)
	56	#define WIDTH_8 (0 << 4)
	57	#define WIDTH_16 (1 << 4)
	58	#define RSTPWRDWN (1 << 6)
	59	#define WPROT (1 << 7)
	60	#define WRT_ENABLE (1 << 12)
	61	#define WAIT_ENB (1 << 13)
	62
	63	/* ctrl_tim register definitions */
	64
65	struct fsms_nand_bank_regs {
66	uint32_t pc;
67	uint32_t sts;
68	uint32_t comm;
69	uint32_t attrib;
70	uint32_t ioata;
71	uint32_t ecc1;
72	uint32_t ecc2;
73	uint32_t ecc3;
74	};
75
76	#define FSMC_NOR_REG_SIZE 0x40
77
78	struct fsmc_regs {
79	struct fsmc_nor_bank_regs nor_bank_regs[FSMC_MAX_NOR_BANKS];
80	uint8_t reserved_1[0x40 - 0x20];
81	struct fsms_nand_bank_regs bank_regs[FSMC_MAX_NAND_BANKS];
82	uint8_t reserved_2[0xfe0 - 0xc0];
83	uint32_t peripid0; /* 0xfe0 */
84	uint32_t peripid1; /* 0xfe4 */
85	uint32_t peripid2; /* 0xfe8 */
86	uint32_t peripid3; /* 0xfec */
87	uint32_t pcellid0; /* 0xff0 */
88	uint32_t pcellid1; /* 0xff4 */
89	uint32_t pcellid2; /* 0xff8 */
90	uint32_t pcellid3; /* 0xffc */
91	};
92
93	#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
94
95	/* pc register definitions */
96	#define FSMC_RESET (1 << 0)
97	#define FSMC_WAITON (1 << 1)
98	#define FSMC_ENABLE (1 << 2)
99	#define FSMC_DEVTYPE_NAND (1 << 3)
100	#define FSMC_DEVWID_8 (0 << 4)
101	#define FSMC_DEVWID_16 (1 << 4)
102	#define FSMC_ECCEN (1 << 6)
103	#define FSMC_ECCPLEN_512 (0 << 7)
104	#define FSMC_ECCPLEN_256 (1 << 7)
105	#define FSMC_TCLR_1 (1 << 9)
106	#define FSMC_TAR_1 (1 << 13)
107
108	/* sts register definitions */
109	#define FSMC_CODE_RDY (1 << 15)
110
111	/* comm register definitions */
112	#define FSMC_TSET_0 (0 << 0)
113	#define FSMC_TWAIT_6 (6 << 8)
114	#define FSMC_THOLD_4 (4 << 16)
115	#define FSMC_THIZ_1 (1 << 24)
116
117	/* peripid2 register definitions */
118	#define FSMC_REVISION_MSK (0xf)
119	#define FSMC_REVISION_SHFT (0x4)
120
121	#define FSMC_VER1 1
122	#define FSMC_VER2 2
123	#define FSMC_VER3 3
124	#define FSMC_VER4 4
125	#define FSMC_VER5 5
126	#define FSMC_VER6 6
127	#define FSMC_VER7 7
128	#define FSMC_VER8 8
129
130	static inline uint32_t get_fsmc_version(struct fsmc_regs *regs)
131	{
132	return (readl(&regs->peripid2) >> FSMC_REVISION_SHFT) &
133	FSMC_REVISION_MSK;
134	}
135
136	/*
137	* There are 13 bytes of ecc for every 512 byte block in FSMC version 8
138	* and it has to be read consecutively and immediately after the 512
139	* byte data block for hardware to generate the error bit offsets
140	* Managing the ecc bytes in the following way is easier. This way is
141	* similar to oobfree structure maintained already in u-boot nand driver
142	*/
143	#define MAX_ECCPLACE_ENTRIES 32
144
145	struct fsmc_nand_eccplace {
146	uint8_t offset;
147	uint8_t length;
148	};
149
150	struct fsmc_eccplace {
151	struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES];
152	};
153
154	/**
155	* fsmc_nand_platform_data - platform specific NAND controller config
156	* @partitions: partition table for the platform, use a default fallback
157	* if this is NULL
158	* @nr_partitions: the number of partitions in the previous entry
159	* @options: different options for the driver
160	* @width: bus width
161	* @bank: default bank
162	* @select_bank: callback to select a certain bank, this is
163	* platform-specific. If the controller only supports one bank
164	* this may be set to NULL
165	*/
166	struct fsmc_nand_platform_data {
167	struct mtd_partition *partitions;
168	unsigned int nr_partitions;
169	unsigned int options;
170	unsigned int width;
171	unsigned int bank;
172	void (*select_bank)(uint32_t bank, uint32_t busw);
173	};
174
175	extern int __init fsmc_nor_init(struct platform_device *pdev,
176	unsigned long base, uint32_t bank, uint32_t width);
177	extern void __init fsmc_init_board_info(struct platform_device *pdev,
178	struct mtd_partition *partitions, unsigned int nr_partitions,
179	unsigned int width);
180
181	#endif /* __MTD_FSMC_H */