Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/include/linux/mtd/nand.h | |
3 | * | |
a1452a37 DW |
4 | * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> |
5 | * Steven J. Hill <sjhill@realitydiluted.com> | |
6 | * Thomas Gleixner <tglx@linutronix.de> | |
1da177e4 | 7 | * |
1da177e4 LT |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
2c0a2bed TG |
12 | * Info: |
13 | * Contains standard defines and IDs for NAND flash devices | |
1da177e4 | 14 | * |
2c0a2bed TG |
15 | * Changelog: |
16 | * See git changelog. | |
1da177e4 LT |
17 | */ |
18 | #ifndef __LINUX_MTD_NAND_H | |
19 | #define __LINUX_MTD_NAND_H | |
20 | ||
1da177e4 LT |
21 | #include <linux/wait.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/mtd/mtd.h> | |
30631cb8 | 24 | #include <linux/mtd/flashchip.h> |
c62d81bc | 25 | #include <linux/mtd/bbm.h> |
1da177e4 LT |
26 | |
27 | struct mtd_info; | |
5e81e88a | 28 | struct nand_flash_dev; |
1da177e4 | 29 | /* Scan and identify a NAND device */ |
a0491fc4 SAS |
30 | extern int nand_scan(struct mtd_info *mtd, int max_chips); |
31 | /* | |
32 | * Separate phases of nand_scan(), allowing board driver to intervene | |
33 | * and override command or ECC setup according to flash type. | |
34 | */ | |
5e81e88a DW |
35 | extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, |
36 | struct nand_flash_dev *table); | |
3b85c321 DW |
37 | extern int nand_scan_tail(struct mtd_info *mtd); |
38 | ||
1da177e4 | 39 | /* Free resources held by the NAND device */ |
a0491fc4 | 40 | extern void nand_release(struct mtd_info *mtd); |
1da177e4 | 41 | |
b77d95c7 DW |
42 | /* Internal helper for board drivers which need to override command function */ |
43 | extern void nand_wait_ready(struct mtd_info *mtd); | |
44 | ||
7854d3f7 | 45 | /* locks all blocks present in the device */ |
7d70f334 VS |
46 | extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); |
47 | ||
7854d3f7 | 48 | /* unlocks specified locked blocks */ |
7d70f334 VS |
49 | extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); |
50 | ||
1da177e4 LT |
51 | /* The maximum number of NAND chips in an array */ |
52 | #define NAND_MAX_CHIPS 8 | |
53 | ||
a0491fc4 SAS |
54 | /* |
55 | * This constant declares the max. oobsize / page, which | |
1da177e4 LT |
56 | * is supported now. If you add a chip with bigger oobsize/page |
57 | * adjust this accordingly. | |
58 | */ | |
52778b2e | 59 | #define NAND_MAX_OOBSIZE 744 |
5c709ee9 | 60 | #define NAND_MAX_PAGESIZE 8192 |
1da177e4 LT |
61 | |
62 | /* | |
63 | * Constants for hardware specific CLE/ALE/NCE function | |
7abd3ef9 TG |
64 | * |
65 | * These are bits which can be or'ed to set/clear multiple | |
66 | * bits in one go. | |
67 | */ | |
1da177e4 | 68 | /* Select the chip by setting nCE to low */ |
7abd3ef9 | 69 | #define NAND_NCE 0x01 |
1da177e4 | 70 | /* Select the command latch by setting CLE to high */ |
7abd3ef9 | 71 | #define NAND_CLE 0x02 |
1da177e4 | 72 | /* Select the address latch by setting ALE to high */ |
7abd3ef9 TG |
73 | #define NAND_ALE 0x04 |
74 | ||
75 | #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) | |
76 | #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) | |
77 | #define NAND_CTRL_CHANGE 0x80 | |
1da177e4 LT |
78 | |
79 | /* | |
80 | * Standard NAND flash commands | |
81 | */ | |
82 | #define NAND_CMD_READ0 0 | |
83 | #define NAND_CMD_READ1 1 | |
7bc3312b | 84 | #define NAND_CMD_RNDOUT 5 |
1da177e4 LT |
85 | #define NAND_CMD_PAGEPROG 0x10 |
86 | #define NAND_CMD_READOOB 0x50 | |
87 | #define NAND_CMD_ERASE1 0x60 | |
88 | #define NAND_CMD_STATUS 0x70 | |
1da177e4 | 89 | #define NAND_CMD_SEQIN 0x80 |
7bc3312b | 90 | #define NAND_CMD_RNDIN 0x85 |
1da177e4 LT |
91 | #define NAND_CMD_READID 0x90 |
92 | #define NAND_CMD_ERASE2 0xd0 | |
caa4b6f2 | 93 | #define NAND_CMD_PARAM 0xec |
7db03ecc HS |
94 | #define NAND_CMD_GET_FEATURES 0xee |
95 | #define NAND_CMD_SET_FEATURES 0xef | |
1da177e4 LT |
96 | #define NAND_CMD_RESET 0xff |
97 | ||
7d70f334 VS |
98 | #define NAND_CMD_LOCK 0x2a |
99 | #define NAND_CMD_UNLOCK1 0x23 | |
100 | #define NAND_CMD_UNLOCK2 0x24 | |
101 | ||
1da177e4 LT |
102 | /* Extended commands for large page devices */ |
103 | #define NAND_CMD_READSTART 0x30 | |
7bc3312b | 104 | #define NAND_CMD_RNDOUTSTART 0xE0 |
1da177e4 LT |
105 | #define NAND_CMD_CACHEDPROG 0x15 |
106 | ||
7abd3ef9 TG |
107 | #define NAND_CMD_NONE -1 |
108 | ||
1da177e4 LT |
109 | /* Status bits */ |
110 | #define NAND_STATUS_FAIL 0x01 | |
111 | #define NAND_STATUS_FAIL_N1 0x02 | |
112 | #define NAND_STATUS_TRUE_READY 0x20 | |
113 | #define NAND_STATUS_READY 0x40 | |
114 | #define NAND_STATUS_WP 0x80 | |
115 | ||
61ecfa87 | 116 | /* |
1da177e4 LT |
117 | * Constants for ECC_MODES |
118 | */ | |
6dfc6d25 TG |
119 | typedef enum { |
120 | NAND_ECC_NONE, | |
121 | NAND_ECC_SOFT, | |
122 | NAND_ECC_HW, | |
123 | NAND_ECC_HW_SYNDROME, | |
6e0cb135 | 124 | NAND_ECC_HW_OOB_FIRST, |
193bd400 | 125 | NAND_ECC_SOFT_BCH, |
6dfc6d25 | 126 | } nand_ecc_modes_t; |
1da177e4 LT |
127 | |
128 | /* | |
129 | * Constants for Hardware ECC | |
068e3c0a | 130 | */ |
1da177e4 LT |
131 | /* Reset Hardware ECC for read */ |
132 | #define NAND_ECC_READ 0 | |
133 | /* Reset Hardware ECC for write */ | |
134 | #define NAND_ECC_WRITE 1 | |
7854d3f7 | 135 | /* Enable Hardware ECC before syndrome is read back from flash */ |
1da177e4 LT |
136 | #define NAND_ECC_READSYN 2 |
137 | ||
068e3c0a DM |
138 | /* Bit mask for flags passed to do_nand_read_ecc */ |
139 | #define NAND_GET_DEVICE 0x80 | |
140 | ||
141 | ||
a0491fc4 SAS |
142 | /* |
143 | * Option constants for bizarre disfunctionality and real | |
144 | * features. | |
145 | */ | |
7854d3f7 | 146 | /* Buswidth is 16 bit */ |
1da177e4 | 147 | #define NAND_BUSWIDTH_16 0x00000002 |
1da177e4 LT |
148 | /* Chip has cache program function */ |
149 | #define NAND_CACHEPRG 0x00000008 | |
5bc7c33c BN |
150 | /* |
151 | * Chip requires ready check on read (for auto-incremented sequential read). | |
152 | * True only for small page devices; large page devices do not support | |
153 | * autoincrement. | |
154 | */ | |
155 | #define NAND_NEED_READRDY 0x00000100 | |
156 | ||
29072b96 TG |
157 | /* Chip does not allow subpage writes */ |
158 | #define NAND_NO_SUBPAGE_WRITE 0x00000200 | |
159 | ||
93edbad6 ML |
160 | /* Device is one of 'new' xD cards that expose fake nand command set */ |
161 | #define NAND_BROKEN_XD 0x00000400 | |
162 | ||
163 | /* Device behaves just like nand, but is readonly */ | |
164 | #define NAND_ROM 0x00000800 | |
165 | ||
a5ff4f10 JW |
166 | /* Device supports subpage reads */ |
167 | #define NAND_SUBPAGE_READ 0x00001000 | |
168 | ||
1da177e4 | 169 | /* Options valid for Samsung large page devices */ |
3239a6cd | 170 | #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG |
1da177e4 LT |
171 | |
172 | /* Macros to identify the above */ | |
1da177e4 | 173 | #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) |
a5ff4f10 | 174 | #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) |
1da177e4 | 175 | |
1da177e4 | 176 | /* Non chip related options */ |
0040bf38 | 177 | /* This option skips the bbt scan during initialization. */ |
b4dc53e1 | 178 | #define NAND_SKIP_BBTSCAN 0x00010000 |
a0491fc4 SAS |
179 | /* |
180 | * This option is defined if the board driver allocates its own buffers | |
181 | * (e.g. because it needs them DMA-coherent). | |
182 | */ | |
b4dc53e1 | 183 | #define NAND_OWN_BUFFERS 0x00020000 |
b1c6e6db | 184 | /* Chip may not exist, so silence any errors in scan */ |
b4dc53e1 | 185 | #define NAND_SCAN_SILENT_NODEV 0x00040000 |
64b37b2a MC |
186 | /* |
187 | * Autodetect nand buswidth with readid/onfi. | |
188 | * This suppose the driver will configure the hardware in 8 bits mode | |
189 | * when calling nand_scan_ident, and update its configuration | |
190 | * before calling nand_scan_tail. | |
191 | */ | |
192 | #define NAND_BUSWIDTH_AUTO 0x00080000 | |
b1c6e6db | 193 | |
1da177e4 | 194 | /* Options set by nand scan */ |
a36ed299 | 195 | /* Nand scan has allocated controller struct */ |
f75e5097 | 196 | #define NAND_CONTROLLER_ALLOC 0x80000000 |
1da177e4 | 197 | |
29072b96 TG |
198 | /* Cell info constants */ |
199 | #define NAND_CI_CHIPNR_MSK 0x03 | |
200 | #define NAND_CI_CELLTYPE_MSK 0x0C | |
7db906b7 | 201 | #define NAND_CI_CELLTYPE_SHIFT 2 |
1da177e4 | 202 | |
1da177e4 LT |
203 | /* Keep gcc happy */ |
204 | struct nand_chip; | |
205 | ||
5b40db68 HS |
206 | /* ONFI features */ |
207 | #define ONFI_FEATURE_16_BIT_BUS (1 << 0) | |
208 | #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) | |
209 | ||
3e70192c HS |
210 | /* ONFI timing mode, used in both asynchronous and synchronous mode */ |
211 | #define ONFI_TIMING_MODE_0 (1 << 0) | |
212 | #define ONFI_TIMING_MODE_1 (1 << 1) | |
213 | #define ONFI_TIMING_MODE_2 (1 << 2) | |
214 | #define ONFI_TIMING_MODE_3 (1 << 3) | |
215 | #define ONFI_TIMING_MODE_4 (1 << 4) | |
216 | #define ONFI_TIMING_MODE_5 (1 << 5) | |
217 | #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) | |
218 | ||
7db03ecc HS |
219 | /* ONFI feature address */ |
220 | #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 | |
221 | ||
8429bb39 BN |
222 | /* Vendor-specific feature address (Micron) */ |
223 | #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 | |
224 | ||
7db03ecc HS |
225 | /* ONFI subfeature parameters length */ |
226 | #define ONFI_SUBFEATURE_PARAM_LEN 4 | |
227 | ||
d914c932 DM |
228 | /* ONFI optional commands SET/GET FEATURES supported? */ |
229 | #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) | |
230 | ||
d1e1f4e4 FF |
231 | struct nand_onfi_params { |
232 | /* rev info and features block */ | |
b46daf7e SAS |
233 | /* 'O' 'N' 'F' 'I' */ |
234 | u8 sig[4]; | |
235 | __le16 revision; | |
236 | __le16 features; | |
237 | __le16 opt_cmd; | |
5138a98f HS |
238 | u8 reserved0[2]; |
239 | __le16 ext_param_page_length; /* since ONFI 2.1 */ | |
240 | u8 num_of_param_pages; /* since ONFI 2.1 */ | |
241 | u8 reserved1[17]; | |
d1e1f4e4 FF |
242 | |
243 | /* manufacturer information block */ | |
b46daf7e SAS |
244 | char manufacturer[12]; |
245 | char model[20]; | |
246 | u8 jedec_id; | |
247 | __le16 date_code; | |
248 | u8 reserved2[13]; | |
d1e1f4e4 FF |
249 | |
250 | /* memory organization block */ | |
b46daf7e SAS |
251 | __le32 byte_per_page; |
252 | __le16 spare_bytes_per_page; | |
253 | __le32 data_bytes_per_ppage; | |
254 | __le16 spare_bytes_per_ppage; | |
255 | __le32 pages_per_block; | |
256 | __le32 blocks_per_lun; | |
257 | u8 lun_count; | |
258 | u8 addr_cycles; | |
259 | u8 bits_per_cell; | |
260 | __le16 bb_per_lun; | |
261 | __le16 block_endurance; | |
262 | u8 guaranteed_good_blocks; | |
263 | __le16 guaranteed_block_endurance; | |
264 | u8 programs_per_page; | |
265 | u8 ppage_attr; | |
266 | u8 ecc_bits; | |
267 | u8 interleaved_bits; | |
268 | u8 interleaved_ops; | |
269 | u8 reserved3[13]; | |
d1e1f4e4 FF |
270 | |
271 | /* electrical parameter block */ | |
b46daf7e SAS |
272 | u8 io_pin_capacitance_max; |
273 | __le16 async_timing_mode; | |
274 | __le16 program_cache_timing_mode; | |
275 | __le16 t_prog; | |
276 | __le16 t_bers; | |
277 | __le16 t_r; | |
278 | __le16 t_ccs; | |
279 | __le16 src_sync_timing_mode; | |
280 | __le16 src_ssync_features; | |
281 | __le16 clk_pin_capacitance_typ; | |
282 | __le16 io_pin_capacitance_typ; | |
283 | __le16 input_pin_capacitance_typ; | |
284 | u8 input_pin_capacitance_max; | |
a55e85ce | 285 | u8 driver_strength_support; |
b46daf7e SAS |
286 | __le16 t_int_r; |
287 | __le16 t_ald; | |
288 | u8 reserved4[7]; | |
d1e1f4e4 FF |
289 | |
290 | /* vendor */ | |
6f0065b0 BN |
291 | __le16 vendor_revision; |
292 | u8 vendor[88]; | |
d1e1f4e4 FF |
293 | |
294 | __le16 crc; | |
e2e6b7b7 | 295 | } __packed; |
d1e1f4e4 FF |
296 | |
297 | #define ONFI_CRC_BASE 0x4F4E | |
298 | ||
5138a98f HS |
299 | /* Extended ECC information Block Definition (since ONFI 2.1) */ |
300 | struct onfi_ext_ecc_info { | |
301 | u8 ecc_bits; | |
302 | u8 codeword_size; | |
303 | __le16 bb_per_lun; | |
304 | __le16 block_endurance; | |
305 | u8 reserved[2]; | |
306 | } __packed; | |
307 | ||
308 | #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ | |
309 | #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ | |
310 | #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ | |
311 | struct onfi_ext_section { | |
312 | u8 type; | |
313 | u8 length; | |
314 | } __packed; | |
315 | ||
316 | #define ONFI_EXT_SECTION_MAX 8 | |
317 | ||
318 | /* Extended Parameter Page Definition (since ONFI 2.1) */ | |
319 | struct onfi_ext_param_page { | |
320 | __le16 crc; | |
321 | u8 sig[4]; /* 'E' 'P' 'P' 'S' */ | |
322 | u8 reserved0[10]; | |
323 | struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; | |
324 | ||
325 | /* | |
326 | * The actual size of the Extended Parameter Page is in | |
327 | * @ext_param_page_length of nand_onfi_params{}. | |
328 | * The following are the variable length sections. | |
329 | * So we do not add any fields below. Please see the ONFI spec. | |
330 | */ | |
331 | } __packed; | |
332 | ||
6f0065b0 BN |
333 | struct nand_onfi_vendor_micron { |
334 | u8 two_plane_read; | |
335 | u8 read_cache; | |
336 | u8 read_unique_id; | |
337 | u8 dq_imped; | |
338 | u8 dq_imped_num_settings; | |
339 | u8 dq_imped_feat_addr; | |
340 | u8 rb_pulldown_strength; | |
341 | u8 rb_pulldown_strength_feat_addr; | |
342 | u8 rb_pulldown_strength_num_settings; | |
343 | u8 otp_mode; | |
344 | u8 otp_page_start; | |
345 | u8 otp_data_prot_addr; | |
346 | u8 otp_num_pages; | |
347 | u8 otp_feat_addr; | |
348 | u8 read_retry_options; | |
349 | u8 reserved[72]; | |
350 | u8 param_revision; | |
351 | } __packed; | |
352 | ||
1da177e4 | 353 | /** |
844d3b42 | 354 | * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices |
61ecfa87 | 355 | * @lock: protection lock |
1da177e4 | 356 | * @active: the mtd device which holds the controller currently |
a0491fc4 SAS |
357 | * @wq: wait queue to sleep on if a NAND operation is in |
358 | * progress used instead of the per chip wait queue | |
359 | * when a hw controller is available. | |
1da177e4 LT |
360 | */ |
361 | struct nand_hw_control { | |
b46daf7e | 362 | spinlock_t lock; |
1da177e4 | 363 | struct nand_chip *active; |
0dfc6246 | 364 | wait_queue_head_t wq; |
1da177e4 LT |
365 | }; |
366 | ||
6dfc6d25 | 367 | /** |
7854d3f7 BN |
368 | * struct nand_ecc_ctrl - Control structure for ECC |
369 | * @mode: ECC mode | |
370 | * @steps: number of ECC steps per page | |
371 | * @size: data bytes per ECC step | |
372 | * @bytes: ECC bytes per step | |
1d0b95b0 | 373 | * @strength: max number of correctible bits per ECC step |
7854d3f7 BN |
374 | * @total: total number of ECC bytes per page |
375 | * @prepad: padding information for syndrome based ECC generators | |
376 | * @postpad: padding information for syndrome based ECC generators | |
844d3b42 | 377 | * @layout: ECC layout control struct pointer |
7854d3f7 BN |
378 | * @priv: pointer to private ECC control data |
379 | * @hwctl: function to control hardware ECC generator. Must only | |
6dfc6d25 | 380 | * be provided if an hardware ECC is available |
7854d3f7 BN |
381 | * @calculate: function for ECC calculation or readback from ECC hardware |
382 | * @correct: function for ECC correction, matching to ECC generator (sw/hw) | |
956e944c DW |
383 | * @read_page_raw: function to read a raw page without ECC |
384 | * @write_page_raw: function to write a raw page without ECC | |
7854d3f7 | 385 | * @read_page: function to read a page according to the ECC generator |
5ca7f415 MD |
386 | * requirements; returns maximum number of bitflips corrected in |
387 | * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error | |
388 | * @read_subpage: function to read parts of the page covered by ECC; | |
389 | * returns same as read_page() | |
837a6ba4 | 390 | * @write_subpage: function to write parts of the page covered by ECC. |
7854d3f7 | 391 | * @write_page: function to write a page according to the ECC generator |
a0491fc4 | 392 | * requirements. |
9ce244b3 | 393 | * @write_oob_raw: function to write chip OOB data without ECC |
c46f6483 | 394 | * @read_oob_raw: function to read chip OOB data without ECC |
844d3b42 RD |
395 | * @read_oob: function to read chip OOB data |
396 | * @write_oob: function to write chip OOB data | |
6dfc6d25 TG |
397 | */ |
398 | struct nand_ecc_ctrl { | |
b46daf7e SAS |
399 | nand_ecc_modes_t mode; |
400 | int steps; | |
401 | int size; | |
402 | int bytes; | |
403 | int total; | |
1d0b95b0 | 404 | int strength; |
b46daf7e SAS |
405 | int prepad; |
406 | int postpad; | |
5bd34c09 | 407 | struct nand_ecclayout *layout; |
193bd400 | 408 | void *priv; |
b46daf7e SAS |
409 | void (*hwctl)(struct mtd_info *mtd, int mode); |
410 | int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, | |
411 | uint8_t *ecc_code); | |
412 | int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, | |
413 | uint8_t *calc_ecc); | |
414 | int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 415 | uint8_t *buf, int oob_required, int page); |
fdbad98d | 416 | int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 417 | const uint8_t *buf, int oob_required); |
b46daf7e | 418 | int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 419 | uint8_t *buf, int oob_required, int page); |
b46daf7e SAS |
420 | int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, |
421 | uint32_t offs, uint32_t len, uint8_t *buf); | |
837a6ba4 GP |
422 | int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, |
423 | uint32_t offset, uint32_t data_len, | |
424 | const uint8_t *data_buf, int oob_required); | |
fdbad98d | 425 | int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 426 | const uint8_t *buf, int oob_required); |
9ce244b3 BN |
427 | int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, |
428 | int page); | |
c46f6483 | 429 | int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, |
5c2ffb11 SL |
430 | int page); |
431 | int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); | |
b46daf7e SAS |
432 | int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, |
433 | int page); | |
f75e5097 TG |
434 | }; |
435 | ||
436 | /** | |
437 | * struct nand_buffers - buffer structure for read/write | |
7854d3f7 BN |
438 | * @ecccalc: buffer for calculated ECC |
439 | * @ecccode: buffer for ECC read from flash | |
f75e5097 | 440 | * @databuf: buffer for data - dynamically sized |
f75e5097 TG |
441 | * |
442 | * Do not change the order of buffers. databuf and oobrbuf must be in | |
443 | * consecutive order. | |
444 | */ | |
445 | struct nand_buffers { | |
446 | uint8_t ecccalc[NAND_MAX_OOBSIZE]; | |
447 | uint8_t ecccode[NAND_MAX_OOBSIZE]; | |
7dcdcbef | 448 | uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; |
6dfc6d25 TG |
449 | }; |
450 | ||
1da177e4 LT |
451 | /** |
452 | * struct nand_chip - NAND Private Flash Chip Data | |
a0491fc4 SAS |
453 | * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the |
454 | * flash device | |
455 | * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the | |
456 | * flash device. | |
1da177e4 | 457 | * @read_byte: [REPLACEABLE] read one byte from the chip |
1da177e4 | 458 | * @read_word: [REPLACEABLE] read one word from the chip |
05f78359 UKK |
459 | * @write_byte: [REPLACEABLE] write a single byte to the chip on the |
460 | * low 8 I/O lines | |
1da177e4 LT |
461 | * @write_buf: [REPLACEABLE] write data from the buffer to the chip |
462 | * @read_buf: [REPLACEABLE] read data from the chip into the buffer | |
1da177e4 | 463 | * @select_chip: [REPLACEABLE] select chip nr |
ce157510 BN |
464 | * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers |
465 | * @block_markbad: [REPLACEABLE] mark a block bad | |
25985edc | 466 | * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling |
7abd3ef9 | 467 | * ALE/CLE/nCE. Also used to write command and address |
25985edc | 468 | * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting |
12a40a57 HS |
469 | * mtd->oobsize, mtd->writesize and so on. |
470 | * @id_data contains the 8 bytes values of NAND_CMD_READID. | |
471 | * Return with the bus width. | |
7854d3f7 | 472 | * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing |
a0491fc4 SAS |
473 | * device ready/busy line. If set to NULL no access to |
474 | * ready/busy is available and the ready/busy information | |
475 | * is read from the chip status register. | |
476 | * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing | |
477 | * commands to the chip. | |
478 | * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on | |
479 | * ready. | |
ba84fb59 BN |
480 | * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for |
481 | * setting the read-retry mode. Mostly needed for MLC NAND. | |
7854d3f7 | 482 | * @ecc: [BOARDSPECIFIC] ECC control structure |
844d3b42 RD |
483 | * @buffers: buffer structure for read/write |
484 | * @hwcontrol: platform-specific hardware control structure | |
a0491fc4 SAS |
485 | * @erase_cmd: [INTERN] erase command write function, selectable due |
486 | * to AND support. | |
1da177e4 | 487 | * @scan_bbt: [REPLACEABLE] function to scan bad block table |
25985edc | 488 | * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring |
a0491fc4 | 489 | * data from array to read regs (tR). |
2c0a2bed | 490 | * @state: [INTERN] the current state of the NAND device |
e9195edc BN |
491 | * @oob_poi: "poison value buffer," used for laying out OOB data |
492 | * before writing | |
a0491fc4 SAS |
493 | * @page_shift: [INTERN] number of address bits in a page (column |
494 | * address bits). | |
1da177e4 LT |
495 | * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock |
496 | * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry | |
497 | * @chip_shift: [INTERN] number of address bits in one chip | |
a0491fc4 SAS |
498 | * @options: [BOARDSPECIFIC] various chip options. They can partly |
499 | * be set to inform nand_scan about special functionality. | |
500 | * See the defines for further explanation. | |
5fb1549d BN |
501 | * @bbt_options: [INTERN] bad block specific options. All options used |
502 | * here must come from bbm.h. By default, these options | |
503 | * will be copied to the appropriate nand_bbt_descr's. | |
a0491fc4 SAS |
504 | * @badblockpos: [INTERN] position of the bad block marker in the oob |
505 | * area. | |
661a0832 BN |
506 | * @badblockbits: [INTERN] minimum number of set bits in a good block's |
507 | * bad block marker position; i.e., BBM == 11110111b is | |
508 | * not bad when badblockbits == 7 | |
7db906b7 | 509 | * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. |
4cfeca2d HS |
510 | * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. |
511 | * Minimum amount of bit errors per @ecc_step_ds guaranteed | |
512 | * to be correctable. If unknown, set to zero. | |
513 | * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, | |
514 | * also from the datasheet. It is the recommended ECC step | |
515 | * size, if known; if unknown, set to zero. | |
1da177e4 LT |
516 | * @numchips: [INTERN] number of physical chips |
517 | * @chipsize: [INTERN] the size of one chip for multichip arrays | |
518 | * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 | |
a0491fc4 SAS |
519 | * @pagebuf: [INTERN] holds the pagenumber which is currently in |
520 | * data_buf. | |
edbc4540 MD |
521 | * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is |
522 | * currently in data_buf. | |
29072b96 | 523 | * @subpagesize: [INTERN] holds the subpagesize |
a0491fc4 SAS |
524 | * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), |
525 | * non 0 if ONFI supported. | |
526 | * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is | |
527 | * supported, 0 otherwise. | |
ba84fb59 | 528 | * @read_retries: [INTERN] the number of read retry modes supported |
9ef525a9 RD |
529 | * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand |
530 | * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand | |
1da177e4 | 531 | * @bbt: [INTERN] bad block table pointer |
a0491fc4 SAS |
532 | * @bbt_td: [REPLACEABLE] bad block table descriptor for flash |
533 | * lookup. | |
1da177e4 | 534 | * @bbt_md: [REPLACEABLE] bad block table mirror descriptor |
a0491fc4 SAS |
535 | * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial |
536 | * bad block scan. | |
537 | * @controller: [REPLACEABLE] a pointer to a hardware controller | |
7854d3f7 | 538 | * structure which is shared among multiple independent |
a0491fc4 | 539 | * devices. |
32c8db8f | 540 | * @priv: [OPTIONAL] pointer to private chip data |
a0491fc4 SAS |
541 | * @errstat: [OPTIONAL] hardware specific function to perform |
542 | * additional error status checks (determine if errors are | |
543 | * correctable). | |
351edd24 | 544 | * @write_page: [REPLACEABLE] High-level page write function |
1da177e4 | 545 | */ |
61ecfa87 | 546 | |
1da177e4 | 547 | struct nand_chip { |
b46daf7e SAS |
548 | void __iomem *IO_ADDR_R; |
549 | void __iomem *IO_ADDR_W; | |
550 | ||
551 | uint8_t (*read_byte)(struct mtd_info *mtd); | |
552 | u16 (*read_word)(struct mtd_info *mtd); | |
05f78359 | 553 | void (*write_byte)(struct mtd_info *mtd, uint8_t byte); |
b46daf7e SAS |
554 | void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); |
555 | void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); | |
b46daf7e SAS |
556 | void (*select_chip)(struct mtd_info *mtd, int chip); |
557 | int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); | |
558 | int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); | |
559 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); | |
560 | int (*init_size)(struct mtd_info *mtd, struct nand_chip *this, | |
561 | u8 *id_data); | |
562 | int (*dev_ready)(struct mtd_info *mtd); | |
563 | void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, | |
564 | int page_addr); | |
565 | int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); | |
566 | void (*erase_cmd)(struct mtd_info *mtd, int page); | |
567 | int (*scan_bbt)(struct mtd_info *mtd); | |
568 | int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, | |
569 | int status, int page); | |
570 | int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, | |
837a6ba4 GP |
571 | uint32_t offset, int data_len, const uint8_t *buf, |
572 | int oob_required, int page, int cached, int raw); | |
7db03ecc HS |
573 | int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, |
574 | int feature_addr, uint8_t *subfeature_para); | |
575 | int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, | |
576 | int feature_addr, uint8_t *subfeature_para); | |
ba84fb59 | 577 | int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); |
b46daf7e SAS |
578 | |
579 | int chip_delay; | |
580 | unsigned int options; | |
5fb1549d | 581 | unsigned int bbt_options; |
b46daf7e SAS |
582 | |
583 | int page_shift; | |
584 | int phys_erase_shift; | |
585 | int bbt_erase_shift; | |
586 | int chip_shift; | |
587 | int numchips; | |
588 | uint64_t chipsize; | |
589 | int pagemask; | |
590 | int pagebuf; | |
edbc4540 | 591 | unsigned int pagebuf_bitflips; |
b46daf7e | 592 | int subpagesize; |
7db906b7 | 593 | uint8_t bits_per_cell; |
4cfeca2d HS |
594 | uint16_t ecc_strength_ds; |
595 | uint16_t ecc_step_ds; | |
b46daf7e SAS |
596 | int badblockpos; |
597 | int badblockbits; | |
598 | ||
599 | int onfi_version; | |
d1e1f4e4 FF |
600 | struct nand_onfi_params onfi_params; |
601 | ||
ba84fb59 BN |
602 | int read_retries; |
603 | ||
b46daf7e | 604 | flstate_t state; |
f75e5097 | 605 | |
b46daf7e SAS |
606 | uint8_t *oob_poi; |
607 | struct nand_hw_control *controller; | |
f75e5097 TG |
608 | |
609 | struct nand_ecc_ctrl ecc; | |
4bf63fcb | 610 | struct nand_buffers *buffers; |
f75e5097 TG |
611 | struct nand_hw_control hwcontrol; |
612 | ||
b46daf7e SAS |
613 | uint8_t *bbt; |
614 | struct nand_bbt_descr *bbt_td; | |
615 | struct nand_bbt_descr *bbt_md; | |
f75e5097 | 616 | |
b46daf7e | 617 | struct nand_bbt_descr *badblock_pattern; |
f75e5097 | 618 | |
b46daf7e | 619 | void *priv; |
1da177e4 LT |
620 | }; |
621 | ||
622 | /* | |
623 | * NAND Flash Manufacturer ID Codes | |
624 | */ | |
625 | #define NAND_MFR_TOSHIBA 0x98 | |
626 | #define NAND_MFR_SAMSUNG 0xec | |
627 | #define NAND_MFR_FUJITSU 0x04 | |
628 | #define NAND_MFR_NATIONAL 0x8f | |
629 | #define NAND_MFR_RENESAS 0x07 | |
630 | #define NAND_MFR_STMICRO 0x20 | |
2c0a2bed | 631 | #define NAND_MFR_HYNIX 0xad |
8c60e547 | 632 | #define NAND_MFR_MICRON 0x2c |
30eb0db0 | 633 | #define NAND_MFR_AMD 0x01 |
c1257b47 | 634 | #define NAND_MFR_MACRONIX 0xc2 |
b1ccfab3 | 635 | #define NAND_MFR_EON 0x92 |
1da177e4 | 636 | |
53552d22 AB |
637 | /* The maximum expected count of bytes in the NAND ID sequence */ |
638 | #define NAND_MAX_ID_LEN 8 | |
639 | ||
8dbfae1e AB |
640 | /* |
641 | * A helper for defining older NAND chips where the second ID byte fully | |
642 | * defined the chip, including the geometry (chip size, eraseblock size, page | |
5bfa9b71 | 643 | * size). All these chips have 512 bytes NAND page size. |
8dbfae1e | 644 | */ |
5bfa9b71 AB |
645 | #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ |
646 | { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ | |
647 | .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } | |
8dbfae1e AB |
648 | |
649 | /* | |
650 | * A helper for defining newer chips which report their page size and | |
651 | * eraseblock size via the extended ID bytes. | |
652 | * | |
653 | * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with | |
654 | * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the | |
655 | * device ID now only represented a particular total chip size (and voltage, | |
656 | * buswidth), and the page size, eraseblock size, and OOB size could vary while | |
657 | * using the same device ID. | |
658 | */ | |
8e12b474 AB |
659 | #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ |
660 | { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ | |
8dbfae1e AB |
661 | .options = (opts) } |
662 | ||
2dc0bdd9 HS |
663 | #define NAND_ECC_INFO(_strength, _step) \ |
664 | { .strength_ds = (_strength), .step_ds = (_step) } | |
665 | #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) | |
666 | #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) | |
667 | ||
1da177e4 LT |
668 | /** |
669 | * struct nand_flash_dev - NAND Flash Device ID Structure | |
68aa352d AB |
670 | * @name: a human-readable name of the NAND chip |
671 | * @dev_id: the device ID (the second byte of the full chip ID array) | |
8e12b474 AB |
672 | * @mfr_id: manufecturer ID part of the full chip ID array (refers the same |
673 | * memory address as @id[0]) | |
674 | * @dev_id: device ID part of the full chip ID array (refers the same memory | |
675 | * address as @id[1]) | |
676 | * @id: full device ID array | |
68aa352d AB |
677 | * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as |
678 | * well as the eraseblock size) is determined from the extended NAND | |
679 | * chip ID array) | |
68aa352d | 680 | * @chipsize: total chip size in MiB |
ecb42fea | 681 | * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) |
68aa352d | 682 | * @options: stores various chip bit options |
f22d5f63 HS |
683 | * @id_len: The valid length of the @id. |
684 | * @oobsize: OOB size | |
2dc0bdd9 HS |
685 | * @ecc.strength_ds: The ECC correctability from the datasheet, same as the |
686 | * @ecc_strength_ds in nand_chip{}. | |
687 | * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the | |
688 | * @ecc_step_ds in nand_chip{}, also from the datasheet. | |
689 | * For example, the "4bit ECC for each 512Byte" can be set with | |
690 | * NAND_ECC_INFO(4, 512). | |
1da177e4 LT |
691 | */ |
692 | struct nand_flash_dev { | |
693 | char *name; | |
8e12b474 AB |
694 | union { |
695 | struct { | |
696 | uint8_t mfr_id; | |
697 | uint8_t dev_id; | |
698 | }; | |
53552d22 | 699 | uint8_t id[NAND_MAX_ID_LEN]; |
8e12b474 | 700 | }; |
ecb42fea AB |
701 | unsigned int pagesize; |
702 | unsigned int chipsize; | |
703 | unsigned int erasesize; | |
704 | unsigned int options; | |
f22d5f63 HS |
705 | uint16_t id_len; |
706 | uint16_t oobsize; | |
2dc0bdd9 HS |
707 | struct { |
708 | uint16_t strength_ds; | |
709 | uint16_t step_ds; | |
710 | } ecc; | |
1da177e4 LT |
711 | }; |
712 | ||
713 | /** | |
714 | * struct nand_manufacturers - NAND Flash Manufacturer ID Structure | |
715 | * @name: Manufacturer name | |
2c0a2bed | 716 | * @id: manufacturer ID code of device. |
1da177e4 LT |
717 | */ |
718 | struct nand_manufacturers { | |
719 | int id; | |
a0491fc4 | 720 | char *name; |
1da177e4 LT |
721 | }; |
722 | ||
723 | extern struct nand_flash_dev nand_flash_ids[]; | |
724 | extern struct nand_manufacturers nand_manuf_ids[]; | |
725 | ||
f5bbdacc | 726 | extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); |
f5bbdacc | 727 | extern int nand_default_bbt(struct mtd_info *mtd); |
b32843b7 | 728 | extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); |
f5bbdacc TG |
729 | extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); |
730 | extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, | |
731 | int allowbbt); | |
732 | extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, | |
a0491fc4 | 733 | size_t *retlen, uint8_t *buf); |
1da177e4 | 734 | |
41796c2e TG |
735 | /** |
736 | * struct platform_nand_chip - chip level device structure | |
41796c2e | 737 | * @nr_chips: max. number of chips to scan for |
844d3b42 | 738 | * @chip_offset: chip number offset |
8be834f7 | 739 | * @nr_partitions: number of partitions pointed to by partitions (or zero) |
41796c2e TG |
740 | * @partitions: mtd partition list |
741 | * @chip_delay: R/B delay value in us | |
742 | * @options: Option flags, e.g. 16bit buswidth | |
a40f7341 | 743 | * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH |
7854d3f7 | 744 | * @ecclayout: ECC layout info structure |
972edcb7 | 745 | * @part_probe_types: NULL-terminated array of probe types |
41796c2e TG |
746 | */ |
747 | struct platform_nand_chip { | |
b46daf7e SAS |
748 | int nr_chips; |
749 | int chip_offset; | |
750 | int nr_partitions; | |
751 | struct mtd_partition *partitions; | |
752 | struct nand_ecclayout *ecclayout; | |
753 | int chip_delay; | |
754 | unsigned int options; | |
a40f7341 | 755 | unsigned int bbt_options; |
b46daf7e | 756 | const char **part_probe_types; |
41796c2e TG |
757 | }; |
758 | ||
bf95efd4 HS |
759 | /* Keep gcc happy */ |
760 | struct platform_device; | |
761 | ||
41796c2e TG |
762 | /** |
763 | * struct platform_nand_ctrl - controller level device structure | |
bf95efd4 HS |
764 | * @probe: platform specific function to probe/setup hardware |
765 | * @remove: platform specific function to remove/teardown hardware | |
41796c2e TG |
766 | * @hwcontrol: platform specific hardware control structure |
767 | * @dev_ready: platform specific function to read ready/busy pin | |
768 | * @select_chip: platform specific chip select function | |
972edcb7 VW |
769 | * @cmd_ctrl: platform specific function for controlling |
770 | * ALE/CLE/nCE. Also used to write command and address | |
d6fed9e9 AC |
771 | * @write_buf: platform specific function for write buffer |
772 | * @read_buf: platform specific function for read buffer | |
25806d3c | 773 | * @read_byte: platform specific function to read one byte from chip |
844d3b42 | 774 | * @priv: private data to transport driver specific settings |
41796c2e TG |
775 | * |
776 | * All fields are optional and depend on the hardware driver requirements | |
777 | */ | |
778 | struct platform_nand_ctrl { | |
b46daf7e SAS |
779 | int (*probe)(struct platform_device *pdev); |
780 | void (*remove)(struct platform_device *pdev); | |
781 | void (*hwcontrol)(struct mtd_info *mtd, int cmd); | |
782 | int (*dev_ready)(struct mtd_info *mtd); | |
783 | void (*select_chip)(struct mtd_info *mtd, int chip); | |
784 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); | |
785 | void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); | |
786 | void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); | |
b4f7aa84 | 787 | unsigned char (*read_byte)(struct mtd_info *mtd); |
b46daf7e | 788 | void *priv; |
41796c2e TG |
789 | }; |
790 | ||
972edcb7 VW |
791 | /** |
792 | * struct platform_nand_data - container structure for platform-specific data | |
793 | * @chip: chip level chip structure | |
794 | * @ctrl: controller level device structure | |
795 | */ | |
796 | struct platform_nand_data { | |
b46daf7e SAS |
797 | struct platform_nand_chip chip; |
798 | struct platform_nand_ctrl ctrl; | |
972edcb7 VW |
799 | }; |
800 | ||
41796c2e TG |
801 | /* Some helpers to access the data structures */ |
802 | static inline | |
803 | struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) | |
804 | { | |
805 | struct nand_chip *chip = mtd->priv; | |
806 | ||
807 | return chip->priv; | |
808 | } | |
809 | ||
5b40db68 HS |
810 | /* return the supported features. */ |
811 | static inline int onfi_feature(struct nand_chip *chip) | |
812 | { | |
813 | return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; | |
814 | } | |
815 | ||
3e70192c HS |
816 | /* return the supported asynchronous timing mode. */ |
817 | static inline int onfi_get_async_timing_mode(struct nand_chip *chip) | |
818 | { | |
819 | if (!chip->onfi_version) | |
820 | return ONFI_TIMING_MODE_UNKNOWN; | |
821 | return le16_to_cpu(chip->onfi_params.async_timing_mode); | |
822 | } | |
823 | ||
824 | /* return the supported synchronous timing mode. */ | |
825 | static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) | |
826 | { | |
827 | if (!chip->onfi_version) | |
828 | return ONFI_TIMING_MODE_UNKNOWN; | |
829 | return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); | |
830 | } | |
831 | ||
1d0ed69d HS |
832 | /* |
833 | * Check if it is a SLC nand. | |
834 | * The !nand_is_slc() can be used to check the MLC/TLC nand chips. | |
835 | * We do not distinguish the MLC and TLC now. | |
836 | */ | |
837 | static inline bool nand_is_slc(struct nand_chip *chip) | |
838 | { | |
7db906b7 | 839 | return chip->bits_per_cell == 1; |
1d0ed69d | 840 | } |
1da177e4 | 841 | #endif /* __LINUX_MTD_NAND_H */ |