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b60503ba MW |
1 | /* |
2 | * Definitions for the NVM Express interface | |
42c77683 | 3 | * Copyright (c) 2011-2013, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #ifndef _LINUX_NVME_H | |
20 | #define _LINUX_NVME_H | |
21 | ||
42c77683 MW |
22 | #include <uapi/linux/nvme.h> |
23 | #include <linux/pci.h> | |
24 | #include <linux/miscdevice.h> | |
25 | #include <linux/kref.h> | |
b60503ba MW |
26 | |
27 | struct nvme_bar { | |
28 | __u64 cap; /* Controller Capabilities */ | |
29 | __u32 vs; /* Version */ | |
897cfe1c MW |
30 | __u32 intms; /* Interrupt Mask Set */ |
31 | __u32 intmc; /* Interrupt Mask Clear */ | |
b60503ba | 32 | __u32 cc; /* Controller Configuration */ |
897cfe1c | 33 | __u32 rsvd1; /* Reserved */ |
b60503ba | 34 | __u32 csts; /* Controller Status */ |
897cfe1c | 35 | __u32 rsvd2; /* Reserved */ |
b60503ba MW |
36 | __u32 aqa; /* Admin Queue Attributes */ |
37 | __u64 asq; /* Admin SQ Base Address */ | |
38 | __u64 acq; /* Admin CQ Base Address */ | |
39 | }; | |
40 | ||
a0cadb85 | 41 | #define NVME_CAP_MQES(cap) ((cap) & 0xffff) |
22605f96 | 42 | #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) |
f1938f6e | 43 | #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) |
8fc23e03 | 44 | #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) |
22605f96 | 45 | |
b60503ba MW |
46 | enum { |
47 | NVME_CC_ENABLE = 1 << 0, | |
48 | NVME_CC_CSS_NVM = 0 << 4, | |
49 | NVME_CC_MPS_SHIFT = 7, | |
50 | NVME_CC_ARB_RR = 0 << 11, | |
51 | NVME_CC_ARB_WRRU = 1 << 11, | |
7f53f9d2 MW |
52 | NVME_CC_ARB_VS = 7 << 11, |
53 | NVME_CC_SHN_NONE = 0 << 14, | |
54 | NVME_CC_SHN_NORMAL = 1 << 14, | |
55 | NVME_CC_SHN_ABRUPT = 2 << 14, | |
1894d8f1 | 56 | NVME_CC_SHN_MASK = 3 << 14, |
7f53f9d2 MW |
57 | NVME_CC_IOSQES = 6 << 16, |
58 | NVME_CC_IOCQES = 4 << 20, | |
b60503ba MW |
59 | NVME_CSTS_RDY = 1 << 0, |
60 | NVME_CSTS_CFS = 1 << 1, | |
61 | NVME_CSTS_SHST_NORMAL = 0 << 2, | |
62 | NVME_CSTS_SHST_OCCUR = 1 << 2, | |
63 | NVME_CSTS_SHST_CMPLT = 2 << 2, | |
1894d8f1 | 64 | NVME_CSTS_SHST_MASK = 3 << 2, |
b60503ba MW |
65 | }; |
66 | ||
67 | #define NVME_VS(major, minor) (major << 16 | minor) | |
68 | ||
b355084a KB |
69 | extern unsigned char io_timeout; |
70 | #define NVME_IO_TIMEOUT (io_timeout * HZ) | |
13c3b0fc VV |
71 | |
72 | /* | |
73 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
74 | */ | |
75 | struct nvme_dev { | |
76 | struct list_head node; | |
5a92e700 | 77 | struct nvme_queue __rcu **queues; |
42f61420 | 78 | unsigned short __percpu *io_queue; |
13c3b0fc VV |
79 | u32 __iomem *dbs; |
80 | struct pci_dev *pci_dev; | |
81 | struct dma_pool *prp_page_pool; | |
82 | struct dma_pool *prp_small_pool; | |
83 | int instance; | |
42f61420 KB |
84 | unsigned queue_count; |
85 | unsigned online_queues; | |
86 | unsigned max_qid; | |
87 | int q_depth; | |
b80d5ccc | 88 | u32 db_stride; |
13c3b0fc VV |
89 | u32 ctrl_config; |
90 | struct msix_entry *entry; | |
91 | struct nvme_bar __iomem *bar; | |
92 | struct list_head namespaces; | |
5e82e952 KB |
93 | struct kref kref; |
94 | struct miscdevice miscdev; | |
9ca97374 | 95 | work_func_t reset_workfn; |
9a6b9458 | 96 | struct work_struct reset_work; |
33b1e95c | 97 | struct notifier_block nb; |
5e82e952 | 98 | char name[12]; |
13c3b0fc VV |
99 | char serial[20]; |
100 | char model[40]; | |
101 | char firmware_rev[8]; | |
102 | u32 max_hw_sectors; | |
159b67d7 | 103 | u32 stripe_size; |
13c3b0fc | 104 | u16 oncs; |
c30341dc | 105 | u16 abort_limit; |
d4b4ff8e | 106 | u8 initialized; |
13c3b0fc VV |
107 | }; |
108 | ||
109 | /* | |
110 | * An NVM Express namespace is equivalent to a SCSI LUN | |
111 | */ | |
112 | struct nvme_ns { | |
113 | struct list_head list; | |
114 | ||
115 | struct nvme_dev *dev; | |
116 | struct request_queue *queue; | |
117 | struct gendisk *disk; | |
118 | ||
c3bfe717 | 119 | unsigned ns_id; |
13c3b0fc | 120 | int lba_shift; |
f410c680 | 121 | int ms; |
5d0f6131 VV |
122 | u64 mode_select_num_blocks; |
123 | u32 mode_select_block_len; | |
13c3b0fc VV |
124 | }; |
125 | ||
126 | /* | |
127 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
128 | * entries. You can't see it in this data structure because C doesn't let | |
129 | * me express that. Use nvme_alloc_iod to ensure there's enough space | |
130 | * allocated to store the PRP list. | |
131 | */ | |
132 | struct nvme_iod { | |
133 | void *private; /* For the use of the submitter of the I/O */ | |
134 | int npages; /* In the PRP list. 0 means small pool in use */ | |
135 | int offset; /* Of PRP list */ | |
136 | int nents; /* Used in scatterlist */ | |
137 | int length; /* Of data, in bytes */ | |
6198221f | 138 | unsigned long start_time; |
13c3b0fc | 139 | dma_addr_t first_dma; |
edd10d33 | 140 | struct list_head node; |
13c3b0fc VV |
141 | struct scatterlist sg[0]; |
142 | }; | |
5d0f6131 | 143 | |
063cc6d5 MW |
144 | static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector) |
145 | { | |
146 | return (sector >> (ns->lba_shift - 9)); | |
147 | } | |
148 | ||
5d0f6131 VV |
149 | /** |
150 | * nvme_free_iod - frees an nvme_iod | |
151 | * @dev: The device that the I/O was submitted to | |
152 | * @iod: The memory to free | |
153 | */ | |
154 | void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod); | |
155 | ||
edd10d33 | 156 | int nvme_setup_prps(struct nvme_dev *, struct nvme_iod *, int , gfp_t); |
5d0f6131 VV |
157 | struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write, |
158 | unsigned long addr, unsigned length); | |
159 | void nvme_unmap_user_pages(struct nvme_dev *dev, int write, | |
160 | struct nvme_iod *iod); | |
4f5099af | 161 | int nvme_submit_io_cmd(struct nvme_dev *, struct nvme_command *, u32 *); |
5d0f6131 VV |
162 | int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns); |
163 | int nvme_submit_admin_cmd(struct nvme_dev *, struct nvme_command *, | |
164 | u32 *result); | |
165 | int nvme_identify(struct nvme_dev *, unsigned nsid, unsigned cns, | |
166 | dma_addr_t dma_addr); | |
167 | int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, | |
168 | dma_addr_t dma_addr, u32 *result); | |
169 | int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, | |
170 | dma_addr_t dma_addr, u32 *result); | |
171 | ||
172 | struct sg_io_hdr; | |
173 | ||
174 | int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr); | |
320a3827 | 175 | int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg); |
5d0f6131 VV |
176 | int nvme_sg_get_version_num(int __user *ip); |
177 | ||
b60503ba | 178 | #endif /* _LINUX_NVME_H */ |