[deliverable/linux.git] / include / linux / nvme.h

/*
 * Definitions for the NVM Express interface
 * Copyright (c) 2011-2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef _LINUX_NVME_H
#define _LINUX_NVME_H

#include <uapi/linux/nvme.h>
#include <linux/pci.h>
#include <linux/kref.h>
#include <linux/blk-mq.h>

struct nvme_bar {
	__u64			cap;	/* Controller Capabilities */
	__u32			vs;	/* Version */
	__u32			intms;	/* Interrupt Mask Set */
	__u32			intmc;	/* Interrupt Mask Clear */
	__u32			cc;	/* Controller Configuration */
	__u32			rsvd1;	/* Reserved */
	__u32			csts;	/* Controller Status */
	__u32			nssr;	/* Subsystem Reset */
	__u32			aqa;	/* Admin Queue Attributes */
	__u64			asq;	/* Admin SQ Base Address */
	__u64			acq;	/* Admin CQ Base Address */
	__u32			cmbloc; /* Controller Memory Buffer Location */
	__u32			cmbsz;  /* Controller Memory Buffer Size */
};

#define NVME_CAP_MQES(cap)	((cap) & 0xffff)
#define NVME_CAP_TIMEOUT(cap)	(((cap) >> 24) & 0xff)
#define NVME_CAP_STRIDE(cap)	(((cap) >> 32) & 0xf)
#define NVME_CAP_NSSRC(cap)	(((cap) >> 36) & 0x1)
#define NVME_CAP_MPSMIN(cap)	(((cap) >> 48) & 0xf)
#define NVME_CAP_MPSMAX(cap)	(((cap) >> 52) & 0xf)

#define NVME_CMB_BIR(cmbloc)	((cmbloc) & 0x7)
#define NVME_CMB_OFST(cmbloc)	(((cmbloc) >> 12) & 0xfffff)
#define NVME_CMB_SZ(cmbsz)	(((cmbsz) >> 12) & 0xfffff)
#define NVME_CMB_SZU(cmbsz)	(((cmbsz) >> 8) & 0xf)

#define NVME_CMB_WDS(cmbsz)	((cmbsz) & 0x10)
#define NVME_CMB_RDS(cmbsz)	((cmbsz) & 0x8)
#define NVME_CMB_LISTS(cmbsz)	((cmbsz) & 0x4)
#define NVME_CMB_CQS(cmbsz)	((cmbsz) & 0x2)
#define NVME_CMB_SQS(cmbsz)	((cmbsz) & 0x1)

enum {
	NVME_CC_ENABLE		= 1 << 0,
	NVME_CC_CSS_NVM		= 0 << 4,
	NVME_CC_MPS_SHIFT	= 7,
	NVME_CC_ARB_RR		= 0 << 11,
	NVME_CC_ARB_WRRU	= 1 << 11,
	NVME_CC_ARB_VS		= 7 << 11,
	NVME_CC_SHN_NONE	= 0 << 14,
	NVME_CC_SHN_NORMAL	= 1 << 14,
	NVME_CC_SHN_ABRUPT	= 2 << 14,
	NVME_CC_SHN_MASK	= 3 << 14,
	NVME_CC_IOSQES		= 6 << 16,
	NVME_CC_IOCQES		= 4 << 20,
	NVME_CSTS_RDY		= 1 << 0,
	NVME_CSTS_CFS		= 1 << 1,
	NVME_CSTS_NSSRO		= 1 << 4,
	NVME_CSTS_SHST_NORMAL	= 0 << 2,
	NVME_CSTS_SHST_OCCUR	= 1 << 2,
	NVME_CSTS_SHST_CMPLT	= 2 << 2,
	NVME_CSTS_SHST_MASK	= 3 << 2,
};

extern unsigned char nvme_io_timeout;
#define NVME_IO_TIMEOUT	(nvme_io_timeout * HZ)

/*
 * Represents an NVM Express device.  Each nvme_dev is a PCI function.
 */
struct nvme_dev {
	struct list_head node;
	struct nvme_queue **queues;
	struct request_queue *admin_q;
	struct blk_mq_tag_set tagset;
	struct blk_mq_tag_set admin_tagset;
	u32 __iomem *dbs;
	struct device *dev;
	struct dma_pool *prp_page_pool;
	struct dma_pool *prp_small_pool;
	int instance;
	unsigned queue_count;
	unsigned online_queues;
	unsigned max_qid;
	int q_depth;
	u32 db_stride;
	u32 ctrl_config;
	struct msix_entry *entry;
	struct nvme_bar __iomem *bar;
	struct list_head namespaces;
	struct kref kref;
	struct device *device;
	work_func_t reset_workfn;
	struct work_struct reset_work;
	struct work_struct probe_work;
	struct work_struct scan_work;
	char name[12];
	char serial[20];
	char model[40];
	char firmware_rev[8];
	bool subsystem;
	u32 max_hw_sectors;
	u32 stripe_size;
	u32 page_size;
	void __iomem *cmb;
	dma_addr_t cmb_dma_addr;
	u64 cmb_size;
	u32 cmbsz;
	u16 oncs;
	u16 abort_limit;
	u8 event_limit;
	u8 vwc;
};

/*
 * An NVM Express namespace is equivalent to a SCSI LUN
 */
struct nvme_ns {
	struct list_head list;

	struct nvme_dev *dev;
	struct request_queue *queue;
	struct gendisk *disk;

	unsigned ns_id;
	int lba_shift;
	u16 ms;
	bool ext;
	u8 pi_type;
	u64 mode_select_num_blocks;
	u32 mode_select_block_len;
};

/*
 * The nvme_iod describes the data in an I/O, including the list of PRP
 * entries.  You can't see it in this data structure because C doesn't let
 * me express that.  Use nvme_alloc_iod to ensure there's enough space
 * allocated to store the PRP list.
 */
struct nvme_iod {
	unsigned long private;	/* For the use of the submitter of the I/O */
	int npages;		/* In the PRP list. 0 means small pool in use */
	int offset;		/* Of PRP list */
	int nents;		/* Used in scatterlist */
	int length;		/* Of data, in bytes */
	dma_addr_t first_dma;
	struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */
	struct scatterlist sg[0];
};

static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
{
	return (sector >> (ns->lba_shift - 9));
}

int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		void *buf, unsigned bufflen);
int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		void *buffer, void __user *ubuffer, unsigned bufflen,
		u32 *result, unsigned timeout);
int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id);
int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid,
		struct nvme_id_ns **id);
int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log);
int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
			dma_addr_t dma_addr, u32 *result);
int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
			dma_addr_t dma_addr, u32 *result);

struct sg_io_hdr;

int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr);
int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
int nvme_sg_get_version_num(int __user *ip);

#endif /* _LINUX_NVME_H */
Commit	Line	Data
b60503ba MW	1	/*
b60503ba MW	2	* Definitions for the NVM Express interface
8757ad65	3	* Copyright (c) 2011-2014, Intel Corporation.
b60503ba MW	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
b60503ba MW	13	*/
	14
	15	#ifndef _LINUX_NVME_H
	16	#define _LINUX_NVME_H
	17
42c77683 MW	18	#include <uapi/linux/nvme.h>
42c77683 MW	19	#include <linux/pci.h>
42c77683	20	#include <linux/kref.h>
a4aea562	21	#include <linux/blk-mq.h>
b60503ba MW	22
	23	struct nvme_bar {
	24	__u64 cap; /* Controller Capabilities */
	25	__u32 vs; /* Version */
897cfe1c MW	26	__u32 intms; /* Interrupt Mask Set */
897cfe1c MW	27	__u32 intmc; /* Interrupt Mask Clear */
b60503ba	28	__u32 cc; /* Controller Configuration */
897cfe1c	29	__u32 rsvd1; /* Reserved */
b60503ba	30	__u32 csts; /* Controller Status */
81f03fed	31	__u32 nssr; /* Subsystem Reset */
b60503ba MW	32	__u32 aqa; /* Admin Queue Attributes */
	33	__u64 asq; /* Admin SQ Base Address */
	34	__u64 acq; /* Admin CQ Base Address */
8ffaadf7 JD	35	__u32 cmbloc; /* Controller Memory Buffer Location */
8ffaadf7 JD	36	__u32 cmbsz; /* Controller Memory Buffer Size */
b60503ba MW	37	};
b60503ba MW	38
a0cadb85	39	#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
22605f96	40	#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
f1938f6e	41	#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
dfbac8c7	42	#define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
8fc23e03	43	#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
1d090624	44	#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
22605f96	45
8ffaadf7 JD	46	#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
	47	#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
	48	#define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff)
	49	#define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf)
	50
	51	#define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10)
	52	#define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8)
	53	#define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4)
	54	#define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2)
	55	#define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1)
	56
b60503ba MW	57	enum {
	58	NVME_CC_ENABLE = 1 << 0,
	59	NVME_CC_CSS_NVM = 0 << 4,
	60	NVME_CC_MPS_SHIFT = 7,
	61	NVME_CC_ARB_RR = 0 << 11,
	62	NVME_CC_ARB_WRRU = 1 << 11,
7f53f9d2 MW	63	NVME_CC_ARB_VS = 7 << 11,
	64	NVME_CC_SHN_NONE = 0 << 14,
	65	NVME_CC_SHN_NORMAL = 1 << 14,
	66	NVME_CC_SHN_ABRUPT = 2 << 14,
1894d8f1	67	NVME_CC_SHN_MASK = 3 << 14,
7f53f9d2 MW	68	NVME_CC_IOSQES = 6 << 16,
7f53f9d2 MW	69	NVME_CC_IOCQES = 4 << 20,
b60503ba MW	70	NVME_CSTS_RDY = 1 << 0,
b60503ba MW	71	NVME_CSTS_CFS = 1 << 1,
dfbac8c7	72	NVME_CSTS_NSSRO = 1 << 4,
b60503ba MW	73	NVME_CSTS_SHST_NORMAL = 0 << 2,
	74	NVME_CSTS_SHST_OCCUR = 1 << 2,
	75	NVME_CSTS_SHST_CMPLT = 2 << 2,
1894d8f1	76	NVME_CSTS_SHST_MASK = 3 << 2,
b60503ba MW	77	};
b60503ba MW	78
bd67608a MW	79	extern unsigned char nvme_io_timeout;
bd67608a MW	80	#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
13c3b0fc VV	81
	82	/*
	83	* Represents an NVM Express device. Each nvme_dev is a PCI function.
	84	*/
	85	struct nvme_dev {
	86	struct list_head node;
a4aea562 MB	87	struct nvme_queue **queues;
	88	struct request_queue *admin_q;
	89	struct blk_mq_tag_set tagset;
	90	struct blk_mq_tag_set admin_tagset;
13c3b0fc	91	u32 __iomem *dbs;
e75ec752	92	struct device *dev;
13c3b0fc VV	93	struct dma_pool *prp_page_pool;
	94	struct dma_pool *prp_small_pool;
	95	int instance;
42f61420 KB	96	unsigned queue_count;
	97	unsigned online_queues;
	98	unsigned max_qid;
	99	int q_depth;
b80d5ccc	100	u32 db_stride;
13c3b0fc VV	101	u32 ctrl_config;
	102	struct msix_entry *entry;
	103	struct nvme_bar __iomem *bar;
	104	struct list_head namespaces;
5e82e952	105	struct kref kref;
b3fffdef	106	struct device *device;
9ca97374	107	work_func_t reset_workfn;
9a6b9458	108	struct work_struct reset_work;
2e1d8448	109	struct work_struct probe_work;
a5768aa8	110	struct work_struct scan_work;
5e82e952	111	char name[12];
13c3b0fc VV	112	char serial[20];
	113	char model[40];
	114	char firmware_rev[8];
dfbac8c7	115	bool subsystem;
13c3b0fc	116	u32 max_hw_sectors;
159b67d7	117	u32 stripe_size;
1d090624	118	u32 page_size;
8ffaadf7 JD	119	void __iomem *cmb;
	120	dma_addr_t cmb_dma_addr;
	121	u64 cmb_size;
	122	u32 cmbsz;
13c3b0fc	123	u16 oncs;
c30341dc	124	u16 abort_limit;
6fccf938	125	u8 event_limit;
a7d2ce28	126	u8 vwc;
13c3b0fc VV	127	};
	128
	129	/*
	130	* An NVM Express namespace is equivalent to a SCSI LUN
	131	*/
	132	struct nvme_ns {
	133	struct list_head list;
	134
	135	struct nvme_dev *dev;
	136	struct request_queue *queue;
	137	struct gendisk *disk;
	138
c3bfe717	139	unsigned ns_id;
13c3b0fc	140	int lba_shift;
a67a9513 KB	141	u16 ms;
	142	bool ext;
	143	u8 pi_type;
5d0f6131 VV	144	u64 mode_select_num_blocks;
5d0f6131 VV	145	u32 mode_select_block_len;
13c3b0fc VV	146	};
	147
	148	/*
	149	* The nvme_iod describes the data in an I/O, including the list of PRP
	150	* entries. You can't see it in this data structure because C doesn't let
	151	* me express that. Use nvme_alloc_iod to ensure there's enough space
	152	* allocated to store the PRP list.
	153	*/
	154	struct nvme_iod {
ac3dd5bd	155	unsigned long private; /* For the use of the submitter of the I/O */
13c3b0fc VV	156	int npages; /* In the PRP list. 0 means small pool in use */
	157	int offset; /* Of PRP list */
	158	int nents; /* Used in scatterlist */
	159	int length; /* Of data, in bytes */
	160	dma_addr_t first_dma;
e1e5e564	161	struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */
13c3b0fc VV	162	struct scatterlist sg[0];
13c3b0fc VV	163	};
5d0f6131	164
063cc6d5 MW	165	static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
	166	{
	167	return (sector >> (ns->lba_shift - 9));
	168	}
	169
d29ec824 CH	170	int nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
	171	void *buf, unsigned bufflen);
	172	int __nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
	173	void buffer, void __user ubuffer, unsigned bufflen,
	174	u32 *result, unsigned timeout);
	175	int nvme_identify_ctrl(struct nvme_dev dev, struct nvme_id_ctrl *id);
	176	int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid,
	177	struct nvme_id_ns **id);
	178	int nvme_get_log_page(struct nvme_dev dev, struct nvme_smart_log *log);
5d0f6131 VV	179	int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
	180	dma_addr_t dma_addr, u32 *result);
	181	int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
	182	dma_addr_t dma_addr, u32 *result);
	183
	184	struct sg_io_hdr;
	185
	186	int nvme_sg_io(struct nvme_ns ns, struct sg_io_hdr __user u_hdr);
320a3827	187	int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
5d0f6131 VV	188	int nvme_sg_get_version_num(int __user *ip);
5d0f6131 VV	189
b60503ba	190	#endif /* _LINUX_NVME_H */