Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * pci.h | |
3 | * | |
4 | * PCI defines and function prototypes | |
5 | * Copyright 1994, Drew Eckhardt | |
6 | * Copyright 1997--1999 Martin Mares <mj@ucw.cz> | |
7 | * | |
8 | * For more information, please consult the following manuals (look at | |
9 | * http://www.pcisig.com/ for how to get them): | |
10 | * | |
11 | * PCI BIOS Specification | |
12 | * PCI Local Bus Specification | |
13 | * PCI to PCI Bridge Specification | |
14 | * PCI System Design Guide | |
15 | */ | |
1da177e4 LT |
16 | #ifndef LINUX_PCI_H |
17 | #define LINUX_PCI_H | |
18 | ||
1da177e4 | 19 | |
778382e0 DW |
20 | #include <linux/mod_devicetable.h> |
21 | ||
1da177e4 | 22 | #include <linux/types.h> |
98db6f19 | 23 | #include <linux/init.h> |
1da177e4 LT |
24 | #include <linux/ioport.h> |
25 | #include <linux/list.h> | |
4a7fb636 | 26 | #include <linux/compiler.h> |
1da177e4 | 27 | #include <linux/errno.h> |
f46753c5 | 28 | #include <linux/kobject.h> |
60063497 | 29 | #include <linux/atomic.h> |
1da177e4 | 30 | #include <linux/device.h> |
1388cc96 | 31 | #include <linux/io.h> |
74bb1bcc | 32 | #include <linux/irqreturn.h> |
607ca46e | 33 | #include <uapi/linux/pci.h> |
1da177e4 | 34 | |
7e7a43c3 AB |
35 | /* Include the ID list */ |
36 | #include <linux/pci_ids.h> | |
37 | ||
85467136 SK |
38 | /* |
39 | * The PCI interface treats multi-function devices as independent | |
40 | * devices. The slot/function address of each device is encoded | |
41 | * in a single byte as follows: | |
42 | * | |
43 | * 7:3 = slot | |
44 | * 2:0 = function | |
45 | * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined uapi/linux/pci.h | |
46 | * In the interest of not exposing interfaces to user-space unnecessarily, | |
47 | * the following kernel only defines are being added here. | |
48 | */ | |
49 | #define PCI_DEVID(bus, devfn) ((((u16)bus) << 8) | devfn) | |
50 | /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ | |
51 | #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) | |
52 | ||
f46753c5 AC |
53 | /* pci_slot represents a physical slot */ |
54 | struct pci_slot { | |
55 | struct pci_bus *bus; /* The bus this slot is on */ | |
56 | struct list_head list; /* node in list of slots on this bus */ | |
57 | struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ | |
58 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ | |
59 | struct kobject kobj; | |
60 | }; | |
61 | ||
0ad772ec AC |
62 | static inline const char *pci_slot_name(const struct pci_slot *slot) |
63 | { | |
64 | return kobject_name(&slot->kobj); | |
65 | } | |
66 | ||
1da177e4 LT |
67 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
68 | enum pci_mmap_state { | |
69 | pci_mmap_io, | |
70 | pci_mmap_mem | |
71 | }; | |
72 | ||
73 | /* This defines the direction arg to the DMA mapping routines. */ | |
74 | #define PCI_DMA_BIDIRECTIONAL 0 | |
75 | #define PCI_DMA_TODEVICE 1 | |
76 | #define PCI_DMA_FROMDEVICE 2 | |
77 | #define PCI_DMA_NONE 3 | |
78 | ||
fde09c6d YZ |
79 | /* |
80 | * For PCI devices, the region numbers are assigned this way: | |
81 | */ | |
82 | enum { | |
83 | /* #0-5: standard PCI resources */ | |
84 | PCI_STD_RESOURCES, | |
85 | PCI_STD_RESOURCE_END = 5, | |
86 | ||
87 | /* #6: expansion ROM resource */ | |
88 | PCI_ROM_RESOURCE, | |
89 | ||
d1b054da YZ |
90 | /* device specific resources */ |
91 | #ifdef CONFIG_PCI_IOV | |
92 | PCI_IOV_RESOURCES, | |
93 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, | |
94 | #endif | |
95 | ||
fde09c6d YZ |
96 | /* resources assigned to buses behind the bridge */ |
97 | #define PCI_BRIDGE_RESOURCE_NUM 4 | |
98 | ||
99 | PCI_BRIDGE_RESOURCES, | |
100 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + | |
101 | PCI_BRIDGE_RESOURCE_NUM - 1, | |
102 | ||
103 | /* total resources associated with a PCI device */ | |
104 | PCI_NUM_RESOURCES, | |
105 | ||
106 | /* preserve this for compatibility */ | |
cda57bf9 | 107 | DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, |
fde09c6d | 108 | }; |
1da177e4 LT |
109 | |
110 | typedef int __bitwise pci_power_t; | |
111 | ||
4352dfd5 GKH |
112 | #define PCI_D0 ((pci_power_t __force) 0) |
113 | #define PCI_D1 ((pci_power_t __force) 1) | |
114 | #define PCI_D2 ((pci_power_t __force) 2) | |
1da177e4 LT |
115 | #define PCI_D3hot ((pci_power_t __force) 3) |
116 | #define PCI_D3cold ((pci_power_t __force) 4) | |
3fe9d19f | 117 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
438510f6 | 118 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
1da177e4 | 119 | |
00240c38 AS |
120 | /* Remember to update this when the list above changes! */ |
121 | extern const char *pci_power_names[]; | |
122 | ||
123 | static inline const char *pci_power_name(pci_power_t state) | |
124 | { | |
125 | return pci_power_names[1 + (int) state]; | |
126 | } | |
127 | ||
448bd857 HY |
128 | #define PCI_PM_D2_DELAY 200 |
129 | #define PCI_PM_D3_WAIT 10 | |
130 | #define PCI_PM_D3COLD_WAIT 100 | |
131 | #define PCI_PM_BUS_WAIT 50 | |
aa8c6c93 | 132 | |
392a1ce7 | 133 | /** The pci_channel state describes connectivity between the CPU and |
134 | * the pci device. If some PCI bus between here and the pci device | |
135 | * has crashed or locked up, this info is reflected here. | |
136 | */ | |
137 | typedef unsigned int __bitwise pci_channel_state_t; | |
138 | ||
139 | enum pci_channel_state { | |
140 | /* I/O channel is in normal state */ | |
141 | pci_channel_io_normal = (__force pci_channel_state_t) 1, | |
142 | ||
143 | /* I/O to channel is blocked */ | |
144 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, | |
145 | ||
146 | /* PCI card is dead */ | |
147 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, | |
148 | }; | |
149 | ||
f7bdd12d BK |
150 | typedef unsigned int __bitwise pcie_reset_state_t; |
151 | ||
152 | enum pcie_reset_state { | |
153 | /* Reset is NOT asserted (Use to deassert reset) */ | |
154 | pcie_deassert_reset = (__force pcie_reset_state_t) 1, | |
155 | ||
156 | /* Use #PERST to reset PCI-E device */ | |
157 | pcie_warm_reset = (__force pcie_reset_state_t) 2, | |
158 | ||
159 | /* Use PCI-E Hot Reset to reset device */ | |
160 | pcie_hot_reset = (__force pcie_reset_state_t) 3 | |
161 | }; | |
162 | ||
ba698ad4 DM |
163 | typedef unsigned short __bitwise pci_dev_flags_t; |
164 | enum pci_dev_flags { | |
165 | /* INTX_DISABLE in PCI_COMMAND register disables MSI | |
166 | * generation too. | |
167 | */ | |
168 | PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, | |
979b1791 AC |
169 | /* Device configuration is irrevocably lost if disabled into D3 */ |
170 | PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2, | |
6777829c GR |
171 | /* Provide indication device is assigned by a Virtual Machine Manager */ |
172 | PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4, | |
ba698ad4 DM |
173 | }; |
174 | ||
e1d3a908 SA |
175 | enum pci_irq_reroute_variant { |
176 | INTEL_IRQ_REROUTE_VARIANT = 1, | |
177 | MAX_IRQ_REROUTE_VARIANTS = 3 | |
178 | }; | |
179 | ||
6e325a62 MT |
180 | typedef unsigned short __bitwise pci_bus_flags_t; |
181 | enum pci_bus_flags { | |
d556ad4b PO |
182 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
183 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, | |
6e325a62 MT |
184 | }; |
185 | ||
59da381e JK |
186 | /* These values come from the PCI Express Spec */ |
187 | enum pcie_link_width { | |
188 | PCIE_LNK_WIDTH_RESRV = 0x00, | |
189 | PCIE_LNK_X1 = 0x01, | |
190 | PCIE_LNK_X2 = 0x02, | |
191 | PCIE_LNK_X4 = 0x04, | |
192 | PCIE_LNK_X8 = 0x08, | |
193 | PCIE_LNK_X12 = 0x0C, | |
194 | PCIE_LNK_X16 = 0x10, | |
195 | PCIE_LNK_X32 = 0x20, | |
196 | PCIE_LNK_WIDTH_UNKNOWN = 0xFF, | |
197 | }; | |
198 | ||
536c8cb4 MW |
199 | /* Based on the PCI Hotplug Spec, but some values are made up by us */ |
200 | enum pci_bus_speed { | |
201 | PCI_SPEED_33MHz = 0x00, | |
202 | PCI_SPEED_66MHz = 0x01, | |
203 | PCI_SPEED_66MHz_PCIX = 0x02, | |
204 | PCI_SPEED_100MHz_PCIX = 0x03, | |
205 | PCI_SPEED_133MHz_PCIX = 0x04, | |
206 | PCI_SPEED_66MHz_PCIX_ECC = 0x05, | |
207 | PCI_SPEED_100MHz_PCIX_ECC = 0x06, | |
208 | PCI_SPEED_133MHz_PCIX_ECC = 0x07, | |
209 | PCI_SPEED_66MHz_PCIX_266 = 0x09, | |
210 | PCI_SPEED_100MHz_PCIX_266 = 0x0a, | |
211 | PCI_SPEED_133MHz_PCIX_266 = 0x0b, | |
45b4cdd5 MW |
212 | AGP_UNKNOWN = 0x0c, |
213 | AGP_1X = 0x0d, | |
214 | AGP_2X = 0x0e, | |
215 | AGP_4X = 0x0f, | |
216 | AGP_8X = 0x10, | |
536c8cb4 MW |
217 | PCI_SPEED_66MHz_PCIX_533 = 0x11, |
218 | PCI_SPEED_100MHz_PCIX_533 = 0x12, | |
219 | PCI_SPEED_133MHz_PCIX_533 = 0x13, | |
220 | PCIE_SPEED_2_5GT = 0x14, | |
221 | PCIE_SPEED_5_0GT = 0x15, | |
9dfd97fe | 222 | PCIE_SPEED_8_0GT = 0x16, |
536c8cb4 MW |
223 | PCI_SPEED_UNKNOWN = 0xff, |
224 | }; | |
225 | ||
24a4742f | 226 | struct pci_cap_saved_data { |
41017f0c | 227 | char cap_nr; |
24a4742f | 228 | unsigned int size; |
41017f0c SL |
229 | u32 data[0]; |
230 | }; | |
231 | ||
24a4742f AW |
232 | struct pci_cap_saved_state { |
233 | struct hlist_node next; | |
234 | struct pci_cap_saved_data cap; | |
235 | }; | |
236 | ||
7d715a6c | 237 | struct pcie_link_state; |
ee69439c | 238 | struct pci_vpd; |
d1b054da | 239 | struct pci_sriov; |
302b4215 | 240 | struct pci_ats; |
ee69439c | 241 | |
1da177e4 LT |
242 | /* |
243 | * The pci_dev structure is used to describe PCI devices. | |
244 | */ | |
245 | struct pci_dev { | |
1da177e4 LT |
246 | struct list_head bus_list; /* node in per-bus list */ |
247 | struct pci_bus *bus; /* bus this device is on */ | |
248 | struct pci_bus *subordinate; /* bus this device bridges to */ | |
249 | ||
250 | void *sysdata; /* hook for sys-specific extension */ | |
251 | struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ | |
f46753c5 | 252 | struct pci_slot *slot; /* Physical slot this device is in */ |
1da177e4 LT |
253 | |
254 | unsigned int devfn; /* encoded device & function index */ | |
255 | unsigned short vendor; | |
256 | unsigned short device; | |
257 | unsigned short subsystem_vendor; | |
258 | unsigned short subsystem_device; | |
259 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ | |
b8a3a521 | 260 | u8 revision; /* PCI revision, low byte of class word */ |
1da177e4 | 261 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
0efea000 | 262 | u8 pcie_cap; /* PCI-E capability offset */ |
e375b561 GS |
263 | u8 msi_cap; /* MSI capability offset */ |
264 | u8 msix_cap; /* MSI-X capability offset */ | |
b03e7495 | 265 | u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ |
1da177e4 | 266 | u8 rom_base_reg; /* which config register controls the ROM */ |
ffeff788 | 267 | u8 pin; /* which interrupt pin this device uses */ |
786e2288 | 268 | u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */ |
1da177e4 LT |
269 | |
270 | struct pci_driver *driver; /* which driver has allocated this device */ | |
271 | u64 dma_mask; /* Mask of the bits of bus address this | |
272 | device implements. Normally this is | |
273 | 0xffffffff. You only need to change | |
274 | this if your device has broken DMA | |
275 | or supports 64-bit transfers. */ | |
276 | ||
4d57cdfa FT |
277 | struct device_dma_parameters dma_parms; |
278 | ||
1da177e4 LT |
279 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
280 | this is D0-D3, D0 being fully functional, | |
281 | and D3 being off. */ | |
703860ed | 282 | u8 pm_cap; /* PM capability offset */ |
337001b6 RW |
283 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
284 | can be generated */ | |
c7f48656 | 285 | unsigned int pme_interrupt:1; |
379021d5 | 286 | unsigned int pme_poll:1; /* Poll device's PME status bit */ |
337001b6 RW |
287 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
288 | unsigned int d2_support:1; /* Low power state D2 is supported */ | |
448bd857 HY |
289 | unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ |
290 | unsigned int no_d3cold:1; /* D3cold is forbidden */ | |
291 | unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ | |
253d2e54 JP |
292 | unsigned int mmio_always_on:1; /* disallow turning off io/mem |
293 | decoding during bar sizing */ | |
e80bb09d | 294 | unsigned int wakeup_prepared:1; |
448bd857 HY |
295 | unsigned int runtime_d3cold:1; /* whether go through runtime |
296 | D3cold, not set for devices | |
297 | powered on/off by the | |
298 | corresponding bridge */ | |
1ae861e6 | 299 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
448bd857 | 300 | unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ |
1da177e4 | 301 | |
7d715a6c SL |
302 | #ifdef CONFIG_PCIEASPM |
303 | struct pcie_link_state *link_state; /* ASPM link state. */ | |
304 | #endif | |
305 | ||
392a1ce7 | 306 | pci_channel_state_t error_state; /* current connectivity state */ |
1da177e4 LT |
307 | struct device dev; /* Generic device interface */ |
308 | ||
1da177e4 LT |
309 | int cfg_size; /* Size of configuration space */ |
310 | ||
311 | /* | |
312 | * Instead of touching interrupt line and base address registers | |
313 | * directly, use the values stored here. They might be different! | |
314 | */ | |
315 | unsigned int irq; | |
316 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ | |
317 | ||
58d9a38f | 318 | bool match_driver; /* Skip attaching driver */ |
1da177e4 LT |
319 | /* These fields are used by common fixups */ |
320 | unsigned int transparent:1; /* Transparent PCI bridge */ | |
321 | unsigned int multifunction:1;/* Part of multi-function device */ | |
322 | /* keep track of device state */ | |
8a1bc901 | 323 | unsigned int is_added:1; |
1da177e4 | 324 | unsigned int is_busmaster:1; /* device is busmaster */ |
4602b88d | 325 | unsigned int no_msi:1; /* device may not use msi */ |
fb51ccbf | 326 | unsigned int block_cfg_access:1; /* config space access is blocked */ |
bd8481e1 | 327 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
e1d3a908 | 328 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
99dc804d SL |
329 | unsigned int msi_enabled:1; |
330 | unsigned int msix_enabled:1; | |
58c3a727 | 331 | unsigned int ari_enabled:1; /* ARI forwarding */ |
9ac7849e | 332 | unsigned int is_managed:1; |
6d3be84a KK |
333 | unsigned int is_pcie:1; /* Obsolete. Will be removed. |
334 | Use pci_is_pcie() instead */ | |
260d703a | 335 | unsigned int needs_freset:1; /* Dev requires fundamental reset */ |
aa8c6c93 | 336 | unsigned int state_saved:1; |
d1b054da | 337 | unsigned int is_physfn:1; |
dd7cc44d | 338 | unsigned int is_virtfn:1; |
711d5779 | 339 | unsigned int reset_fn:1; |
28760489 | 340 | unsigned int is_hotplug_bridge:1; |
affb72c3 HY |
341 | unsigned int __aer_firmware_first_valid:1; |
342 | unsigned int __aer_firmware_first:1; | |
fbebb9fd | 343 | unsigned int broken_intx_masking:1; |
2b28ae19 | 344 | unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ |
ba698ad4 | 345 | pci_dev_flags_t dev_flags; |
bae94d02 | 346 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
4602b88d | 347 | |
1da177e4 | 348 | u32 saved_config_space[16]; /* config space saved at suspend time */ |
41017f0c | 349 | struct hlist_head saved_cap_space; |
1da177e4 LT |
350 | struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
351 | int rom_attr_enabled; /* has display of the rom attribute been enabled? */ | |
352 | struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ | |
45aec1ae | 353 | struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
ded86d8d | 354 | #ifdef CONFIG_PCI_MSI |
4aa9bc95 | 355 | struct list_head msi_list; |
da8d1c8b | 356 | struct kset *msi_kset; |
ded86d8d | 357 | #endif |
94e61088 | 358 | struct pci_vpd *vpd; |
466b3ddf | 359 | #ifdef CONFIG_PCI_ATS |
dd7cc44d YZ |
360 | union { |
361 | struct pci_sriov *sriov; /* SR-IOV capability related */ | |
362 | struct pci_dev *physfn; /* the PF this VF is associated with */ | |
363 | }; | |
302b4215 | 364 | struct pci_ats *ats; /* Address Translation Service */ |
d1b054da | 365 | #endif |
dbd3fc33 | 366 | phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ |
84c1b80e | 367 | size_t romlen; /* Length of ROM if it's not from the BAR */ |
1da177e4 LT |
368 | }; |
369 | ||
dda56549 Y |
370 | static inline struct pci_dev *pci_physfn(struct pci_dev *dev) |
371 | { | |
372 | #ifdef CONFIG_PCI_IOV | |
373 | if (dev->is_virtfn) | |
374 | dev = dev->physfn; | |
375 | #endif | |
376 | ||
377 | return dev; | |
378 | } | |
379 | ||
3c6e6ae7 GZ |
380 | struct pci_dev *pci_alloc_dev(struct pci_bus *bus); |
381 | struct pci_dev * __deprecated alloc_pci_dev(void); | |
65891215 | 382 | |
1da177e4 LT |
383 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
384 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) | |
385 | ||
a7369f1f LV |
386 | static inline int pci_channel_offline(struct pci_dev *pdev) |
387 | { | |
388 | return (pdev->error_state != pci_channel_io_normal); | |
389 | } | |
390 | ||
67cdc827 YL |
391 | extern struct resource busn_resource; |
392 | ||
0efd5aab BH |
393 | struct pci_host_bridge_window { |
394 | struct list_head list; | |
395 | struct resource *res; /* host bridge aperture (CPU address) */ | |
396 | resource_size_t offset; /* bus address + offset = CPU address */ | |
397 | }; | |
41017f0c | 398 | |
5a21d70d | 399 | struct pci_host_bridge { |
7b543663 | 400 | struct device dev; |
5a21d70d | 401 | struct pci_bus *bus; /* root bus */ |
0efd5aab | 402 | struct list_head windows; /* pci_host_bridge_windows */ |
4fa2649a YL |
403 | void (*release_fn)(struct pci_host_bridge *); |
404 | void *release_data; | |
5a21d70d | 405 | }; |
41017f0c | 406 | |
7b543663 | 407 | #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) |
4fa2649a YL |
408 | void pci_set_host_bridge_release(struct pci_host_bridge *bridge, |
409 | void (*release_fn)(struct pci_host_bridge *), | |
410 | void *release_data); | |
7b543663 | 411 | |
6c0cc950 RW |
412 | int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); |
413 | ||
2fe2abf8 BH |
414 | /* |
415 | * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond | |
416 | * to P2P or CardBus bridge windows) go in a table. Additional ones (for | |
417 | * buses below host bridges or subtractive decode bridges) go in the list. | |
418 | * Use pci_bus_for_each_resource() to iterate through all the resources. | |
419 | */ | |
420 | ||
421 | /* | |
422 | * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly | |
423 | * and there's no way to program the bridge with the details of the window. | |
424 | * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- | |
425 | * decode bit set, because they are explicit and can be programmed with _SRS. | |
426 | */ | |
427 | #define PCI_SUBTRACTIVE_DECODE 0x1 | |
428 | ||
429 | struct pci_bus_resource { | |
430 | struct list_head list; | |
431 | struct resource *res; | |
432 | unsigned int flags; | |
433 | }; | |
4352dfd5 GKH |
434 | |
435 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ | |
1da177e4 LT |
436 | |
437 | struct pci_bus { | |
438 | struct list_head node; /* node in list of buses */ | |
439 | struct pci_bus *parent; /* parent bus this bridge is on */ | |
440 | struct list_head children; /* list of child buses */ | |
441 | struct list_head devices; /* list of devices on this bus */ | |
442 | struct pci_dev *self; /* bridge device as seen by parent */ | |
f46753c5 | 443 | struct list_head slots; /* list of slots on this bus */ |
2fe2abf8 BH |
444 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
445 | struct list_head resources; /* address space routed to this bus */ | |
92f02430 | 446 | struct resource busn_res; /* bus numbers routed to this bus */ |
1da177e4 LT |
447 | |
448 | struct pci_ops *ops; /* configuration access functions */ | |
0cbdcfcf | 449 | struct msi_chip *msi; /* MSI controller */ |
1da177e4 LT |
450 | void *sysdata; /* hook for sys-specific extension */ |
451 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ | |
452 | ||
453 | unsigned char number; /* bus number */ | |
454 | unsigned char primary; /* number of primary bridge */ | |
3749c51a MW |
455 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
456 | unsigned char cur_bus_speed; /* enum pci_bus_speed */ | |
1da177e4 LT |
457 | |
458 | char name[48]; | |
459 | ||
460 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ | |
6e325a62 | 461 | pci_bus_flags_t bus_flags; /* Inherited by child busses */ |
1da177e4 | 462 | struct device *bridge; |
fd7d1ced | 463 | struct device dev; |
1da177e4 LT |
464 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
465 | struct bin_attribute *legacy_mem; /* legacy mem */ | |
cc74d96f | 466 | unsigned int is_added:1; |
1da177e4 LT |
467 | }; |
468 | ||
469 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) | |
fd7d1ced | 470 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
1da177e4 | 471 | |
79af72d7 KK |
472 | /* |
473 | * Returns true if the pci bus is root (behind host-pci bridge), | |
474 | * false otherwise | |
475 | */ | |
476 | static inline bool pci_is_root_bus(struct pci_bus *pbus) | |
477 | { | |
478 | return !(pbus->parent); | |
479 | } | |
480 | ||
16cf0ebc RW |
481 | #ifdef CONFIG_PCI_MSI |
482 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) | |
483 | { | |
484 | return pci_dev->msi_enabled || pci_dev->msix_enabled; | |
485 | } | |
486 | #else | |
487 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } | |
488 | #endif | |
489 | ||
1da177e4 LT |
490 | /* |
491 | * Error values that may be returned by PCI functions. | |
492 | */ | |
493 | #define PCIBIOS_SUCCESSFUL 0x00 | |
494 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 | |
495 | #define PCIBIOS_BAD_VENDOR_ID 0x83 | |
496 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 | |
497 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 | |
498 | #define PCIBIOS_SET_FAILED 0x88 | |
499 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 | |
500 | ||
a6961651 AW |
501 | /* |
502 | * Translate above to generic errno for passing back through non-pci. | |
503 | */ | |
504 | static inline int pcibios_err_to_errno(int err) | |
505 | { | |
506 | if (err <= PCIBIOS_SUCCESSFUL) | |
507 | return err; /* Assume already errno */ | |
508 | ||
509 | switch (err) { | |
510 | case PCIBIOS_FUNC_NOT_SUPPORTED: | |
511 | return -ENOENT; | |
512 | case PCIBIOS_BAD_VENDOR_ID: | |
513 | return -EINVAL; | |
514 | case PCIBIOS_DEVICE_NOT_FOUND: | |
515 | return -ENODEV; | |
516 | case PCIBIOS_BAD_REGISTER_NUMBER: | |
517 | return -EFAULT; | |
518 | case PCIBIOS_SET_FAILED: | |
519 | return -EIO; | |
520 | case PCIBIOS_BUFFER_TOO_SMALL: | |
521 | return -ENOSPC; | |
522 | } | |
523 | ||
524 | return -ENOTTY; | |
525 | } | |
526 | ||
1da177e4 LT |
527 | /* Low-level architecture-dependent routines */ |
528 | ||
529 | struct pci_ops { | |
530 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); | |
531 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); | |
532 | }; | |
533 | ||
b6ce068a MW |
534 | /* |
535 | * ACPI needs to be able to access PCI config space before we've done a | |
536 | * PCI bus scan and created pci_bus structures. | |
537 | */ | |
f39d5b72 BH |
538 | int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, |
539 | int reg, int len, u32 *val); | |
540 | int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, | |
541 | int reg, int len, u32 val); | |
1da177e4 LT |
542 | |
543 | struct pci_bus_region { | |
c40a22e0 BH |
544 | resource_size_t start; |
545 | resource_size_t end; | |
1da177e4 LT |
546 | }; |
547 | ||
548 | struct pci_dynids { | |
549 | spinlock_t lock; /* protects list, index */ | |
550 | struct list_head list; /* for IDs added at runtime */ | |
1da177e4 LT |
551 | }; |
552 | ||
392a1ce7 | 553 | /* ---------------------------------------------------------------- */ |
554 | /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides | |
579082df | 555 | * a set of callbacks in struct pci_error_handlers, then that device driver |
392a1ce7 | 556 | * will be notified of PCI bus errors, and will be driven to recovery |
557 | * when an error occurs. | |
558 | */ | |
559 | ||
560 | typedef unsigned int __bitwise pci_ers_result_t; | |
561 | ||
562 | enum pci_ers_result { | |
563 | /* no result/none/not supported in device driver */ | |
564 | PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, | |
565 | ||
566 | /* Device driver can recover without slot reset */ | |
567 | PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, | |
568 | ||
569 | /* Device driver wants slot to be reset. */ | |
570 | PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, | |
571 | ||
572 | /* Device has completely failed, is unrecoverable */ | |
573 | PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, | |
574 | ||
575 | /* Device driver is fully recovered and operational */ | |
576 | PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, | |
918b4053 VMP |
577 | |
578 | /* No AER capabilities registered for the driver */ | |
579 | PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, | |
392a1ce7 | 580 | }; |
581 | ||
582 | /* PCI bus error event callbacks */ | |
05cca6e5 | 583 | struct pci_error_handlers { |
392a1ce7 | 584 | /* PCI bus error detected on this device */ |
585 | pci_ers_result_t (*error_detected)(struct pci_dev *dev, | |
05cca6e5 | 586 | enum pci_channel_state error); |
392a1ce7 | 587 | |
588 | /* MMIO has been re-enabled, but not DMA */ | |
589 | pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); | |
590 | ||
591 | /* PCI Express link has been reset */ | |
592 | pci_ers_result_t (*link_reset)(struct pci_dev *dev); | |
593 | ||
594 | /* PCI slot has been reset */ | |
595 | pci_ers_result_t (*slot_reset)(struct pci_dev *dev); | |
596 | ||
597 | /* Device driver may resume normal operations */ | |
598 | void (*resume)(struct pci_dev *dev); | |
599 | }; | |
600 | ||
601 | /* ---------------------------------------------------------------- */ | |
602 | ||
1da177e4 LT |
603 | struct module; |
604 | struct pci_driver { | |
605 | struct list_head node; | |
42b21932 | 606 | const char *name; |
1da177e4 LT |
607 | const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ |
608 | int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ | |
609 | void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ | |
610 | int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ | |
cbd69dbb LT |
611 | int (*suspend_late) (struct pci_dev *dev, pm_message_t state); |
612 | int (*resume_early) (struct pci_dev *dev); | |
1da177e4 | 613 | int (*resume) (struct pci_dev *dev); /* Device woken up */ |
c8958177 | 614 | void (*shutdown) (struct pci_dev *dev); |
1789382a | 615 | int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ |
49453028 | 616 | const struct pci_error_handlers *err_handler; |
1da177e4 LT |
617 | struct device_driver driver; |
618 | struct pci_dynids dynids; | |
619 | }; | |
620 | ||
05cca6e5 | 621 | #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) |
1da177e4 | 622 | |
90a1ba0c | 623 | /** |
9f9351bb | 624 | * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table |
90a1ba0c JB |
625 | * @_table: device table name |
626 | * | |
627 | * This macro is used to create a struct pci_device_id array (a device table) | |
628 | * in a generic manner. | |
629 | */ | |
9f9351bb | 630 | #define DEFINE_PCI_DEVICE_TABLE(_table) \ |
15856ad5 | 631 | const struct pci_device_id _table[] |
90a1ba0c | 632 | |
1da177e4 LT |
633 | /** |
634 | * PCI_DEVICE - macro used to describe a specific pci device | |
635 | * @vend: the 16 bit PCI Vendor ID | |
636 | * @dev: the 16 bit PCI Device ID | |
637 | * | |
638 | * This macro is used to create a struct pci_device_id that matches a | |
639 | * specific device. The subvendor and subdevice fields will be set to | |
640 | * PCI_ANY_ID. | |
641 | */ | |
642 | #define PCI_DEVICE(vend,dev) \ | |
643 | .vendor = (vend), .device = (dev), \ | |
644 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
645 | ||
3d567e0e NNS |
646 | /** |
647 | * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem | |
648 | * @vend: the 16 bit PCI Vendor ID | |
649 | * @dev: the 16 bit PCI Device ID | |
650 | * @subvend: the 16 bit PCI Subvendor ID | |
651 | * @subdev: the 16 bit PCI Subdevice ID | |
652 | * | |
653 | * This macro is used to create a struct pci_device_id that matches a | |
654 | * specific device with subsystem information. | |
655 | */ | |
656 | #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ | |
657 | .vendor = (vend), .device = (dev), \ | |
658 | .subvendor = (subvend), .subdevice = (subdev) | |
659 | ||
1da177e4 LT |
660 | /** |
661 | * PCI_DEVICE_CLASS - macro used to describe a specific pci device class | |
662 | * @dev_class: the class, subclass, prog-if triple for this device | |
663 | * @dev_class_mask: the class mask for this device | |
664 | * | |
665 | * This macro is used to create a struct pci_device_id that matches a | |
4352dfd5 | 666 | * specific PCI class. The vendor, device, subvendor, and subdevice |
1da177e4 LT |
667 | * fields will be set to PCI_ANY_ID. |
668 | */ | |
669 | #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ | |
670 | .class = (dev_class), .class_mask = (dev_class_mask), \ | |
671 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ | |
672 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
673 | ||
1597cacb AC |
674 | /** |
675 | * PCI_VDEVICE - macro used to describe a specific pci device in short form | |
c322b28a ZY |
676 | * @vendor: the vendor name |
677 | * @device: the 16 bit PCI Device ID | |
1597cacb AC |
678 | * |
679 | * This macro is used to create a struct pci_device_id that matches a | |
680 | * specific PCI device. The subvendor, and subdevice fields will be set | |
681 | * to PCI_ANY_ID. The macro allows the next field to follow as the device | |
682 | * private data. | |
683 | */ | |
684 | ||
685 | #define PCI_VDEVICE(vendor, device) \ | |
686 | PCI_VENDOR_ID_##vendor, (device), \ | |
687 | PCI_ANY_ID, PCI_ANY_ID, 0, 0 | |
688 | ||
1da177e4 LT |
689 | /* these external functions are only available when PCI support is enabled */ |
690 | #ifdef CONFIG_PCI | |
691 | ||
a58674ff | 692 | void pcie_bus_configure_settings(struct pci_bus *bus); |
b03e7495 JM |
693 | |
694 | enum pcie_bus_config_types { | |
5f39e670 | 695 | PCIE_BUS_TUNE_OFF, |
b03e7495 | 696 | PCIE_BUS_SAFE, |
5f39e670 | 697 | PCIE_BUS_PERFORMANCE, |
b03e7495 JM |
698 | PCIE_BUS_PEER2PEER, |
699 | }; | |
700 | ||
701 | extern enum pcie_bus_config_types pcie_bus_config; | |
702 | ||
1da177e4 LT |
703 | extern struct bus_type pci_bus_type; |
704 | ||
705 | /* Do NOT directly access these two variables, unless you are arch specific pci | |
706 | * code, or pci core code. */ | |
707 | extern struct list_head pci_root_buses; /* list of all known PCI buses */ | |
ed4aaadb | 708 | /* Some device drivers need know if pci is initiated */ |
f39d5b72 | 709 | int no_pci_devices(void); |
1da177e4 | 710 | |
3c449ed0 | 711 | void pcibios_resource_survey_bus(struct pci_bus *bus); |
10a95747 JL |
712 | void pcibios_add_bus(struct pci_bus *bus); |
713 | void pcibios_remove_bus(struct pci_bus *bus); | |
1da177e4 | 714 | void pcibios_fixup_bus(struct pci_bus *); |
4a7fb636 | 715 | int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
2b6f2c35 | 716 | /* Architecture specific versions may override this (weak) */ |
05cca6e5 | 717 | char *pcibios_setup(char *str); |
1da177e4 LT |
718 | |
719 | /* Used only when drivers/pci/setup.c is used */ | |
3b7a17fc | 720 | resource_size_t pcibios_align_resource(void *, const struct resource *, |
b26b2d49 | 721 | resource_size_t, |
e31dd6e4 | 722 | resource_size_t); |
1da177e4 LT |
723 | void pcibios_update_irq(struct pci_dev *, int irq); |
724 | ||
2d1c8618 BH |
725 | /* Weak but can be overriden by arch */ |
726 | void pci_fixup_cardbus(struct pci_bus *); | |
727 | ||
1da177e4 LT |
728 | /* Generic PCI functions used internally */ |
729 | ||
36a66cd6 BH |
730 | void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, |
731 | struct resource *res); | |
732 | void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, | |
733 | struct pci_bus_region *region); | |
d1fd4fb6 | 734 | void pcibios_scan_specific_bus(int busn); |
f39d5b72 | 735 | struct pci_bus *pci_find_bus(int domain, int busnr); |
c48f1670 | 736 | void pci_bus_add_devices(const struct pci_bus *bus); |
05cca6e5 GKH |
737 | struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, |
738 | struct pci_ops *ops, void *sysdata); | |
de4b2f76 | 739 | struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); |
166c6370 BH |
740 | struct pci_bus *pci_create_root_bus(struct device *parent, int bus, |
741 | struct pci_ops *ops, void *sysdata, | |
742 | struct list_head *resources); | |
98a35831 YL |
743 | int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); |
744 | int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); | |
745 | void pci_bus_release_busn_res(struct pci_bus *b); | |
15856ad5 | 746 | struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, |
a2ebb827 BH |
747 | struct pci_ops *ops, void *sysdata, |
748 | struct list_head *resources); | |
05cca6e5 GKH |
749 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, |
750 | int busnr); | |
3749c51a | 751 | void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); |
f46753c5 | 752 | struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, |
828f3768 AC |
753 | const char *name, |
754 | struct hotplug_slot *hotplug); | |
f46753c5 | 755 | void pci_destroy_slot(struct pci_slot *slot); |
d25b7c8d | 756 | void pci_renumber_slot(struct pci_slot *slot, int slot_nr); |
1da177e4 | 757 | int pci_scan_slot(struct pci_bus *bus, int devfn); |
05cca6e5 | 758 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); |
cdb9b9f7 | 759 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
1da177e4 | 760 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
b19441af | 761 | int __must_check pci_bus_add_device(struct pci_dev *dev); |
1da177e4 | 762 | void pci_read_bridge_bases(struct pci_bus *child); |
05cca6e5 GKH |
763 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
764 | struct resource *res); | |
3df425f3 | 765 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); |
1da177e4 | 766 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
68feac87 | 767 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); |
f39d5b72 BH |
768 | struct pci_dev *pci_dev_get(struct pci_dev *dev); |
769 | void pci_dev_put(struct pci_dev *dev); | |
770 | void pci_remove_bus(struct pci_bus *b); | |
771 | void pci_stop_and_remove_bus_device(struct pci_dev *dev); | |
cdfcc572 YL |
772 | void pci_stop_root_bus(struct pci_bus *bus); |
773 | void pci_remove_root_bus(struct pci_bus *bus); | |
b3743fa4 | 774 | void pci_setup_cardbus(struct pci_bus *bus); |
f39d5b72 | 775 | void pci_sort_breadthfirst(void); |
fb8a0d9d WM |
776 | #define dev_is_pci(d) ((d)->bus == &pci_bus_type) |
777 | #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) | |
778 | #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) | |
1da177e4 LT |
779 | |
780 | /* Generic PCI functions exported to card drivers */ | |
781 | ||
388c8c16 JB |
782 | enum pci_lost_interrupt_reason { |
783 | PCI_LOST_IRQ_NO_INFORMATION = 0, | |
784 | PCI_LOST_IRQ_DISABLE_MSI, | |
785 | PCI_LOST_IRQ_DISABLE_MSIX, | |
786 | PCI_LOST_IRQ_DISABLE_ACPI, | |
787 | }; | |
788 | enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); | |
05cca6e5 GKH |
789 | int pci_find_capability(struct pci_dev *dev, int cap); |
790 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); | |
791 | int pci_find_ext_capability(struct pci_dev *dev, int cap); | |
44a9a36f | 792 | int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); |
05cca6e5 GKH |
793 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); |
794 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); | |
29f3eb64 | 795 | struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
1da177e4 | 796 | |
d42552c3 AM |
797 | struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
798 | struct pci_dev *from); | |
05cca6e5 | 799 | struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, |
1da177e4 | 800 | unsigned int ss_vendor, unsigned int ss_device, |
b08508c4 | 801 | struct pci_dev *from); |
05cca6e5 | 802 | struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); |
3c299dc2 AP |
803 | struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, |
804 | unsigned int devfn); | |
805 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, | |
806 | unsigned int devfn) | |
807 | { | |
808 | return pci_get_domain_bus_and_slot(0, bus, devfn); | |
809 | } | |
05cca6e5 | 810 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
1da177e4 LT |
811 | int pci_dev_present(const struct pci_device_id *ids); |
812 | ||
05cca6e5 GKH |
813 | int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, |
814 | int where, u8 *val); | |
815 | int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, | |
816 | int where, u16 *val); | |
817 | int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, | |
818 | int where, u32 *val); | |
819 | int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, | |
820 | int where, u8 val); | |
821 | int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, | |
822 | int where, u16 val); | |
823 | int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, | |
824 | int where, u32 val); | |
a72b46c3 | 825 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); |
1da177e4 | 826 | |
bf362f75 | 827 | static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) |
1da177e4 | 828 | { |
05cca6e5 | 829 | return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 | 830 | } |
bf362f75 | 831 | static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) |
1da177e4 | 832 | { |
05cca6e5 | 833 | return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 834 | } |
bf362f75 | 835 | static inline int pci_read_config_dword(const struct pci_dev *dev, int where, |
05cca6e5 | 836 | u32 *val) |
1da177e4 | 837 | { |
05cca6e5 | 838 | return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 | 839 | } |
bf362f75 | 840 | static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) |
1da177e4 | 841 | { |
05cca6e5 | 842 | return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 | 843 | } |
bf362f75 | 844 | static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) |
1da177e4 | 845 | { |
05cca6e5 | 846 | return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 847 | } |
bf362f75 | 848 | static inline int pci_write_config_dword(const struct pci_dev *dev, int where, |
05cca6e5 | 849 | u32 val) |
1da177e4 | 850 | { |
05cca6e5 | 851 | return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
852 | } |
853 | ||
8c0d3a02 JL |
854 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); |
855 | int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); | |
856 | int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); | |
857 | int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); | |
858 | int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, | |
859 | u16 clear, u16 set); | |
860 | int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, | |
861 | u32 clear, u32 set); | |
862 | ||
863 | static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, | |
864 | u16 set) | |
865 | { | |
866 | return pcie_capability_clear_and_set_word(dev, pos, 0, set); | |
867 | } | |
868 | ||
869 | static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, | |
870 | u32 set) | |
871 | { | |
872 | return pcie_capability_clear_and_set_dword(dev, pos, 0, set); | |
873 | } | |
874 | ||
875 | static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, | |
876 | u16 clear) | |
877 | { | |
878 | return pcie_capability_clear_and_set_word(dev, pos, clear, 0); | |
879 | } | |
880 | ||
881 | static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, | |
882 | u32 clear) | |
883 | { | |
884 | return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); | |
885 | } | |
886 | ||
c63587d7 AW |
887 | /* user-space driven config access */ |
888 | int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); | |
889 | int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); | |
890 | int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); | |
891 | int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); | |
892 | int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); | |
893 | int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); | |
894 | ||
4a7fb636 | 895 | int __must_check pci_enable_device(struct pci_dev *dev); |
b718989d BH |
896 | int __must_check pci_enable_device_io(struct pci_dev *dev); |
897 | int __must_check pci_enable_device_mem(struct pci_dev *dev); | |
0b62e13b | 898 | int __must_check pci_reenable_device(struct pci_dev *); |
9ac7849e TH |
899 | int __must_check pcim_enable_device(struct pci_dev *pdev); |
900 | void pcim_pin_device(struct pci_dev *pdev); | |
901 | ||
296ccb08 YS |
902 | static inline int pci_is_enabled(struct pci_dev *pdev) |
903 | { | |
904 | return (atomic_read(&pdev->enable_cnt) > 0); | |
905 | } | |
906 | ||
9ac7849e TH |
907 | static inline int pci_is_managed(struct pci_dev *pdev) |
908 | { | |
909 | return pdev->is_managed; | |
910 | } | |
911 | ||
1da177e4 | 912 | void pci_disable_device(struct pci_dev *dev); |
96c55900 MS |
913 | |
914 | extern unsigned int pcibios_max_latency; | |
1da177e4 | 915 | void pci_set_master(struct pci_dev *dev); |
6a479079 | 916 | void pci_clear_master(struct pci_dev *dev); |
96c55900 | 917 | |
f7bdd12d | 918 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
15ea76d4 | 919 | int pci_set_cacheline_size(struct pci_dev *dev); |
1da177e4 | 920 | #define HAVE_PCI_SET_MWI |
4a7fb636 | 921 | int __must_check pci_set_mwi(struct pci_dev *dev); |
694625c0 | 922 | int pci_try_set_mwi(struct pci_dev *dev); |
1da177e4 | 923 | void pci_clear_mwi(struct pci_dev *dev); |
a04ce0ff | 924 | void pci_intx(struct pci_dev *dev, int enable); |
a2e27787 JK |
925 | bool pci_intx_mask_supported(struct pci_dev *dev); |
926 | bool pci_check_and_mask_intx(struct pci_dev *dev); | |
927 | bool pci_check_and_unmask_intx(struct pci_dev *dev); | |
f5f2b131 | 928 | void pci_msi_off(struct pci_dev *dev); |
4d57cdfa | 929 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); |
59fc67de | 930 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); |
3775a209 | 931 | int pci_wait_for_pending_transaction(struct pci_dev *dev); |
d556ad4b PO |
932 | int pcix_get_max_mmrbc(struct pci_dev *dev); |
933 | int pcix_get_mmrbc(struct pci_dev *dev); | |
934 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); | |
2637e5b5 | 935 | int pcie_get_readrq(struct pci_dev *dev); |
d556ad4b | 936 | int pcie_set_readrq(struct pci_dev *dev, int rq); |
b03e7495 JM |
937 | int pcie_get_mps(struct pci_dev *dev); |
938 | int pcie_set_mps(struct pci_dev *dev, int mps); | |
81377c8d JK |
939 | int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, |
940 | enum pcie_link_width *width); | |
8c1c699f | 941 | int __pci_reset_function(struct pci_dev *dev); |
a96d627a | 942 | int __pci_reset_function_locked(struct pci_dev *dev); |
8dd7f803 | 943 | int pci_reset_function(struct pci_dev *dev); |
9a3d2b9b | 944 | int pci_probe_reset_slot(struct pci_slot *slot); |
090a3c53 | 945 | int pci_reset_slot(struct pci_slot *slot); |
9a3d2b9b | 946 | int pci_probe_reset_bus(struct pci_bus *bus); |
090a3c53 | 947 | int pci_reset_bus(struct pci_bus *bus); |
64e8674f | 948 | void pci_reset_bridge_secondary_bus(struct pci_dev *dev); |
14add80b | 949 | void pci_update_resource(struct pci_dev *dev, int resno); |
4a7fb636 | 950 | int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
2bbc6942 | 951 | int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); |
c87deff7 | 952 | int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
1da177e4 LT |
953 | |
954 | /* ROM control related routines */ | |
e416de5e AC |
955 | int pci_enable_rom(struct pci_dev *pdev); |
956 | void pci_disable_rom(struct pci_dev *pdev); | |
144a50ea | 957 | void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
1da177e4 | 958 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
97c44836 | 959 | size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); |
fffe01f7 | 960 | void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); |
1da177e4 LT |
961 | |
962 | /* Power management related routines */ | |
963 | int pci_save_state(struct pci_dev *dev); | |
1d3c16a8 | 964 | void pci_restore_state(struct pci_dev *dev); |
ffbdd3f7 AW |
965 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); |
966 | int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state); | |
967 | int pci_load_and_free_saved_state(struct pci_dev *dev, | |
968 | struct pci_saved_state **state); | |
0e5dd46b | 969 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); |
9c8550ee LT |
970 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
971 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); | |
e5899e1b | 972 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); |
5a6c9b60 | 973 | void pci_pme_active(struct pci_dev *dev, bool enable); |
6cbf8214 RW |
974 | int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
975 | bool runtime, bool enable); | |
0235c4fc | 976 | int pci_wake_from_d3(struct pci_dev *dev, bool enable); |
e5899e1b | 977 | pci_power_t pci_target_state(struct pci_dev *dev); |
404cc2d8 RW |
978 | int pci_prepare_to_sleep(struct pci_dev *dev); |
979 | int pci_back_from_sleep(struct pci_dev *dev); | |
b67ea761 | 980 | bool pci_dev_run_wake(struct pci_dev *dev); |
bf4d2908 | 981 | bool pci_check_pme_status(struct pci_dev *dev); |
bf4d2908 | 982 | void pci_pme_wakeup_bus(struct pci_bus *bus); |
1da177e4 | 983 | |
6cbf8214 RW |
984 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
985 | bool enable) | |
986 | { | |
987 | return __pci_enable_wake(dev, state, false, enable); | |
988 | } | |
1da177e4 | 989 | |
b48d4425 JB |
990 | #define PCI_EXP_IDO_REQUEST (1<<0) |
991 | #define PCI_EXP_IDO_COMPLETION (1<<1) | |
992 | void pci_enable_ido(struct pci_dev *dev, unsigned long type); | |
993 | void pci_disable_ido(struct pci_dev *dev, unsigned long type); | |
994 | ||
48a92a81 | 995 | enum pci_obff_signal_type { |
688398bb MS |
996 | PCI_EXP_OBFF_SIGNAL_L0 = 0, |
997 | PCI_EXP_OBFF_SIGNAL_ALWAYS = 1, | |
48a92a81 JB |
998 | }; |
999 | int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type); | |
1000 | void pci_disable_obff(struct pci_dev *dev); | |
1001 | ||
51c2e0a7 JB |
1002 | int pci_enable_ltr(struct pci_dev *dev); |
1003 | void pci_disable_ltr(struct pci_dev *dev); | |
1004 | int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns); | |
1005 | ||
bb209c82 BH |
1006 | /* For use by arch with custom probe code */ |
1007 | void set_pcie_port_type(struct pci_dev *pdev); | |
1008 | void set_pcie_hotplug_bridge(struct pci_dev *pdev); | |
1009 | ||
ce5ccdef | 1010 | /* Functions for PCI Hotplug drivers to use */ |
05cca6e5 | 1011 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); |
2f320521 | 1012 | unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); |
3ed4fd96 | 1013 | unsigned int pci_rescan_bus(struct pci_bus *bus); |
ce5ccdef | 1014 | |
287d19ce SH |
1015 | /* Vital product data routines */ |
1016 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); | |
1017 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); | |
db567943 | 1018 | int pci_vpd_truncate(struct pci_dev *dev, size_t size); |
287d19ce | 1019 | |
1da177e4 | 1020 | /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
925845bd | 1021 | resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); |
ea741551 | 1022 | void pci_bus_assign_resources(const struct pci_bus *bus); |
1da177e4 LT |
1023 | void pci_bus_size_bridges(struct pci_bus *bus); |
1024 | int pci_claim_resource(struct pci_dev *, int); | |
1025 | void pci_assign_unassigned_resources(void); | |
6841ec68 | 1026 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); |
17787940 | 1027 | void pci_assign_unassigned_bus_resources(struct pci_bus *bus); |
39772038 | 1028 | void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); |
1da177e4 | 1029 | void pdev_enable_device(struct pci_dev *); |
842de40d | 1030 | int pci_enable_resources(struct pci_dev *, int mask); |
1da177e4 | 1031 | void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), |
d5341942 | 1032 | int (*)(const struct pci_dev *, u8, u8)); |
1da177e4 | 1033 | #define HAVE_PCI_REQ_REGIONS 2 |
4a7fb636 | 1034 | int __must_check pci_request_regions(struct pci_dev *, const char *); |
e8de1481 | 1035 | int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); |
1da177e4 | 1036 | void pci_release_regions(struct pci_dev *); |
4a7fb636 | 1037 | int __must_check pci_request_region(struct pci_dev *, int, const char *); |
e8de1481 | 1038 | int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); |
1da177e4 | 1039 | void pci_release_region(struct pci_dev *, int); |
c87deff7 | 1040 | int pci_request_selected_regions(struct pci_dev *, int, const char *); |
e8de1481 | 1041 | int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); |
c87deff7 | 1042 | void pci_release_selected_regions(struct pci_dev *, int); |
1da177e4 LT |
1043 | |
1044 | /* drivers/pci/bus.c */ | |
fe830ef6 JL |
1045 | struct pci_bus *pci_bus_get(struct pci_bus *bus); |
1046 | void pci_bus_put(struct pci_bus *bus); | |
45ca9e97 | 1047 | void pci_add_resource(struct list_head *resources, struct resource *res); |
0efd5aab BH |
1048 | void pci_add_resource_offset(struct list_head *resources, struct resource *res, |
1049 | resource_size_t offset); | |
45ca9e97 | 1050 | void pci_free_resource_list(struct list_head *resources); |
2fe2abf8 BH |
1051 | void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); |
1052 | struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); | |
1053 | void pci_bus_remove_resources(struct pci_bus *bus); | |
1054 | ||
89a74ecc | 1055 | #define pci_bus_for_each_resource(bus, res, i) \ |
2fe2abf8 BH |
1056 | for (i = 0; \ |
1057 | (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ | |
1058 | i++) | |
89a74ecc | 1059 | |
4a7fb636 AM |
1060 | int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
1061 | struct resource *res, resource_size_t size, | |
1062 | resource_size_t align, resource_size_t min, | |
1063 | unsigned int type_mask, | |
3b7a17fc DB |
1064 | resource_size_t (*alignf)(void *, |
1065 | const struct resource *, | |
b26b2d49 DB |
1066 | resource_size_t, |
1067 | resource_size_t), | |
4a7fb636 | 1068 | void *alignf_data); |
1da177e4 | 1069 | |
863b18f4 | 1070 | /* Proper probing supporting hot-pluggable devices */ |
725522b5 GKH |
1071 | int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
1072 | const char *mod_name); | |
bba81165 AM |
1073 | |
1074 | /* | |
1075 | * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded | |
1076 | */ | |
1077 | #define pci_register_driver(driver) \ | |
1078 | __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) | |
863b18f4 | 1079 | |
05cca6e5 | 1080 | void pci_unregister_driver(struct pci_driver *dev); |
aad4f400 GKH |
1081 | |
1082 | /** | |
1083 | * module_pci_driver() - Helper macro for registering a PCI driver | |
1084 | * @__pci_driver: pci_driver struct | |
1085 | * | |
1086 | * Helper macro for PCI drivers which do not do anything special in module | |
1087 | * init/exit. This eliminates a lot of boilerplate. Each module may only | |
1088 | * use this macro once, and calling it replaces module_init() and module_exit() | |
1089 | */ | |
1090 | #define module_pci_driver(__pci_driver) \ | |
1091 | module_driver(__pci_driver, pci_register_driver, \ | |
1092 | pci_unregister_driver) | |
1093 | ||
05cca6e5 | 1094 | struct pci_driver *pci_dev_driver(const struct pci_dev *dev); |
9dba910e TH |
1095 | int pci_add_dynid(struct pci_driver *drv, |
1096 | unsigned int vendor, unsigned int device, | |
1097 | unsigned int subvendor, unsigned int subdevice, | |
1098 | unsigned int class, unsigned int class_mask, | |
1099 | unsigned long driver_data); | |
05cca6e5 GKH |
1100 | const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, |
1101 | struct pci_dev *dev); | |
1102 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, | |
1103 | int pass); | |
1da177e4 | 1104 | |
70298c6e | 1105 | void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), |
cecf4864 | 1106 | void *userdata); |
70b9f7dc | 1107 | int pci_cfg_space_size_ext(struct pci_dev *dev); |
ac7dc65a | 1108 | int pci_cfg_space_size(struct pci_dev *dev); |
05cca6e5 | 1109 | unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
e2444273 | 1110 | void pci_setup_bridge(struct pci_bus *bus); |
ac5ad93e GS |
1111 | resource_size_t pcibios_window_alignment(struct pci_bus *bus, |
1112 | unsigned long type); | |
cecf4864 | 1113 | |
3448a19d DA |
1114 | #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) |
1115 | #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) | |
1116 | ||
deb2d2ec | 1117 | int pci_set_vga_state(struct pci_dev *pdev, bool decode, |
3448a19d | 1118 | unsigned int command_bits, u32 flags); |
1da177e4 LT |
1119 | /* kmem_cache style wrapper around pci_alloc_consistent() */ |
1120 | ||
f41b1771 | 1121 | #include <linux/pci-dma.h> |
1da177e4 LT |
1122 | #include <linux/dmapool.h> |
1123 | ||
1124 | #define pci_pool dma_pool | |
1125 | #define pci_pool_create(name, pdev, size, align, allocation) \ | |
1126 | dma_pool_create(name, &pdev->dev, size, align, allocation) | |
1127 | #define pci_pool_destroy(pool) dma_pool_destroy(pool) | |
1128 | #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) | |
1129 | #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) | |
1130 | ||
e24c2d96 DM |
1131 | enum pci_dma_burst_strategy { |
1132 | PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, | |
1133 | strategy_parameter is N/A */ | |
1134 | PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter | |
1135 | byte boundaries */ | |
1136 | PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of | |
1137 | strategy_parameter byte boundaries */ | |
1138 | }; | |
1139 | ||
1da177e4 | 1140 | struct msix_entry { |
16dbef4a | 1141 | u32 vector; /* kernel uses to write allocated vector */ |
1da177e4 LT |
1142 | u16 entry; /* driver uses to specify entry, OS writes */ |
1143 | }; | |
1144 | ||
0366f8f7 | 1145 | |
1da177e4 | 1146 | #ifndef CONFIG_PCI_MSI |
1c8d7b0a | 1147 | static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) |
05cca6e5 GKH |
1148 | { |
1149 | return -1; | |
1150 | } | |
1151 | ||
08261d87 AG |
1152 | static inline int |
1153 | pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec) | |
1154 | { | |
1155 | return -1; | |
1156 | } | |
1157 | ||
d52877c7 YL |
1158 | static inline void pci_msi_shutdown(struct pci_dev *dev) |
1159 | { } | |
05cca6e5 GKH |
1160 | static inline void pci_disable_msi(struct pci_dev *dev) |
1161 | { } | |
1162 | ||
a52e2e35 RW |
1163 | static inline int pci_msix_table_size(struct pci_dev *dev) |
1164 | { | |
1165 | return 0; | |
1166 | } | |
05cca6e5 GKH |
1167 | static inline int pci_enable_msix(struct pci_dev *dev, |
1168 | struct msix_entry *entries, int nvec) | |
1169 | { | |
1170 | return -1; | |
1171 | } | |
1172 | ||
d52877c7 YL |
1173 | static inline void pci_msix_shutdown(struct pci_dev *dev) |
1174 | { } | |
05cca6e5 GKH |
1175 | static inline void pci_disable_msix(struct pci_dev *dev) |
1176 | { } | |
1177 | ||
1178 | static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) | |
1179 | { } | |
1180 | ||
1181 | static inline void pci_restore_msi_state(struct pci_dev *dev) | |
1182 | { } | |
07ae95f9 AP |
1183 | static inline int pci_msi_enabled(void) |
1184 | { | |
1185 | return 0; | |
1186 | } | |
1da177e4 | 1187 | #else |
f39d5b72 BH |
1188 | int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec); |
1189 | int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec); | |
1190 | void pci_msi_shutdown(struct pci_dev *dev); | |
1191 | void pci_disable_msi(struct pci_dev *dev); | |
1192 | int pci_msix_table_size(struct pci_dev *dev); | |
1193 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec); | |
1194 | void pci_msix_shutdown(struct pci_dev *dev); | |
1195 | void pci_disable_msix(struct pci_dev *dev); | |
1196 | void msi_remove_pci_irq_vectors(struct pci_dev *dev); | |
1197 | void pci_restore_msi_state(struct pci_dev *dev); | |
1198 | int pci_msi_enabled(void); | |
1da177e4 LT |
1199 | #endif |
1200 | ||
ab0724ff | 1201 | #ifdef CONFIG_PCIEPORTBUS |
415e12b2 RW |
1202 | extern bool pcie_ports_disabled; |
1203 | extern bool pcie_ports_auto; | |
ab0724ff MT |
1204 | #else |
1205 | #define pcie_ports_disabled true | |
1206 | #define pcie_ports_auto false | |
1207 | #endif | |
415e12b2 | 1208 | |
3e1b1600 | 1209 | #ifndef CONFIG_PCIEASPM |
8b8bae90 RW |
1210 | static inline int pcie_aspm_enabled(void) { return 0; } |
1211 | static inline bool pcie_aspm_support_enabled(void) { return false; } | |
3e1b1600 | 1212 | #else |
f39d5b72 BH |
1213 | int pcie_aspm_enabled(void); |
1214 | bool pcie_aspm_support_enabled(void); | |
3e1b1600 AP |
1215 | #endif |
1216 | ||
415e12b2 RW |
1217 | #ifdef CONFIG_PCIEAER |
1218 | void pci_no_aer(void); | |
1219 | bool pci_aer_available(void); | |
1220 | #else | |
1221 | static inline void pci_no_aer(void) { } | |
1222 | static inline bool pci_aer_available(void) { return false; } | |
1223 | #endif | |
1224 | ||
43c16408 AP |
1225 | #ifndef CONFIG_PCIE_ECRC |
1226 | static inline void pcie_set_ecrc_checking(struct pci_dev *dev) | |
1227 | { | |
1228 | return; | |
1229 | } | |
1230 | static inline void pcie_ecrc_get_policy(char *str) {}; | |
1231 | #else | |
f39d5b72 BH |
1232 | void pcie_set_ecrc_checking(struct pci_dev *dev); |
1233 | void pcie_ecrc_get_policy(char *str); | |
43c16408 AP |
1234 | #endif |
1235 | ||
1c8d7b0a MW |
1236 | #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1) |
1237 | ||
8b955b0d | 1238 | #ifdef CONFIG_HT_IRQ |
8b955b0d EB |
1239 | /* The functions a driver should call */ |
1240 | int ht_create_irq(struct pci_dev *dev, int idx); | |
1241 | void ht_destroy_irq(unsigned int irq); | |
8b955b0d EB |
1242 | #endif /* CONFIG_HT_IRQ */ |
1243 | ||
f39d5b72 BH |
1244 | void pci_cfg_access_lock(struct pci_dev *dev); |
1245 | bool pci_cfg_access_trylock(struct pci_dev *dev); | |
1246 | void pci_cfg_access_unlock(struct pci_dev *dev); | |
e04b0ea2 | 1247 | |
4352dfd5 GKH |
1248 | /* |
1249 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), | |
1250 | * a PCI domain is defined to be a set of PCI busses which share | |
1251 | * configuration space. | |
1252 | */ | |
32a2eea7 JG |
1253 | #ifdef CONFIG_PCI_DOMAINS |
1254 | extern int pci_domains_supported; | |
1255 | #else | |
1256 | enum { pci_domains_supported = 0 }; | |
05cca6e5 GKH |
1257 | static inline int pci_domain_nr(struct pci_bus *bus) |
1258 | { | |
1259 | return 0; | |
1260 | } | |
1261 | ||
4352dfd5 GKH |
1262 | static inline int pci_proc_domain(struct pci_bus *bus) |
1263 | { | |
1264 | return 0; | |
1265 | } | |
32a2eea7 | 1266 | #endif /* CONFIG_PCI_DOMAINS */ |
1da177e4 | 1267 | |
95a8b6ef MT |
1268 | /* some architectures require additional setup to direct VGA traffic */ |
1269 | typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, | |
3448a19d | 1270 | unsigned int command_bits, u32 flags); |
f39d5b72 | 1271 | void pci_register_set_vga_state(arch_set_vga_state_t func); |
95a8b6ef | 1272 | |
4352dfd5 | 1273 | #else /* CONFIG_PCI is not enabled */ |
1da177e4 LT |
1274 | |
1275 | /* | |
1276 | * If the system does not have PCI, clearly these return errors. Define | |
1277 | * these as simple inline functions to avoid hair in drivers. | |
1278 | */ | |
1279 | ||
05cca6e5 GKH |
1280 | #define _PCI_NOP(o, s, t) \ |
1281 | static inline int pci_##o##_config_##s(struct pci_dev *dev, \ | |
1282 | int where, t val) \ | |
1da177e4 | 1283 | { return PCIBIOS_FUNC_NOT_SUPPORTED; } |
05cca6e5 GKH |
1284 | |
1285 | #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ | |
1286 | _PCI_NOP(o, word, u16 x) \ | |
1287 | _PCI_NOP(o, dword, u32 x) | |
1da177e4 LT |
1288 | _PCI_NOP_ALL(read, *) |
1289 | _PCI_NOP_ALL(write,) | |
1290 | ||
d42552c3 | 1291 | static inline struct pci_dev *pci_get_device(unsigned int vendor, |
05cca6e5 GKH |
1292 | unsigned int device, |
1293 | struct pci_dev *from) | |
1294 | { | |
1295 | return NULL; | |
1296 | } | |
d42552c3 | 1297 | |
05cca6e5 GKH |
1298 | static inline struct pci_dev *pci_get_subsys(unsigned int vendor, |
1299 | unsigned int device, | |
1300 | unsigned int ss_vendor, | |
1301 | unsigned int ss_device, | |
b08508c4 | 1302 | struct pci_dev *from) |
05cca6e5 GKH |
1303 | { |
1304 | return NULL; | |
1305 | } | |
1da177e4 | 1306 | |
05cca6e5 GKH |
1307 | static inline struct pci_dev *pci_get_class(unsigned int class, |
1308 | struct pci_dev *from) | |
1309 | { | |
1310 | return NULL; | |
1311 | } | |
1da177e4 LT |
1312 | |
1313 | #define pci_dev_present(ids) (0) | |
ed4aaadb | 1314 | #define no_pci_devices() (1) |
1da177e4 LT |
1315 | #define pci_dev_put(dev) do { } while (0) |
1316 | ||
05cca6e5 GKH |
1317 | static inline void pci_set_master(struct pci_dev *dev) |
1318 | { } | |
1319 | ||
1320 | static inline int pci_enable_device(struct pci_dev *dev) | |
1321 | { | |
1322 | return -EIO; | |
1323 | } | |
1324 | ||
1325 | static inline void pci_disable_device(struct pci_dev *dev) | |
1326 | { } | |
1327 | ||
1328 | static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
1329 | { | |
1330 | return -EIO; | |
1331 | } | |
1332 | ||
80be0385 RD |
1333 | static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) |
1334 | { | |
1335 | return -EIO; | |
1336 | } | |
1337 | ||
4d57cdfa FT |
1338 | static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, |
1339 | unsigned int size) | |
1340 | { | |
1341 | return -EIO; | |
1342 | } | |
1343 | ||
59fc67de FT |
1344 | static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, |
1345 | unsigned long mask) | |
1346 | { | |
1347 | return -EIO; | |
1348 | } | |
1349 | ||
05cca6e5 GKH |
1350 | static inline int pci_assign_resource(struct pci_dev *dev, int i) |
1351 | { | |
1352 | return -EBUSY; | |
1353 | } | |
1354 | ||
1355 | static inline int __pci_register_driver(struct pci_driver *drv, | |
1356 | struct module *owner) | |
1357 | { | |
1358 | return 0; | |
1359 | } | |
1360 | ||
1361 | static inline int pci_register_driver(struct pci_driver *drv) | |
1362 | { | |
1363 | return 0; | |
1364 | } | |
1365 | ||
1366 | static inline void pci_unregister_driver(struct pci_driver *drv) | |
1367 | { } | |
1368 | ||
1369 | static inline int pci_find_capability(struct pci_dev *dev, int cap) | |
1370 | { | |
1371 | return 0; | |
1372 | } | |
1373 | ||
1374 | static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, | |
1375 | int cap) | |
1376 | { | |
1377 | return 0; | |
1378 | } | |
1379 | ||
1380 | static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
1381 | { | |
1382 | return 0; | |
1383 | } | |
1384 | ||
1da177e4 | 1385 | /* Power management related routines */ |
05cca6e5 GKH |
1386 | static inline int pci_save_state(struct pci_dev *dev) |
1387 | { | |
1388 | return 0; | |
1389 | } | |
1390 | ||
1d3c16a8 JM |
1391 | static inline void pci_restore_state(struct pci_dev *dev) |
1392 | { } | |
1da177e4 | 1393 | |
05cca6e5 GKH |
1394 | static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
1395 | { | |
1396 | return 0; | |
1397 | } | |
1398 | ||
3449248c RD |
1399 | static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) |
1400 | { | |
1401 | return 0; | |
1402 | } | |
1403 | ||
05cca6e5 GKH |
1404 | static inline pci_power_t pci_choose_state(struct pci_dev *dev, |
1405 | pm_message_t state) | |
1406 | { | |
1407 | return PCI_D0; | |
1408 | } | |
1409 | ||
1410 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, | |
1411 | int enable) | |
1412 | { | |
1413 | return 0; | |
1414 | } | |
1415 | ||
b48d4425 JB |
1416 | static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type) |
1417 | { | |
1418 | } | |
1419 | ||
1420 | static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type) | |
1421 | { | |
1422 | } | |
1423 | ||
48a92a81 JB |
1424 | static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type) |
1425 | { | |
1426 | return 0; | |
1427 | } | |
1428 | ||
1429 | static inline void pci_disable_obff(struct pci_dev *dev) | |
1430 | { | |
1431 | } | |
1432 | ||
05cca6e5 GKH |
1433 | static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) |
1434 | { | |
1435 | return -EIO; | |
1436 | } | |
1437 | ||
1438 | static inline void pci_release_regions(struct pci_dev *dev) | |
1439 | { } | |
0da0ead9 | 1440 | |
a46e8126 KG |
1441 | #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) |
1442 | ||
fb51ccbf | 1443 | static inline void pci_block_cfg_access(struct pci_dev *dev) |
05cca6e5 GKH |
1444 | { } |
1445 | ||
fb51ccbf JK |
1446 | static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) |
1447 | { return 0; } | |
1448 | ||
1449 | static inline void pci_unblock_cfg_access(struct pci_dev *dev) | |
05cca6e5 | 1450 | { } |
e04b0ea2 | 1451 | |
d80d0217 RD |
1452 | static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
1453 | { return NULL; } | |
1454 | ||
1455 | static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, | |
1456 | unsigned int devfn) | |
1457 | { return NULL; } | |
1458 | ||
1459 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, | |
1460 | unsigned int devfn) | |
1461 | { return NULL; } | |
1462 | ||
92298e66 DA |
1463 | static inline int pci_domain_nr(struct pci_bus *bus) |
1464 | { return 0; } | |
1465 | ||
12ea6cad AW |
1466 | static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) |
1467 | { return NULL; } | |
1468 | ||
fb8a0d9d WM |
1469 | #define dev_is_pci(d) (false) |
1470 | #define dev_is_pf(d) (false) | |
1471 | #define dev_num_vf(d) (0) | |
4352dfd5 | 1472 | #endif /* CONFIG_PCI */ |
1da177e4 | 1473 | |
4352dfd5 GKH |
1474 | /* Include architecture-dependent settings and functions */ |
1475 | ||
1476 | #include <asm/pci.h> | |
1da177e4 | 1477 | |
1f82de10 YL |
1478 | #ifndef PCIBIOS_MAX_MEM_32 |
1479 | #define PCIBIOS_MAX_MEM_32 (-1) | |
1480 | #endif | |
1481 | ||
1da177e4 LT |
1482 | /* these helpers provide future and backwards compatibility |
1483 | * for accessing popular PCI BAR info */ | |
05cca6e5 GKH |
1484 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
1485 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) | |
1486 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) | |
1da177e4 | 1487 | #define pci_resource_len(dev,bar) \ |
05cca6e5 GKH |
1488 | ((pci_resource_start((dev), (bar)) == 0 && \ |
1489 | pci_resource_end((dev), (bar)) == \ | |
1490 | pci_resource_start((dev), (bar))) ? 0 : \ | |
1491 | \ | |
1492 | (pci_resource_end((dev), (bar)) - \ | |
1493 | pci_resource_start((dev), (bar)) + 1)) | |
1da177e4 LT |
1494 | |
1495 | /* Similar to the helpers above, these manipulate per-pci_dev | |
1496 | * driver-specific data. They are really just a wrapper around | |
1497 | * the generic device structure functions of these calls. | |
1498 | */ | |
05cca6e5 | 1499 | static inline void *pci_get_drvdata(struct pci_dev *pdev) |
1da177e4 LT |
1500 | { |
1501 | return dev_get_drvdata(&pdev->dev); | |
1502 | } | |
1503 | ||
05cca6e5 | 1504 | static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) |
1da177e4 LT |
1505 | { |
1506 | dev_set_drvdata(&pdev->dev, data); | |
1507 | } | |
1508 | ||
1509 | /* If you want to know what to call your pci_dev, ask this function. | |
1510 | * Again, it's a wrapper around the generic device. | |
1511 | */ | |
2fc90f61 | 1512 | static inline const char *pci_name(const struct pci_dev *pdev) |
1da177e4 | 1513 | { |
c6c4f070 | 1514 | return dev_name(&pdev->dev); |
1da177e4 LT |
1515 | } |
1516 | ||
2311b1f2 ME |
1517 | |
1518 | /* Some archs don't want to expose struct resource to userland as-is | |
1519 | * in sysfs and /proc | |
1520 | */ | |
1521 | #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER | |
1522 | static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
05cca6e5 | 1523 | const struct resource *rsrc, resource_size_t *start, |
e31dd6e4 | 1524 | resource_size_t *end) |
2311b1f2 ME |
1525 | { |
1526 | *start = rsrc->start; | |
1527 | *end = rsrc->end; | |
1528 | } | |
1529 | #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ | |
1530 | ||
1531 | ||
1da177e4 LT |
1532 | /* |
1533 | * The world is not perfect and supplies us with broken PCI devices. | |
1534 | * For at least a part of these bugs we need a work-around, so both | |
1535 | * generic (drivers/pci/quirks.c) and per-architecture code can define | |
1536 | * fixup hooks to be called for particular buggy devices. | |
1537 | */ | |
1538 | ||
1539 | struct pci_fixup { | |
f4ca5c6a YL |
1540 | u16 vendor; /* You can use PCI_ANY_ID here of course */ |
1541 | u16 device; /* You can use PCI_ANY_ID here of course */ | |
1542 | u32 class; /* You can use PCI_ANY_ID here too */ | |
1543 | unsigned int class_shift; /* should be 0, 8, 16 */ | |
1da177e4 LT |
1544 | void (*hook)(struct pci_dev *dev); |
1545 | }; | |
1546 | ||
1547 | enum pci_fixup_pass { | |
1548 | pci_fixup_early, /* Before probing BARs */ | |
1549 | pci_fixup_header, /* After reading configuration header */ | |
1550 | pci_fixup_final, /* Final phase of device fixups */ | |
1551 | pci_fixup_enable, /* pci_enable_device() time */ | |
e1a2a51e RW |
1552 | pci_fixup_resume, /* pci_device_resume() */ |
1553 | pci_fixup_suspend, /* pci_device_suspend */ | |
1554 | pci_fixup_resume_early, /* pci_device_resume_early() */ | |
1da177e4 LT |
1555 | }; |
1556 | ||
1557 | /* Anonymous variables would be nice... */ | |
f4ca5c6a YL |
1558 | #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ |
1559 | class_shift, hook) \ | |
769ae543 | 1560 | static const struct pci_fixup __pci_fixup_##name __used \ |
f4ca5c6a YL |
1561 | __attribute__((__section__(#section), aligned((sizeof(void *))))) \ |
1562 | = { vendor, device, class, class_shift, hook }; | |
1563 | ||
1564 | #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ | |
1565 | class_shift, hook) \ | |
1566 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
1567 | vendor##device##hook, vendor, device, class, class_shift, hook) | |
1568 | #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ | |
1569 | class_shift, hook) \ | |
1570 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
1571 | vendor##device##hook, vendor, device, class, class_shift, hook) | |
1572 | #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ | |
1573 | class_shift, hook) \ | |
1574 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
1575 | vendor##device##hook, vendor, device, class, class_shift, hook) | |
1576 | #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ | |
1577 | class_shift, hook) \ | |
1578 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
1579 | vendor##device##hook, vendor, device, class, class_shift, hook) | |
1580 | #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ | |
1581 | class_shift, hook) \ | |
1582 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
1583 | resume##vendor##device##hook, vendor, device, class, \ | |
1584 | class_shift, hook) | |
1585 | #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ | |
1586 | class_shift, hook) \ | |
1587 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
1588 | resume_early##vendor##device##hook, vendor, device, \ | |
1589 | class, class_shift, hook) | |
1590 | #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ | |
1591 | class_shift, hook) \ | |
1592 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
1593 | suspend##vendor##device##hook, vendor, device, class, \ | |
1594 | class_shift, hook) | |
1595 | ||
1da177e4 LT |
1596 | #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ |
1597 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
f4ca5c6a | 1598 | vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
1599 | #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ |
1600 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
f4ca5c6a | 1601 | vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
1602 | #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ |
1603 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
f4ca5c6a | 1604 | vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
1605 | #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ |
1606 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
f4ca5c6a | 1607 | vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook) |
1597cacb AC |
1608 | #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
1609 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
f4ca5c6a YL |
1610 | resume##vendor##device##hook, vendor, device, \ |
1611 | PCI_ANY_ID, 0, hook) | |
e1a2a51e RW |
1612 | #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ |
1613 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
f4ca5c6a YL |
1614 | resume_early##vendor##device##hook, vendor, device, \ |
1615 | PCI_ANY_ID, 0, hook) | |
e1a2a51e RW |
1616 | #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ |
1617 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
f4ca5c6a YL |
1618 | suspend##vendor##device##hook, vendor, device, \ |
1619 | PCI_ANY_ID, 0, hook) | |
1da177e4 | 1620 | |
93177a74 | 1621 | #ifdef CONFIG_PCI_QUIRKS |
1da177e4 | 1622 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); |
12ea6cad | 1623 | struct pci_dev *pci_get_dma_source(struct pci_dev *dev); |
ad805758 | 1624 | int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); |
93177a74 RW |
1625 | #else |
1626 | static inline void pci_fixup_device(enum pci_fixup_pass pass, | |
1627 | struct pci_dev *dev) {} | |
12ea6cad AW |
1628 | static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev) |
1629 | { | |
1630 | return pci_dev_get(dev); | |
1631 | } | |
ad805758 AW |
1632 | static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, |
1633 | u16 acs_flags) | |
1634 | { | |
1635 | return -ENOTTY; | |
1636 | } | |
93177a74 | 1637 | #endif |
1da177e4 | 1638 | |
05cca6e5 | 1639 | void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
5ea81769 | 1640 | void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); |
05cca6e5 | 1641 | void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); |
fb7ebfe4 YL |
1642 | int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); |
1643 | int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, | |
916fbfb7 | 1644 | const char *name); |
fb7ebfe4 | 1645 | void pcim_iounmap_regions(struct pci_dev *pdev, int mask); |
5ea81769 | 1646 | |
1da177e4 | 1647 | extern int pci_pci_problems; |
236561e5 | 1648 | #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
1da177e4 LT |
1649 | #define PCIPCI_TRITON 2 |
1650 | #define PCIPCI_NATOMA 4 | |
1651 | #define PCIPCI_VIAETBF 8 | |
1652 | #define PCIPCI_VSFX 16 | |
236561e5 AC |
1653 | #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
1654 | #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ | |
1da177e4 | 1655 | |
4516a618 AN |
1656 | extern unsigned long pci_cardbus_io_size; |
1657 | extern unsigned long pci_cardbus_mem_size; | |
15856ad5 | 1658 | extern u8 pci_dfl_cache_line_size; |
ac1aa47b | 1659 | extern u8 pci_cache_line_size; |
4516a618 | 1660 | |
28760489 EB |
1661 | extern unsigned long pci_hotplug_io_size; |
1662 | extern unsigned long pci_hotplug_mem_size; | |
1663 | ||
cfce9fb8 | 1664 | /* Architecture specific versions may override these (weak) */ |
19792a08 AB |
1665 | int pcibios_add_platform_entries(struct pci_dev *dev); |
1666 | void pcibios_disable_device(struct pci_dev *dev); | |
cfce9fb8 | 1667 | void pcibios_set_master(struct pci_dev *dev); |
19792a08 AB |
1668 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, |
1669 | enum pcie_reset_state state); | |
eca0d467 | 1670 | int pcibios_add_device(struct pci_dev *dev); |
6ae32c53 | 1671 | void pcibios_release_device(struct pci_dev *dev); |
575e3348 | 1672 | |
699c1985 SO |
1673 | #ifdef CONFIG_HIBERNATE_CALLBACKS |
1674 | extern struct dev_pm_ops pcibios_pm_ops; | |
1675 | #endif | |
1676 | ||
7752d5cf | 1677 | #ifdef CONFIG_PCI_MMCONFIG |
f39d5b72 BH |
1678 | void __init pci_mmcfg_early_init(void); |
1679 | void __init pci_mmcfg_late_init(void); | |
7752d5cf | 1680 | #else |
bb63b421 | 1681 | static inline void pci_mmcfg_early_init(void) { } |
7752d5cf RH |
1682 | static inline void pci_mmcfg_late_init(void) { } |
1683 | #endif | |
1684 | ||
642c92da | 1685 | int pci_ext_cfg_avail(void); |
0ef5f8f6 | 1686 | |
1684f5dd | 1687 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); |
aa42d7c6 | 1688 | |
dd7cc44d | 1689 | #ifdef CONFIG_PCI_IOV |
f39d5b72 BH |
1690 | int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); |
1691 | void pci_disable_sriov(struct pci_dev *dev); | |
1692 | irqreturn_t pci_sriov_migration(struct pci_dev *dev); | |
1693 | int pci_num_vf(struct pci_dev *dev); | |
5a8eb242 | 1694 | int pci_vfs_assigned(struct pci_dev *dev); |
f39d5b72 BH |
1695 | int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); |
1696 | int pci_sriov_get_totalvfs(struct pci_dev *dev); | |
dd7cc44d YZ |
1697 | #else |
1698 | static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) | |
1699 | { | |
1700 | return -ENODEV; | |
1701 | } | |
1702 | static inline void pci_disable_sriov(struct pci_dev *dev) | |
1703 | { | |
1704 | } | |
74bb1bcc YZ |
1705 | static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev) |
1706 | { | |
1707 | return IRQ_NONE; | |
1708 | } | |
fb8a0d9d WM |
1709 | static inline int pci_num_vf(struct pci_dev *dev) |
1710 | { | |
1711 | return 0; | |
1712 | } | |
5a8eb242 AD |
1713 | static inline int pci_vfs_assigned(struct pci_dev *dev) |
1714 | { | |
1715 | return 0; | |
1716 | } | |
bff73156 DD |
1717 | static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) |
1718 | { | |
1719 | return 0; | |
1720 | } | |
1721 | static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) | |
1722 | { | |
1723 | return 0; | |
1724 | } | |
dd7cc44d YZ |
1725 | #endif |
1726 | ||
c825bc94 | 1727 | #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) |
f39d5b72 BH |
1728 | void pci_hp_create_module_link(struct pci_slot *pci_slot); |
1729 | void pci_hp_remove_module_link(struct pci_slot *pci_slot); | |
c825bc94 KK |
1730 | #endif |
1731 | ||
d7b7e605 KK |
1732 | /** |
1733 | * pci_pcie_cap - get the saved PCIe capability offset | |
1734 | * @dev: PCI device | |
1735 | * | |
1736 | * PCIe capability offset is calculated at PCI device initialization | |
1737 | * time and saved in the data structure. This function returns saved | |
1738 | * PCIe capability offset. Using this instead of pci_find_capability() | |
1739 | * reduces unnecessary search in the PCI configuration space. If you | |
1740 | * need to calculate PCIe capability offset from raw device for some | |
1741 | * reasons, please use pci_find_capability() instead. | |
1742 | */ | |
1743 | static inline int pci_pcie_cap(struct pci_dev *dev) | |
1744 | { | |
1745 | return dev->pcie_cap; | |
1746 | } | |
1747 | ||
7eb776c4 KK |
1748 | /** |
1749 | * pci_is_pcie - check if the PCI device is PCI Express capable | |
1750 | * @dev: PCI device | |
1751 | * | |
1752 | * Retrun true if the PCI device is PCI Express capable, false otherwise. | |
1753 | */ | |
1754 | static inline bool pci_is_pcie(struct pci_dev *dev) | |
1755 | { | |
1756 | return !!pci_pcie_cap(dev); | |
1757 | } | |
1758 | ||
7c9c003c MS |
1759 | /** |
1760 | * pcie_caps_reg - get the PCIe Capabilities Register | |
1761 | * @dev: PCI device | |
1762 | */ | |
1763 | static inline u16 pcie_caps_reg(const struct pci_dev *dev) | |
1764 | { | |
1765 | return dev->pcie_flags_reg; | |
1766 | } | |
1767 | ||
786e2288 YW |
1768 | /** |
1769 | * pci_pcie_type - get the PCIe device/port type | |
1770 | * @dev: PCI device | |
1771 | */ | |
1772 | static inline int pci_pcie_type(const struct pci_dev *dev) | |
1773 | { | |
1c531d82 | 1774 | return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; |
786e2288 YW |
1775 | } |
1776 | ||
5d990b62 | 1777 | void pci_request_acs(void); |
ad805758 AW |
1778 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); |
1779 | bool pci_acs_path_enabled(struct pci_dev *start, | |
1780 | struct pci_dev *end, u16 acs_flags); | |
a2ce7662 | 1781 | |
7ad506fa MC |
1782 | #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ |
1783 | #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT) | |
1784 | ||
1785 | /* Large Resource Data Type Tag Item Names */ | |
1786 | #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ | |
1787 | #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ | |
1788 | #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ | |
1789 | ||
1790 | #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) | |
1791 | #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) | |
1792 | #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) | |
1793 | ||
1794 | /* Small Resource Data Type Tag Item Names */ | |
1795 | #define PCI_VPD_STIN_END 0x78 /* End */ | |
1796 | ||
1797 | #define PCI_VPD_SRDT_END PCI_VPD_STIN_END | |
1798 | ||
1799 | #define PCI_VPD_SRDT_TIN_MASK 0x78 | |
1800 | #define PCI_VPD_SRDT_LEN_MASK 0x07 | |
1801 | ||
1802 | #define PCI_VPD_LRDT_TAG_SIZE 3 | |
1803 | #define PCI_VPD_SRDT_TAG_SIZE 1 | |
a2ce7662 | 1804 | |
e1d5bdab MC |
1805 | #define PCI_VPD_INFO_FLD_HDR_SIZE 3 |
1806 | ||
4067a854 MC |
1807 | #define PCI_VPD_RO_KEYWORD_PARTNO "PN" |
1808 | #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" | |
1809 | #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" | |
d4894f3e | 1810 | #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" |
4067a854 | 1811 | |
a2ce7662 MC |
1812 | /** |
1813 | * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length | |
1814 | * @lrdt: Pointer to the beginning of the Large Resource Data Type tag | |
1815 | * | |
1816 | * Returns the extracted Large Resource Data Type length. | |
1817 | */ | |
1818 | static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) | |
1819 | { | |
1820 | return (u16)lrdt[1] + ((u16)lrdt[2] << 8); | |
1821 | } | |
1822 | ||
7ad506fa MC |
1823 | /** |
1824 | * pci_vpd_srdt_size - Extracts the Small Resource Data Type length | |
1825 | * @lrdt: Pointer to the beginning of the Small Resource Data Type tag | |
1826 | * | |
1827 | * Returns the extracted Small Resource Data Type length. | |
1828 | */ | |
1829 | static inline u8 pci_vpd_srdt_size(const u8 *srdt) | |
1830 | { | |
1831 | return (*srdt) & PCI_VPD_SRDT_LEN_MASK; | |
1832 | } | |
1833 | ||
e1d5bdab MC |
1834 | /** |
1835 | * pci_vpd_info_field_size - Extracts the information field length | |
1836 | * @lrdt: Pointer to the beginning of an information field header | |
1837 | * | |
1838 | * Returns the extracted information field length. | |
1839 | */ | |
1840 | static inline u8 pci_vpd_info_field_size(const u8 *info_field) | |
1841 | { | |
1842 | return info_field[2]; | |
1843 | } | |
1844 | ||
b55ac1b2 MC |
1845 | /** |
1846 | * pci_vpd_find_tag - Locates the Resource Data Type tag provided | |
1847 | * @buf: Pointer to buffered vpd data | |
1848 | * @off: The offset into the buffer at which to begin the search | |
1849 | * @len: The length of the vpd buffer | |
1850 | * @rdt: The Resource Data Type to search for | |
1851 | * | |
1852 | * Returns the index where the Resource Data Type was found or | |
1853 | * -ENOENT otherwise. | |
1854 | */ | |
1855 | int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); | |
1856 | ||
4067a854 MC |
1857 | /** |
1858 | * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD | |
1859 | * @buf: Pointer to buffered vpd data | |
1860 | * @off: The offset into the buffer at which to begin the search | |
1861 | * @len: The length of the buffer area, relative to off, in which to search | |
1862 | * @kw: The keyword to search for | |
1863 | * | |
1864 | * Returns the index where the information field keyword was found or | |
1865 | * -ENOENT otherwise. | |
1866 | */ | |
1867 | int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, | |
1868 | unsigned int len, const char *kw); | |
1869 | ||
98d9f30c BH |
1870 | /* PCI <-> OF binding helpers */ |
1871 | #ifdef CONFIG_OF | |
1872 | struct device_node; | |
f39d5b72 BH |
1873 | void pci_set_of_node(struct pci_dev *dev); |
1874 | void pci_release_of_node(struct pci_dev *dev); | |
1875 | void pci_set_bus_of_node(struct pci_bus *bus); | |
1876 | void pci_release_bus_of_node(struct pci_bus *bus); | |
98d9f30c BH |
1877 | |
1878 | /* Arch may override this (weak) */ | |
723ec4d0 | 1879 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); |
98d9f30c | 1880 | |
3df425f3 JC |
1881 | static inline struct device_node * |
1882 | pci_device_to_OF_node(const struct pci_dev *pdev) | |
64099d98 BH |
1883 | { |
1884 | return pdev ? pdev->dev.of_node : NULL; | |
1885 | } | |
1886 | ||
ef3b4f8c BH |
1887 | static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) |
1888 | { | |
1889 | return bus ? bus->dev.of_node : NULL; | |
1890 | } | |
1891 | ||
98d9f30c BH |
1892 | #else /* CONFIG_OF */ |
1893 | static inline void pci_set_of_node(struct pci_dev *dev) { } | |
1894 | static inline void pci_release_of_node(struct pci_dev *dev) { } | |
1895 | static inline void pci_set_bus_of_node(struct pci_bus *bus) { } | |
1896 | static inline void pci_release_bus_of_node(struct pci_bus *bus) { } | |
1897 | #endif /* CONFIG_OF */ | |
1898 | ||
eb740b5f GS |
1899 | #ifdef CONFIG_EEH |
1900 | static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) | |
1901 | { | |
1902 | return pdev->dev.archdata.edev; | |
1903 | } | |
1904 | #endif | |
1905 | ||
166e9278 OBC |
1906 | /** |
1907 | * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device | |
1908 | * @pdev: the PCI device | |
1909 | * | |
1910 | * if the device is PCIE, return NULL | |
1911 | * if the device isn't connected to a PCIe bridge (that is its parent is a | |
1912 | * legacy PCI bridge and the bridge is directly connected to bus 0), return its | |
1913 | * parent | |
1914 | */ | |
1915 | struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev); | |
1916 | ||
1da177e4 | 1917 | #endif /* LINUX_PCI_H */ |