projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
PCI: checking busn_res in pci_scan_root_bus()
[deliverable/linux.git] / include / linux / pci.h
CommitLineData
1da177e4
LT		 1/*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
f46753c5 20#include <linux/pci_regs.h> /* The pci register defines */
1da177e4 21
1da177e4
LT		 22/*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
05cca6e5 30#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
1da177e4
LT		 31#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32#define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34/* Ioctls for /proc/bus/pci/X/Y nodes. */
35#define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36#define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37#define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38#define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39#define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41#ifdef __KERNEL__
42
778382e0
DW		 43#include <linux/mod_devicetable.h>
44
1da177e4 45#include <linux/types.h>
98db6f19 46#include <linux/init.h>
1da177e4
LT		 47#include <linux/ioport.h>
48#include <linux/list.h>
4a7fb636 49#include <linux/compiler.h>
1da177e4 50#include <linux/errno.h>
f46753c5 51#include <linux/kobject.h>
60063497 52#include <linux/atomic.h>
1da177e4 53#include <linux/device.h>
1388cc96 54#include <linux/io.h>
74bb1bcc 55#include <linux/irqreturn.h>
1da177e4 56
7e7a43c3
AB		 57/* Include the ID list */
58#include <linux/pci_ids.h>
59
f46753c5
AC		 60/* pci_slot represents a physical slot */
61struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67};
68
0ad772ec
AC		 69static inline const char *pci_slot_name(const struct pci_slot *slot)
70{
71 return kobject_name(&slot->kobj);
72}
73
1da177e4
LT		 74/* File state for mmap()s on /proc/bus/pci/X/Y */
75enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78};
79
80/* This defines the direction arg to the DMA mapping routines. */
81#define PCI_DMA_BIDIRECTIONAL 0
82#define PCI_DMA_TODEVICE 1
83#define PCI_DMA_FROMDEVICE 2
84#define PCI_DMA_NONE 3
85
fde09c6d
YZ		 86/*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
d1b054da
YZ		 97 /* device specific resources */
98#ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101#endif
102
fde09c6d
YZ		 103 /* resources assigned to buses behind the bridge */
104#define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
cda57bf9 114 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
fde09c6d 115};
1da177e4
LT		 116
117typedef int __bitwise pci_power_t;
118
4352dfd5
GKH		 119#define PCI_D0 ((pci_power_t __force) 0)
120#define PCI_D1 ((pci_power_t __force) 1)
121#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 122#define PCI_D3hot ((pci_power_t __force) 3)
123#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 124#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 125#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 126
00240c38
AS		 127/* Remember to update this when the list above changes! */
128extern const char *pci_power_names[];
129
130static inline const char *pci_power_name(pci_power_t state)
131{
132 return pci_power_names[1 + (int) state];
133}
134
aa8c6c93
RW		 135#define PCI_PM_D2_DELAY 200
136#define PCI_PM_D3_WAIT 10
137#define PCI_PM_BUS_WAIT 50
138
392a1ce7 139/** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
142 */
143typedef unsigned int __bitwise pci_channel_state_t;
144
145enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
148
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
151
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
154};
155
f7bdd12d
BK		 156typedef unsigned int __bitwise pcie_reset_state_t;
157
158enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
161
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
164
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
167};
168
ba698ad4
DM		 169typedef unsigned short __bitwise pci_dev_flags_t;
170enum pci_dev_flags {
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
172 * generation too.
173 */
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
979b1791
AC		 175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
6777829c
GR		 177 /* Provide indication device is assigned by a Virtual Machine Manager */
178 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
ba698ad4
DM		 179};
180
e1d3a908
SA		 181enum pci_irq_reroute_variant {
182 INTEL_IRQ_REROUTE_VARIANT = 1,
183 MAX_IRQ_REROUTE_VARIANTS = 3
184};
185
6e325a62
MT		 186typedef unsigned short __bitwise pci_bus_flags_t;
187enum pci_bus_flags {
d556ad4b
PO		 188 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
189 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
6e325a62
MT		 190};
191
536c8cb4
MW		 192/* Based on the PCI Hotplug Spec, but some values are made up by us */
193enum pci_bus_speed {
194 PCI_SPEED_33MHz = 0x00,
195 PCI_SPEED_66MHz = 0x01,
196 PCI_SPEED_66MHz_PCIX = 0x02,
197 PCI_SPEED_100MHz_PCIX = 0x03,
198 PCI_SPEED_133MHz_PCIX = 0x04,
199 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
200 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
201 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
202 PCI_SPEED_66MHz_PCIX_266 = 0x09,
203 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
204 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
45b4cdd5
MW		 205 AGP_UNKNOWN = 0x0c,
206 AGP_1X = 0x0d,
207 AGP_2X = 0x0e,
208 AGP_4X = 0x0f,
209 AGP_8X = 0x10,
536c8cb4
MW		 210 PCI_SPEED_66MHz_PCIX_533 = 0x11,
211 PCI_SPEED_100MHz_PCIX_533 = 0x12,
212 PCI_SPEED_133MHz_PCIX_533 = 0x13,
213 PCIE_SPEED_2_5GT = 0x14,
214 PCIE_SPEED_5_0GT = 0x15,
9dfd97fe 215 PCIE_SPEED_8_0GT = 0x16,
536c8cb4
MW		 216 PCI_SPEED_UNKNOWN = 0xff,
217};
218
24a4742f 219struct pci_cap_saved_data {
41017f0c 220 char cap_nr;
24a4742f 221 unsigned int size;
41017f0c
SL		 222 u32 data[0];
223};
224
24a4742f
AW		 225struct pci_cap_saved_state {
226 struct hlist_node next;
227 struct pci_cap_saved_data cap;
228};
229
7d715a6c 230struct pcie_link_state;
ee69439c 231struct pci_vpd;
d1b054da 232struct pci_sriov;
302b4215 233struct pci_ats;
ee69439c 234
1da177e4
LT		 235/*
236 * The pci_dev structure is used to describe PCI devices.
237 */
238struct pci_dev {
1da177e4
LT		 239 struct list_head bus_list; /* node in per-bus list */
240 struct pci_bus *bus; /* bus this device is on */
241 struct pci_bus *subordinate; /* bus this device bridges to */
242
243 void *sysdata; /* hook for sys-specific extension */
244 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
f46753c5 245 struct pci_slot *slot; /* Physical slot this device is in */
1da177e4
LT		 246
247 unsigned int devfn; /* encoded device & function index */
248 unsigned short vendor;
249 unsigned short device;
250 unsigned short subsystem_vendor;
251 unsigned short subsystem_device;
252 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
b8a3a521 253 u8 revision; /* PCI revision, low byte of class word */
1da177e4 254 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
0efea000 255 u8 pcie_cap; /* PCI-E capability offset */
b03e7495
JM		 256 u8 pcie_type:4; /* PCI-E device/port type */
257 u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
1da177e4 258 u8 rom_base_reg; /* which config register controls the ROM */
ffeff788 259 u8 pin; /* which interrupt pin this device uses */
1da177e4
LT		 260
261 struct pci_driver *driver; /* which driver has allocated this device */
262 u64 dma_mask; /* Mask of the bits of bus address this
263 device implements. Normally this is
264 0xffffffff. You only need to change
265 this if your device has broken DMA
266 or supports 64-bit transfers. */
267
4d57cdfa
FT		 268 struct device_dma_parameters dma_parms;
269
1da177e4
LT		 270 pci_power_t current_state; /* Current operating state. In ACPI-speak,
271 this is D0-D3, D0 being fully functional,
272 and D3 being off. */
337001b6
RW		 273 int pm_cap; /* PM capability offset in the
274 configuration space */
275 unsigned int pme_support:5; /* Bitmask of states from which PME#
276 can be generated */
c7f48656 277 unsigned int pme_interrupt:1;
379021d5 278 unsigned int pme_poll:1; /* Poll device's PME status bit */
337001b6
RW		 279 unsigned int d1_support:1; /* Low power state D1 is supported */
280 unsigned int d2_support:1; /* Low power state D2 is supported */
281 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
253d2e54
JP		 282 unsigned int mmio_always_on:1; /* disallow turning off io/mem
283 decoding during bar sizing */
e80bb09d 284 unsigned int wakeup_prepared:1;
1ae861e6 285 unsigned int d3_delay; /* D3->D0 transition time in ms */
1da177e4 286
7d715a6c
SL		 287#ifdef CONFIG_PCIEASPM
288 struct pcie_link_state *link_state; /* ASPM link state. */
289#endif
290
392a1ce7 291 pci_channel_state_t error_state; /* current connectivity state */
1da177e4
LT		 292 struct device dev; /* Generic device interface */
293
1da177e4
LT		 294 int cfg_size; /* Size of configuration space */
295
296 /*
297 * Instead of touching interrupt line and base address registers
298 * directly, use the values stored here. They might be different!
299 */
300 unsigned int irq;
301 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
302
303 /* These fields are used by common fixups */
304 unsigned int transparent:1; /* Transparent PCI bridge */
305 unsigned int multifunction:1;/* Part of multi-function device */
306 /* keep track of device state */
8a1bc901 307 unsigned int is_added:1;
1da177e4 308 unsigned int is_busmaster:1; /* device is busmaster */
4602b88d 309 unsigned int no_msi:1; /* device may not use msi */
fb51ccbf 310 unsigned int block_cfg_access:1; /* config space access is blocked */
bd8481e1 311 unsigned int broken_parity_status:1; /* Device generates false positive parity */
e1d3a908 312 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
99dc804d
SL		 313 unsigned int msi_enabled:1;
314 unsigned int msix_enabled:1;
58c3a727 315 unsigned int ari_enabled:1; /* ARI forwarding */
9ac7849e 316 unsigned int is_managed:1;
6d3be84a
KK		 317 unsigned int is_pcie:1; /* Obsolete. Will be removed.
318 Use pci_is_pcie() instead */
260d703a 319 unsigned int needs_freset:1; /* Dev requires fundamental reset */
aa8c6c93 320 unsigned int state_saved:1;
d1b054da 321 unsigned int is_physfn:1;
dd7cc44d 322 unsigned int is_virtfn:1;
711d5779 323 unsigned int reset_fn:1;
28760489 324 unsigned int is_hotplug_bridge:1;
affb72c3
HY		 325 unsigned int __aer_firmware_first_valid:1;
326 unsigned int __aer_firmware_first:1;
ba698ad4 327 pci_dev_flags_t dev_flags;
bae94d02 328 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 329
1da177e4 330 u32 saved_config_space[16]; /* config space saved at suspend time */
41017f0c 331 struct hlist_head saved_cap_space;
1da177e4
LT		 332 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
333 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
334 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
45aec1ae 335 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
ded86d8d 336#ifdef CONFIG_PCI_MSI
4aa9bc95 337 struct list_head msi_list;
da8d1c8b 338 struct kset *msi_kset;
ded86d8d 339#endif
94e61088 340 struct pci_vpd *vpd;
466b3ddf 341#ifdef CONFIG_PCI_ATS
dd7cc44d
YZ		 342 union {
343 struct pci_sriov *sriov; /* SR-IOV capability related */
344 struct pci_dev *physfn; /* the PF this VF is associated with */
345 };
302b4215 346 struct pci_ats *ats; /* Address Translation Service */
d1b054da 347#endif
1da177e4
LT		 348};
349
dda56549
Y		 350static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
351{
352#ifdef CONFIG_PCI_IOV
353 if (dev->is_virtfn)
354 dev = dev->physfn;
355#endif
356
357 return dev;
358}
359
65891215
ME		 360extern struct pci_dev *alloc_pci_dev(void);
361
1da177e4
LT		 362#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
363#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
364#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
365
a7369f1f
LV		 366static inline int pci_channel_offline(struct pci_dev *pdev)
367{
368 return (pdev->error_state != pci_channel_io_normal);
369}
370
0efd5aab
BH		 371struct pci_host_bridge_window {
372 struct list_head list;
373 struct resource *res; /* host bridge aperture (CPU address) */
374 resource_size_t offset; /* bus address + offset = CPU address */
375};
41017f0c 376
5a21d70d 377struct pci_host_bridge {
7b543663 378 struct device dev;
5a21d70d 379 struct pci_bus *bus; /* root bus */
0efd5aab 380 struct list_head windows; /* pci_host_bridge_windows */
4fa2649a
YL		 381 void (*release_fn)(struct pci_host_bridge *);
382 void *release_data;
5a21d70d 383};
41017f0c 384
7b543663 385#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
4fa2649a
YL		 386void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
387 void (*release_fn)(struct pci_host_bridge *),
388 void *release_data);
7b543663 389
2fe2abf8
BH		 390/*
391 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
392 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
393 * buses below host bridges or subtractive decode bridges) go in the list.
394 * Use pci_bus_for_each_resource() to iterate through all the resources.
395 */
396
397/*
398 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
399 * and there's no way to program the bridge with the details of the window.
400 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
401 * decode bit set, because they are explicit and can be programmed with _SRS.
402 */
403#define PCI_SUBTRACTIVE_DECODE 0x1
404
405struct pci_bus_resource {
406 struct list_head list;
407 struct resource *res;
408 unsigned int flags;
409};
4352dfd5
GKH		 410
411#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 412
413struct pci_bus {
414 struct list_head node; /* node in list of buses */
415 struct pci_bus *parent; /* parent bus this bridge is on */
416 struct list_head children; /* list of child buses */
417 struct list_head devices; /* list of devices on this bus */
418 struct pci_dev *self; /* bridge device as seen by parent */
f46753c5 419 struct list_head slots; /* list of slots on this bus */
2fe2abf8
BH		 420 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
421 struct list_head resources; /* address space routed to this bus */
92f02430 422 struct resource busn_res; /* bus numbers routed to this bus */
1da177e4
LT		 423
424 struct pci_ops *ops; /* configuration access functions */
425 void *sysdata; /* hook for sys-specific extension */
426 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
427
428 unsigned char number; /* bus number */
429 unsigned char primary; /* number of primary bridge */
3749c51a
MW		 430 unsigned char max_bus_speed; /* enum pci_bus_speed */
431 unsigned char cur_bus_speed; /* enum pci_bus_speed */
1da177e4
LT		 432
433 char name[48];
434
435 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
6e325a62 436 pci_bus_flags_t bus_flags; /* Inherited by child busses */
1da177e4 437 struct device *bridge;
fd7d1ced 438 struct device dev;
1da177e4
LT		 439 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
440 struct bin_attribute *legacy_mem; /* legacy mem */
cc74d96f 441 unsigned int is_added:1;
1da177e4
LT		 442};
443
444#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
fd7d1ced 445#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
1da177e4 446
79af72d7
KK		 447/*
448 * Returns true if the pci bus is root (behind host-pci bridge),
449 * false otherwise
450 */
451static inline bool pci_is_root_bus(struct pci_bus *pbus)
452{
453 return !(pbus->parent);
454}
455
16cf0ebc
RW		 456#ifdef CONFIG_PCI_MSI
457static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
458{
459 return pci_dev->msi_enabled || pci_dev->msix_enabled;
460}
461#else
462static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
463#endif
464
1da177e4
LT		 465/*
466 * Error values that may be returned by PCI functions.
467 */
468#define PCIBIOS_SUCCESSFUL 0x00
469#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
470#define PCIBIOS_BAD_VENDOR_ID 0x83
471#define PCIBIOS_DEVICE_NOT_FOUND 0x86
472#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
473#define PCIBIOS_SET_FAILED 0x88
474#define PCIBIOS_BUFFER_TOO_SMALL 0x89
475
476/* Low-level architecture-dependent routines */
477
478struct pci_ops {
479 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
480 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
481};
482
b6ce068a
MW		 483/*
484 * ACPI needs to be able to access PCI config space before we've done a
485 * PCI bus scan and created pci_bus structures.
486 */
487extern int raw_pci_read(unsigned int domain, unsigned int bus,
488 unsigned int devfn, int reg, int len, u32 *val);
489extern int raw_pci_write(unsigned int domain, unsigned int bus,
490 unsigned int devfn, int reg, int len, u32 val);
1da177e4
LT		 491
492struct pci_bus_region {
c40a22e0
BH		 493 resource_size_t start;
494 resource_size_t end;
1da177e4
LT		 495};
496
497struct pci_dynids {
498 spinlock_t lock; /* protects list, index */
499 struct list_head list; /* for IDs added at runtime */
1da177e4
LT		 500};
501
392a1ce7 502/* ---------------------------------------------------------------- */
503/** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
579082df 504 * a set of callbacks in struct pci_error_handlers, then that device driver
392a1ce7 505 * will be notified of PCI bus errors, and will be driven to recovery
506 * when an error occurs.
507 */
508
509typedef unsigned int __bitwise pci_ers_result_t;
510
511enum pci_ers_result {
512 /* no result/none/not supported in device driver */
513 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
514
515 /* Device driver can recover without slot reset */
516 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
517
518 /* Device driver wants slot to be reset. */
519 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
520
521 /* Device has completely failed, is unrecoverable */
522 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
523
524 /* Device driver is fully recovered and operational */
525 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
526};
527
528/* PCI bus error event callbacks */
05cca6e5 529struct pci_error_handlers {
392a1ce7 530 /* PCI bus error detected on this device */
531 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
05cca6e5 532 enum pci_channel_state error);
392a1ce7 533
534 /* MMIO has been re-enabled, but not DMA */
535 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
536
537 /* PCI Express link has been reset */
538 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
539
540 /* PCI slot has been reset */
541 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
542
543 /* Device driver may resume normal operations */
544 void (*resume)(struct pci_dev *dev);
545};
546
547/* ---------------------------------------------------------------- */
548
1da177e4
LT		 549struct module;
550struct pci_driver {
551 struct list_head node;
42b21932 552 const char *name;
1da177e4
LT		 553 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
554 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
555 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
556 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
cbd69dbb
LT		 557 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
558 int (*resume_early) (struct pci_dev *dev);
1da177e4 559 int (*resume) (struct pci_dev *dev); /* Device woken up */
c8958177 560 void (*shutdown) (struct pci_dev *dev);
392a1ce7 561 struct pci_error_handlers *err_handler;
1da177e4
LT		 562 struct device_driver driver;
563 struct pci_dynids dynids;
564};
565
05cca6e5 566#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
1da177e4 567
90a1ba0c 568/**
9f9351bb 569 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
90a1ba0c
JB		 570 * @_table: device table name
571 *
572 * This macro is used to create a struct pci_device_id array (a device table)
573 * in a generic manner.
574 */
9f9351bb 575#define DEFINE_PCI_DEVICE_TABLE(_table) \
90a1ba0c
JB		 576 const struct pci_device_id _table[] __devinitconst
577
1da177e4
LT		 578/**
579 * PCI_DEVICE - macro used to describe a specific pci device
580 * @vend: the 16 bit PCI Vendor ID
581 * @dev: the 16 bit PCI Device ID
582 *
583 * This macro is used to create a struct pci_device_id that matches a
584 * specific device. The subvendor and subdevice fields will be set to
585 * PCI_ANY_ID.
586 */
587#define PCI_DEVICE(vend,dev) \
588 .vendor = (vend), .device = (dev), \
589 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
590
591/**
592 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
593 * @dev_class: the class, subclass, prog-if triple for this device
594 * @dev_class_mask: the class mask for this device
595 *
596 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 597 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 598 * fields will be set to PCI_ANY_ID.
599 */
600#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
601 .class = (dev_class), .class_mask = (dev_class_mask), \
602 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
603 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
604
1597cacb
AC		 605/**
606 * PCI_VDEVICE - macro used to describe a specific pci device in short form
c322b28a
ZY		 607 * @vendor: the vendor name
608 * @device: the 16 bit PCI Device ID
1597cacb
AC		 609 *
610 * This macro is used to create a struct pci_device_id that matches a
611 * specific PCI device. The subvendor, and subdevice fields will be set
612 * to PCI_ANY_ID. The macro allows the next field to follow as the device
613 * private data.
614 */
615
616#define PCI_VDEVICE(vendor, device) \
617 PCI_VENDOR_ID_##vendor, (device), \
618 PCI_ANY_ID, PCI_ANY_ID, 0, 0
619
1da177e4
LT		 620/* these external functions are only available when PCI support is enabled */
621#ifdef CONFIG_PCI
622
b03e7495
JM		 623extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
624
625enum pcie_bus_config_types {
5f39e670 626 PCIE_BUS_TUNE_OFF,
b03e7495 627 PCIE_BUS_SAFE,
5f39e670 628 PCIE_BUS_PERFORMANCE,
b03e7495
JM		 629 PCIE_BUS_PEER2PEER,
630};
631
632extern enum pcie_bus_config_types pcie_bus_config;
633
1da177e4
LT		 634extern struct bus_type pci_bus_type;
635
636/* Do NOT directly access these two variables, unless you are arch specific pci
637 * code, or pci core code. */
638extern struct list_head pci_root_buses; /* list of all known PCI buses */
ed4aaadb
ZY		 639/* Some device drivers need know if pci is initiated */
640extern int no_pci_devices(void);
1da177e4
LT		 641
642void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 643int __must_check pcibios_enable_device(struct pci_dev *, int mask);
05cca6e5 644char *pcibios_setup(char *str);
1da177e4
LT		 645
646/* Used only when drivers/pci/setup.c is used */
3b7a17fc 647resource_size_t pcibios_align_resource(void *, const struct resource *,
b26b2d49 648 resource_size_t,
e31dd6e4 649 resource_size_t);
1da177e4
LT		 650void pcibios_update_irq(struct pci_dev *, int irq);
651
2d1c8618
BH		 652/* Weak but can be overriden by arch */
653void pci_fixup_cardbus(struct pci_bus *);
654
1da177e4
LT		 655/* Generic PCI functions used internally */
656
36a66cd6
BH		 657void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
658 struct resource *res);
659void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
660 struct pci_bus_region *region);
d1fd4fb6 661void pcibios_scan_specific_bus(int busn);
1da177e4 662extern struct pci_bus *pci_find_bus(int domain, int busnr);
c48f1670 663void pci_bus_add_devices(const struct pci_bus *bus);
05cca6e5
GKH		 664struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
665 struct pci_ops *ops, void *sysdata);
de4b2f76 666struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
166c6370
BH		 667struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
668 struct pci_ops *ops, void *sysdata,
669 struct list_head *resources);
98a35831
YL		 670int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
671int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
672void pci_bus_release_busn_res(struct pci_bus *b);
a2ebb827
BH		 673struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus,
674 struct pci_ops *ops, void *sysdata,
675 struct list_head *resources);
05cca6e5
GKH		 676struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
677 int busnr);
3749c51a 678void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
f46753c5 679struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
828f3768
AC		 680 const char *name,
681 struct hotplug_slot *hotplug);
f46753c5 682void pci_destroy_slot(struct pci_slot *slot);
d25b7c8d 683void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
1da177e4 684int pci_scan_slot(struct pci_bus *bus, int devfn);
05cca6e5 685struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 686void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 687unsigned int pci_scan_child_bus(struct pci_bus *bus);
b19441af 688int __must_check pci_bus_add_device(struct pci_dev *dev);
1da177e4 689void pci_read_bridge_bases(struct pci_bus *child);
05cca6e5
GKH		 690struct resource *pci_find_parent_resource(const struct pci_dev *dev,
691 struct resource *res);
3df425f3 692u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1da177e4 693int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
68feac87 694u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1da177e4
LT		 695extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
696extern void pci_dev_put(struct pci_dev *dev);
697extern void pci_remove_bus(struct pci_bus *b);
6b22cf3f 698extern void __pci_remove_bus_device(struct pci_dev *dev);
210647af 699extern void pci_stop_and_remove_bus_device(struct pci_dev *dev);
24f8aa9b 700extern void pci_stop_bus_device(struct pci_dev *dev);
b3743fa4 701void pci_setup_cardbus(struct pci_bus *bus);
6b4b78fe 702extern void pci_sort_breadthfirst(void);
fb8a0d9d
WM		 703#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
704#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
705#define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
1da177e4
LT		 706
707/* Generic PCI functions exported to card drivers */
708
388c8c16
JB		 709enum pci_lost_interrupt_reason {
710 PCI_LOST_IRQ_NO_INFORMATION = 0,
711 PCI_LOST_IRQ_DISABLE_MSI,
712 PCI_LOST_IRQ_DISABLE_MSIX,
713 PCI_LOST_IRQ_DISABLE_ACPI,
714};
715enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
05cca6e5
GKH		 716int pci_find_capability(struct pci_dev *dev, int cap);
717int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
718int pci_find_ext_capability(struct pci_dev *dev, int cap);
cf4c43dd
JB		 719int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
720 int cap);
05cca6e5
GKH		 721int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
722int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
29f3eb64 723struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4 724
d42552c3
AM		 725struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
726 struct pci_dev *from);
05cca6e5 727struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1da177e4 728 unsigned int ss_vendor, unsigned int ss_device,
b08508c4 729 struct pci_dev *from);
05cca6e5 730struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
3c299dc2
AP		 731struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
732 unsigned int devfn);
733static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
734 unsigned int devfn)
735{
736 return pci_get_domain_bus_and_slot(0, bus, devfn);
737}
05cca6e5 738struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1da177e4
LT		 739int pci_dev_present(const struct pci_device_id *ids);
740
05cca6e5
GKH		 741int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
742 int where, u8 *val);
743int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
744 int where, u16 *val);
745int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
746 int where, u32 *val);
747int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
748 int where, u8 val);
749int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
750 int where, u16 val);
751int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
752 int where, u32 val);
a72b46c3 753struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1da177e4 754
bf362f75 755static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
1da177e4 756{
05cca6e5 757 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
1da177e4 758}
bf362f75 759static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
1da177e4 760{
05cca6e5 761 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
1da177e4 762}
bf362f75 763static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
05cca6e5 764 u32 *val)
1da177e4 765{
05cca6e5 766 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
1da177e4 767}
bf362f75 768static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
1da177e4 769{
05cca6e5 770 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
1da177e4 771}
bf362f75 772static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
1da177e4 773{
05cca6e5 774 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
1da177e4 775}
bf362f75 776static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
05cca6e5 777 u32 val)
1da177e4 778{
05cca6e5 779 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
1da177e4
LT		 780}
781
4a7fb636 782int __must_check pci_enable_device(struct pci_dev *dev);
b718989d
BH		 783int __must_check pci_enable_device_io(struct pci_dev *dev);
784int __must_check pci_enable_device_mem(struct pci_dev *dev);
0b62e13b 785int __must_check pci_reenable_device(struct pci_dev *);
9ac7849e
TH		 786int __must_check pcim_enable_device(struct pci_dev *pdev);
787void pcim_pin_device(struct pci_dev *pdev);
788
296ccb08
YS		 789static inline int pci_is_enabled(struct pci_dev *pdev)
790{
791 return (atomic_read(&pdev->enable_cnt) > 0);
792}
793
9ac7849e
TH		 794static inline int pci_is_managed(struct pci_dev *pdev)
795{
796 return pdev->is_managed;
797}
798
1da177e4 799void pci_disable_device(struct pci_dev *dev);
96c55900
MS		 800
801extern unsigned int pcibios_max_latency;
1da177e4 802void pci_set_master(struct pci_dev *dev);
6a479079 803void pci_clear_master(struct pci_dev *dev);
96c55900 804
f7bdd12d 805int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
15ea76d4 806int pci_set_cacheline_size(struct pci_dev *dev);
1da177e4 807#define HAVE_PCI_SET_MWI
4a7fb636 808int __must_check pci_set_mwi(struct pci_dev *dev);
694625c0 809int pci_try_set_mwi(struct pci_dev *dev);
1da177e4 810void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 811void pci_intx(struct pci_dev *dev, int enable);
a2e27787
JK		 812bool pci_intx_mask_supported(struct pci_dev *dev);
813bool pci_check_and_mask_intx(struct pci_dev *dev);
814bool pci_check_and_unmask_intx(struct pci_dev *dev);
f5f2b131 815void pci_msi_off(struct pci_dev *dev);
4d57cdfa 816int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
59fc67de 817int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
d556ad4b
PO		 818int pcix_get_max_mmrbc(struct pci_dev *dev);
819int pcix_get_mmrbc(struct pci_dev *dev);
820int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
2637e5b5 821int pcie_get_readrq(struct pci_dev *dev);
d556ad4b 822int pcie_set_readrq(struct pci_dev *dev, int rq);
b03e7495
JM		 823int pcie_get_mps(struct pci_dev *dev);
824int pcie_set_mps(struct pci_dev *dev, int mps);
8c1c699f 825int __pci_reset_function(struct pci_dev *dev);
a96d627a 826int __pci_reset_function_locked(struct pci_dev *dev);
8dd7f803 827int pci_reset_function(struct pci_dev *dev);
14add80b 828void pci_update_resource(struct pci_dev *dev, int resno);
4a7fb636 829int __must_check pci_assign_resource(struct pci_dev *dev, int i);
2bbc6942 830int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
c87deff7 831int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1da177e4
LT		 832
833/* ROM control related routines */
e416de5e
AC		 834int pci_enable_rom(struct pci_dev *pdev);
835void pci_disable_rom(struct pci_dev *pdev);
144a50ea 836void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1da177e4 837void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
97c44836 838size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1da177e4
LT		 839
840/* Power management related routines */
841int pci_save_state(struct pci_dev *dev);
1d3c16a8 842void pci_restore_state(struct pci_dev *dev);
ffbdd3f7
AW		 843struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
844int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
845int pci_load_and_free_saved_state(struct pci_dev *dev,
846 struct pci_saved_state **state);
0e5dd46b 847int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
9c8550ee
LT		 848int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
849pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
e5899e1b 850bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
5a6c9b60 851void pci_pme_active(struct pci_dev *dev, bool enable);
6cbf8214
RW		 852int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
853 bool runtime, bool enable);
0235c4fc 854int pci_wake_from_d3(struct pci_dev *dev, bool enable);
e5899e1b 855pci_power_t pci_target_state(struct pci_dev *dev);
404cc2d8
RW		 856int pci_prepare_to_sleep(struct pci_dev *dev);
857int pci_back_from_sleep(struct pci_dev *dev);
b67ea761 858bool pci_dev_run_wake(struct pci_dev *dev);
bf4d2908 859bool pci_check_pme_status(struct pci_dev *dev);
bf4d2908 860void pci_pme_wakeup_bus(struct pci_bus *bus);
1da177e4 861
6cbf8214
RW		 862static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
863 bool enable)
864{
865 return __pci_enable_wake(dev, state, false, enable);
866}
1da177e4 867
b48d4425
JB		 868#define PCI_EXP_IDO_REQUEST (1<<0)
869#define PCI_EXP_IDO_COMPLETION (1<<1)
870void pci_enable_ido(struct pci_dev *dev, unsigned long type);
871void pci_disable_ido(struct pci_dev *dev, unsigned long type);
872
48a92a81 873enum pci_obff_signal_type {
688398bb
MS		 874 PCI_EXP_OBFF_SIGNAL_L0 = 0,
875 PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
48a92a81
JB		 876};
877int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
878void pci_disable_obff(struct pci_dev *dev);
879
51c2e0a7
JB		 880bool pci_ltr_supported(struct pci_dev *dev);
881int pci_enable_ltr(struct pci_dev *dev);
882void pci_disable_ltr(struct pci_dev *dev);
883int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
884
bb209c82
BH		 885/* For use by arch with custom probe code */
886void set_pcie_port_type(struct pci_dev *pdev);
887void set_pcie_hotplug_bridge(struct pci_dev *pdev);
888
ce5ccdef 889/* Functions for PCI Hotplug drivers to use */
05cca6e5 890int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
3ed4fd96 891#ifdef CONFIG_HOTPLUG
2f320521 892unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
3ed4fd96
AC		 893unsigned int pci_rescan_bus(struct pci_bus *bus);
894#endif
ce5ccdef 895
287d19ce
SH		 896/* Vital product data routines */
897ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
898ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
db567943 899int pci_vpd_truncate(struct pci_dev *dev, size_t size);
287d19ce 900
1da177e4 901/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
925845bd 902resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
ea741551 903void pci_bus_assign_resources(const struct pci_bus *bus);
1da177e4
LT		 904void pci_bus_size_bridges(struct pci_bus *bus);
905int pci_claim_resource(struct pci_dev *, int);
906void pci_assign_unassigned_resources(void);
6841ec68 907void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1da177e4 908void pdev_enable_device(struct pci_dev *);
842de40d 909int pci_enable_resources(struct pci_dev *, int mask);
1da177e4 910void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
d5341942 911 int (*)(const struct pci_dev *, u8, u8));
1da177e4 912#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 913int __must_check pci_request_regions(struct pci_dev *, const char *);
e8de1481 914int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1da177e4 915void pci_release_regions(struct pci_dev *);
4a7fb636 916int __must_check pci_request_region(struct pci_dev *, int, const char *);
e8de1481 917int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1da177e4 918void pci_release_region(struct pci_dev *, int);
c87deff7 919int pci_request_selected_regions(struct pci_dev *, int, const char *);
e8de1481 920int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
c87deff7 921void pci_release_selected_regions(struct pci_dev *, int);
1da177e4
LT		 922
923/* drivers/pci/bus.c */
45ca9e97 924void pci_add_resource(struct list_head *resources, struct resource *res);
0efd5aab
BH		 925void pci_add_resource_offset(struct list_head *resources, struct resource *res,
926 resource_size_t offset);
45ca9e97 927void pci_free_resource_list(struct list_head *resources);
2fe2abf8
BH		 928void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
929struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
930void pci_bus_remove_resources(struct pci_bus *bus);
931
89a74ecc 932#define pci_bus_for_each_resource(bus, res, i) \
2fe2abf8
BH		 933 for (i = 0; \
934 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
935 i++)
89a74ecc 936
4a7fb636
AM		 937int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
938 struct resource *res, resource_size_t size,
939 resource_size_t align, resource_size_t min,
940 unsigned int type_mask,
3b7a17fc
DB		 941 resource_size_t (*alignf)(void *,
942 const struct resource *,
b26b2d49
DB		 943 resource_size_t,
944 resource_size_t),
4a7fb636 945 void *alignf_data);
1da177e4
LT		 946void pci_enable_bridges(struct pci_bus *bus);
947
863b18f4 948/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 949int __must_check __pci_register_driver(struct pci_driver *, struct module *,
950 const char *mod_name);
bba81165
AM		 951
952/*
953 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
954 */
955#define pci_register_driver(driver) \
956 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
863b18f4 957
05cca6e5 958void pci_unregister_driver(struct pci_driver *dev);
aad4f400
GKH		 959
960/**
961 * module_pci_driver() - Helper macro for registering a PCI driver
962 * @__pci_driver: pci_driver struct
963 *
964 * Helper macro for PCI drivers which do not do anything special in module
965 * init/exit. This eliminates a lot of boilerplate. Each module may only
966 * use this macro once, and calling it replaces module_init() and module_exit()
967 */
968#define module_pci_driver(__pci_driver) \
969 module_driver(__pci_driver, pci_register_driver, \
970 pci_unregister_driver)
971
6754b9e9 972void pci_stop_and_remove_behind_bridge(struct pci_dev *dev);
05cca6e5 973struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
9dba910e
TH		 974int pci_add_dynid(struct pci_driver *drv,
975 unsigned int vendor, unsigned int device,
976 unsigned int subvendor, unsigned int subdevice,
977 unsigned int class, unsigned int class_mask,
978 unsigned long driver_data);
05cca6e5
GKH		 979const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
980 struct pci_dev *dev);
981int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
982 int pass);
1da177e4 983
70298c6e 984void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
cecf4864 985 void *userdata);
70b9f7dc 986int pci_cfg_space_size_ext(struct pci_dev *dev);
ac7dc65a 987int pci_cfg_space_size(struct pci_dev *dev);
05cca6e5 988unsigned char pci_bus_max_busnr(struct pci_bus *bus);
e2444273 989void pci_setup_bridge(struct pci_bus *bus);
cecf4864 990
3448a19d
DA		 991#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
992#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
993
deb2d2ec 994int pci_set_vga_state(struct pci_dev *pdev, bool decode,
3448a19d 995 unsigned int command_bits, u32 flags);
1da177e4
LT		 996/* kmem_cache style wrapper around pci_alloc_consistent() */
997
f41b1771 998#include <linux/pci-dma.h>
1da177e4
LT		 999#include <linux/dmapool.h>
1000
1001#define pci_pool dma_pool
1002#define pci_pool_create(name, pdev, size, align, allocation) \
1003 dma_pool_create(name, &pdev->dev, size, align, allocation)
1004#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1005#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1006#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1007
e24c2d96
DM		 1008enum pci_dma_burst_strategy {
1009 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1010 strategy_parameter is N/A */
1011 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1012 byte boundaries */
1013 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1014 strategy_parameter byte boundaries */
1015};
1016
1da177e4 1017struct msix_entry {
16dbef4a 1018 u32 vector; /* kernel uses to write allocated vector */
1da177e4
LT		 1019 u16 entry; /* driver uses to specify entry, OS writes */
1020};
1021
0366f8f7 1022
1da177e4 1023#ifndef CONFIG_PCI_MSI
1c8d7b0a 1024static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
05cca6e5
GKH		 1025{
1026 return -1;
1027}
1028
d52877c7
YL		 1029static inline void pci_msi_shutdown(struct pci_dev *dev)
1030{ }
05cca6e5
GKH		 1031static inline void pci_disable_msi(struct pci_dev *dev)
1032{ }
1033
a52e2e35
RW		 1034static inline int pci_msix_table_size(struct pci_dev *dev)
1035{
1036 return 0;
1037}
05cca6e5
GKH		 1038static inline int pci_enable_msix(struct pci_dev *dev,
1039 struct msix_entry *entries, int nvec)
1040{
1041 return -1;
1042}
1043
d52877c7
YL		 1044static inline void pci_msix_shutdown(struct pci_dev *dev)
1045{ }
05cca6e5
GKH		 1046static inline void pci_disable_msix(struct pci_dev *dev)
1047{ }
1048
1049static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1050{ }
1051
1052static inline void pci_restore_msi_state(struct pci_dev *dev)
1053{ }
07ae95f9
AP		 1054static inline int pci_msi_enabled(void)
1055{
1056 return 0;
1057}
1da177e4 1058#else
1c8d7b0a 1059extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
d52877c7 1060extern void pci_msi_shutdown(struct pci_dev *dev);
1da177e4 1061extern void pci_disable_msi(struct pci_dev *dev);
a52e2e35 1062extern int pci_msix_table_size(struct pci_dev *dev);
05cca6e5 1063extern int pci_enable_msix(struct pci_dev *dev,
1da177e4 1064 struct msix_entry *entries, int nvec);
d52877c7 1065extern void pci_msix_shutdown(struct pci_dev *dev);
1da177e4
LT		 1066extern void pci_disable_msix(struct pci_dev *dev);
1067extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
94688cf2 1068extern void pci_restore_msi_state(struct pci_dev *dev);
07ae95f9 1069extern int pci_msi_enabled(void);
1da177e4
LT		 1070#endif
1071
ab0724ff 1072#ifdef CONFIG_PCIEPORTBUS
415e12b2
RW		 1073extern bool pcie_ports_disabled;
1074extern bool pcie_ports_auto;
ab0724ff
MT		 1075#else
1076#define pcie_ports_disabled true
1077#define pcie_ports_auto false
1078#endif
415e12b2 1079
3e1b1600 1080#ifndef CONFIG_PCIEASPM
8b8bae90
RW		 1081static inline int pcie_aspm_enabled(void) { return 0; }
1082static inline bool pcie_aspm_support_enabled(void) { return false; }
3e1b1600
AP		 1083#else
1084extern int pcie_aspm_enabled(void);
8b8bae90 1085extern bool pcie_aspm_support_enabled(void);
3e1b1600
AP		 1086#endif
1087
415e12b2
RW		 1088#ifdef CONFIG_PCIEAER
1089void pci_no_aer(void);
1090bool pci_aer_available(void);
1091#else
1092static inline void pci_no_aer(void) { }
1093static inline bool pci_aer_available(void) { return false; }
1094#endif
1095
43c16408
AP		 1096#ifndef CONFIG_PCIE_ECRC
1097static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1098{
1099 return;
1100}
1101static inline void pcie_ecrc_get_policy(char *str) {};
1102#else
1103extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1104extern void pcie_ecrc_get_policy(char *str);
1105#endif
1106
1c8d7b0a
MW		 1107#define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1108
8b955b0d 1109#ifdef CONFIG_HT_IRQ
8b955b0d
EB		 1110/* The functions a driver should call */
1111int ht_create_irq(struct pci_dev *dev, int idx);
1112void ht_destroy_irq(unsigned int irq);
8b955b0d
EB		 1113#endif /* CONFIG_HT_IRQ */
1114
fb51ccbf
JK		 1115extern void pci_cfg_access_lock(struct pci_dev *dev);
1116extern bool pci_cfg_access_trylock(struct pci_dev *dev);
1117extern void pci_cfg_access_unlock(struct pci_dev *dev);
e04b0ea2 1118
4352dfd5
GKH		 1119/*
1120 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1121 * a PCI domain is defined to be a set of PCI busses which share
1122 * configuration space.
1123 */
32a2eea7
JG		 1124#ifdef CONFIG_PCI_DOMAINS
1125extern int pci_domains_supported;
1126#else
1127enum { pci_domains_supported = 0 };
05cca6e5
GKH		 1128static inline int pci_domain_nr(struct pci_bus *bus)
1129{
1130 return 0;
1131}
1132
4352dfd5
GKH		 1133static inline int pci_proc_domain(struct pci_bus *bus)
1134{
1135 return 0;
1136}
32a2eea7 1137#endif /* CONFIG_PCI_DOMAINS */
1da177e4 1138
95a8b6ef
MT		 1139/* some architectures require additional setup to direct VGA traffic */
1140typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
3448a19d 1141 unsigned int command_bits, u32 flags);
95a8b6ef
MT		 1142extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1143
4352dfd5 1144#else /* CONFIG_PCI is not enabled */
1da177e4
LT		 1145
1146/*
1147 * If the system does not have PCI, clearly these return errors. Define
1148 * these as simple inline functions to avoid hair in drivers.
1149 */
1150
05cca6e5
GKH		 1151#define _PCI_NOP(o, s, t) \
1152 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1153 int where, t val) \
1da177e4 1154 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
05cca6e5
GKH		 1155
1156#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1157 _PCI_NOP(o, word, u16 x) \
1158 _PCI_NOP(o, dword, u32 x)
1da177e4
LT		 1159_PCI_NOP_ALL(read, *)
1160_PCI_NOP_ALL(write,)
1161
d42552c3 1162static inline struct pci_dev *pci_get_device(unsigned int vendor,
05cca6e5
GKH		 1163 unsigned int device,
1164 struct pci_dev *from)
1165{
1166 return NULL;
1167}
d42552c3 1168
05cca6e5
GKH		 1169static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1170 unsigned int device,
1171 unsigned int ss_vendor,
1172 unsigned int ss_device,
b08508c4 1173 struct pci_dev *from)
05cca6e5
GKH		 1174{
1175 return NULL;
1176}
1da177e4 1177
05cca6e5
GKH		 1178static inline struct pci_dev *pci_get_class(unsigned int class,
1179 struct pci_dev *from)
1180{
1181 return NULL;
1182}
1da177e4
LT		 1183
1184#define pci_dev_present(ids) (0)
ed4aaadb 1185#define no_pci_devices() (1)
1da177e4
LT		 1186#define pci_dev_put(dev) do { } while (0)
1187
05cca6e5
GKH		 1188static inline void pci_set_master(struct pci_dev *dev)
1189{ }
1190
1191static inline int pci_enable_device(struct pci_dev *dev)
1192{
1193 return -EIO;
1194}
1195
1196static inline void pci_disable_device(struct pci_dev *dev)
1197{ }
1198
1199static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1200{
1201 return -EIO;
1202}
1203
80be0385
RD		 1204static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1205{
1206 return -EIO;
1207}
1208
4d57cdfa
FT		 1209static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1210 unsigned int size)
1211{
1212 return -EIO;
1213}
1214
59fc67de
FT		 1215static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1216 unsigned long mask)
1217{
1218 return -EIO;
1219}
1220
05cca6e5
GKH		 1221static inline int pci_assign_resource(struct pci_dev *dev, int i)
1222{
1223 return -EBUSY;
1224}
1225
1226static inline int __pci_register_driver(struct pci_driver *drv,
1227 struct module *owner)
1228{
1229 return 0;
1230}
1231
1232static inline int pci_register_driver(struct pci_driver *drv)
1233{
1234 return 0;
1235}
1236
1237static inline void pci_unregister_driver(struct pci_driver *drv)
1238{ }
1239
1240static inline int pci_find_capability(struct pci_dev *dev, int cap)
1241{
1242 return 0;
1243}
1244
1245static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1246 int cap)
1247{
1248 return 0;
1249}
1250
1251static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1252{
1253 return 0;
1254}
1255
1da177e4 1256/* Power management related routines */
05cca6e5
GKH		 1257static inline int pci_save_state(struct pci_dev *dev)
1258{
1259 return 0;
1260}
1261
1d3c16a8
JM		 1262static inline void pci_restore_state(struct pci_dev *dev)
1263{ }
1da177e4 1264
05cca6e5
GKH		 1265static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1266{
1267 return 0;
1268}
1269
3449248c
RD		 1270static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1271{
1272 return 0;
1273}
1274
05cca6e5
GKH		 1275static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1276 pm_message_t state)
1277{
1278 return PCI_D0;
1279}
1280
1281static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1282 int enable)
1283{
1284 return 0;
1285}
1286
b48d4425
JB		 1287static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1288{
1289}
1290
1291static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1292{
1293}
1294
48a92a81
JB		 1295static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1296{
1297 return 0;
1298}
1299
1300static inline void pci_disable_obff(struct pci_dev *dev)
1301{
1302}
1303
05cca6e5
GKH		 1304static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1305{
1306 return -EIO;
1307}
1308
1309static inline void pci_release_regions(struct pci_dev *dev)
1310{ }
0da0ead9 1311
a46e8126
KG		 1312#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1313
fb51ccbf 1314static inline void pci_block_cfg_access(struct pci_dev *dev)
05cca6e5
GKH		 1315{ }
1316
fb51ccbf
JK		 1317static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1318{ return 0; }
1319
1320static inline void pci_unblock_cfg_access(struct pci_dev *dev)
05cca6e5 1321{ }
e04b0ea2 1322
d80d0217
RD		 1323static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1324{ return NULL; }
1325
1326static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1327 unsigned int devfn)
1328{ return NULL; }
1329
1330static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1331 unsigned int devfn)
1332{ return NULL; }
1333
92298e66
DA		 1334static inline int pci_domain_nr(struct pci_bus *bus)
1335{ return 0; }
1336
fb8a0d9d
WM		 1337#define dev_is_pci(d) (false)
1338#define dev_is_pf(d) (false)
1339#define dev_num_vf(d) (0)
4352dfd5 1340#endif /* CONFIG_PCI */
1da177e4 1341
4352dfd5
GKH		 1342/* Include architecture-dependent settings and functions */
1343
1344#include <asm/pci.h>
1da177e4 1345
1f82de10
YL		 1346#ifndef PCIBIOS_MAX_MEM_32
1347#define PCIBIOS_MAX_MEM_32 (-1)
1348#endif
1349
1da177e4
LT		 1350/* these helpers provide future and backwards compatibility
1351 * for accessing popular PCI BAR info */
05cca6e5
GKH		 1352#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1353#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1354#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1da177e4 1355#define pci_resource_len(dev,bar) \
05cca6e5
GKH		 1356 ((pci_resource_start((dev), (bar)) == 0 && \
1357 pci_resource_end((dev), (bar)) == \
1358 pci_resource_start((dev), (bar))) ? 0 : \
1359 \
1360 (pci_resource_end((dev), (bar)) - \
1361 pci_resource_start((dev), (bar)) + 1))
1da177e4
LT		 1362
1363/* Similar to the helpers above, these manipulate per-pci_dev
1364 * driver-specific data. They are really just a wrapper around
1365 * the generic device structure functions of these calls.
1366 */
05cca6e5 1367static inline void *pci_get_drvdata(struct pci_dev *pdev)
1da177e4
LT		 1368{
1369 return dev_get_drvdata(&pdev->dev);
1370}
1371
05cca6e5 1372static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1da177e4
LT		 1373{
1374 dev_set_drvdata(&pdev->dev, data);
1375}
1376
1377/* If you want to know what to call your pci_dev, ask this function.
1378 * Again, it's a wrapper around the generic device.
1379 */
2fc90f61 1380static inline const char *pci_name(const struct pci_dev *pdev)
1da177e4 1381{
c6c4f070 1382 return dev_name(&pdev->dev);
1da177e4
LT		 1383}
1384
2311b1f2
ME		 1385
1386/* Some archs don't want to expose struct resource to userland as-is
1387 * in sysfs and /proc
1388 */
1389#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1390static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
05cca6e5 1391 const struct resource *rsrc, resource_size_t *start,
e31dd6e4 1392 resource_size_t *end)
2311b1f2
ME		 1393{
1394 *start = rsrc->start;
1395 *end = rsrc->end;
1396}
1397#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1398
1399
1da177e4
LT		 1400/*
1401 * The world is not perfect and supplies us with broken PCI devices.
1402 * For at least a part of these bugs we need a work-around, so both
1403 * generic (drivers/pci/quirks.c) and per-architecture code can define
1404 * fixup hooks to be called for particular buggy devices.
1405 */
1406
1407struct pci_fixup {
f4ca5c6a
YL		 1408 u16 vendor; /* You can use PCI_ANY_ID here of course */
1409 u16 device; /* You can use PCI_ANY_ID here of course */
1410 u32 class; /* You can use PCI_ANY_ID here too */
1411 unsigned int class_shift; /* should be 0, 8, 16 */
1da177e4
LT		 1412 void (*hook)(struct pci_dev *dev);
1413};
1414
1415enum pci_fixup_pass {
1416 pci_fixup_early, /* Before probing BARs */
1417 pci_fixup_header, /* After reading configuration header */
1418 pci_fixup_final, /* Final phase of device fixups */
1419 pci_fixup_enable, /* pci_enable_device() time */
e1a2a51e
RW		 1420 pci_fixup_resume, /* pci_device_resume() */
1421 pci_fixup_suspend, /* pci_device_suspend */
1422 pci_fixup_resume_early, /* pci_device_resume_early() */
1da177e4
LT		 1423};
1424
1425/* Anonymous variables would be nice... */
f4ca5c6a
YL		 1426#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1427 class_shift, hook) \
1428 static const struct pci_fixup const __pci_fixup_##name __used \
1429 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1430 = { vendor, device, class, class_shift, hook };
1431
1432#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1433 class_shift, hook) \
1434 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1435 vendor##device##hook, vendor, device, class, class_shift, hook)
1436#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1437 class_shift, hook) \
1438 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1439 vendor##device##hook, vendor, device, class, class_shift, hook)
1440#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1441 class_shift, hook) \
1442 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1443 vendor##device##hook, vendor, device, class, class_shift, hook)
1444#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1445 class_shift, hook) \
1446 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1447 vendor##device##hook, vendor, device, class, class_shift, hook)
1448#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1449 class_shift, hook) \
1450 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1451 resume##vendor##device##hook, vendor, device, class, \
1452 class_shift, hook)
1453#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1454 class_shift, hook) \
1455 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1456 resume_early##vendor##device##hook, vendor, device, \
1457 class, class_shift, hook)
1458#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1459 class_shift, hook) \
1460 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1461 suspend##vendor##device##hook, vendor, device, class, \
1462 class_shift, hook)
1463
1da177e4
LT		 1464#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1465 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
f4ca5c6a 1466 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1467#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1468 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
f4ca5c6a 1469 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1470#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1471 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
f4ca5c6a 1472 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1473#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1474 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
f4ca5c6a 1475 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1597cacb
AC		 1476#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1477 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
f4ca5c6a
YL		 1478 resume##vendor##device##hook, vendor, device, \
1479 PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1480#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1481 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
f4ca5c6a
YL		 1482 resume_early##vendor##device##hook, vendor, device, \
1483 PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1484#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1485 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
f4ca5c6a
YL		 1486 suspend##vendor##device##hook, vendor, device, \
1487 PCI_ANY_ID, 0, hook)
1da177e4 1488
93177a74 1489#ifdef CONFIG_PCI_QUIRKS
1da177e4 1490void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
93177a74
RW		 1491#else
1492static inline void pci_fixup_device(enum pci_fixup_pass pass,
1493 struct pci_dev *dev) {}
1494#endif
1da177e4 1495
05cca6e5 1496void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
5ea81769 1497void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
05cca6e5 1498void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
fb7ebfe4
YL		 1499int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1500int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
916fbfb7 1501 const char *name);
fb7ebfe4 1502void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
5ea81769 1503
1da177e4 1504extern int pci_pci_problems;
236561e5 1505#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 1506#define PCIPCI_TRITON 2
1507#define PCIPCI_NATOMA 4
1508#define PCIPCI_VIAETBF 8
1509#define PCIPCI_VSFX 16
236561e5
AC		 1510#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1511#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4 1512
4516a618
AN		 1513extern unsigned long pci_cardbus_io_size;
1514extern unsigned long pci_cardbus_mem_size;
491424c0 1515extern u8 __devinitdata pci_dfl_cache_line_size;
ac1aa47b 1516extern u8 pci_cache_line_size;
4516a618 1517
28760489
EB		 1518extern unsigned long pci_hotplug_io_size;
1519extern unsigned long pci_hotplug_mem_size;
1520
cfce9fb8 1521/* Architecture specific versions may override these (weak) */
19792a08
AB		 1522int pcibios_add_platform_entries(struct pci_dev *dev);
1523void pcibios_disable_device(struct pci_dev *dev);
cfce9fb8 1524void pcibios_set_master(struct pci_dev *dev);
19792a08
AB		 1525int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1526 enum pcie_reset_state state);
575e3348 1527
7752d5cf 1528#ifdef CONFIG_PCI_MMCONFIG
bb63b421 1529extern void __init pci_mmcfg_early_init(void);
7752d5cf
RH		 1530extern void __init pci_mmcfg_late_init(void);
1531#else
bb63b421 1532static inline void pci_mmcfg_early_init(void) { }
7752d5cf
RH		 1533static inline void pci_mmcfg_late_init(void) { }
1534#endif
1535
0ef5f8f6
AP		 1536int pci_ext_cfg_avail(struct pci_dev *dev);
1537
1684f5dd 1538void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
aa42d7c6 1539
dd7cc44d
YZ		 1540#ifdef CONFIG_PCI_IOV
1541extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1542extern void pci_disable_sriov(struct pci_dev *dev);
74bb1bcc 1543extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
fb8a0d9d 1544extern int pci_num_vf(struct pci_dev *dev);
dd7cc44d
YZ		 1545#else
1546static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1547{
1548 return -ENODEV;
1549}
1550static inline void pci_disable_sriov(struct pci_dev *dev)
1551{
1552}
74bb1bcc
YZ		 1553static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1554{
1555 return IRQ_NONE;
1556}
fb8a0d9d
WM		 1557static inline int pci_num_vf(struct pci_dev *dev)
1558{
1559 return 0;
1560}
dd7cc44d
YZ		 1561#endif
1562
c825bc94
KK		 1563#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1564extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1565extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1566#endif
1567
d7b7e605
KK		 1568/**
1569 * pci_pcie_cap - get the saved PCIe capability offset
1570 * @dev: PCI device
1571 *
1572 * PCIe capability offset is calculated at PCI device initialization
1573 * time and saved in the data structure. This function returns saved
1574 * PCIe capability offset. Using this instead of pci_find_capability()
1575 * reduces unnecessary search in the PCI configuration space. If you
1576 * need to calculate PCIe capability offset from raw device for some
1577 * reasons, please use pci_find_capability() instead.
1578 */
1579static inline int pci_pcie_cap(struct pci_dev *dev)
1580{
1581 return dev->pcie_cap;
1582}
1583
7eb776c4
KK		 1584/**
1585 * pci_is_pcie - check if the PCI device is PCI Express capable
1586 * @dev: PCI device
1587 *
1588 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1589 */
1590static inline bool pci_is_pcie(struct pci_dev *dev)
1591{
1592 return !!pci_pcie_cap(dev);
1593}
1594
5d990b62
CW		 1595void pci_request_acs(void);
1596
a2ce7662 1597
7ad506fa
MC		 1598#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1599#define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1600
1601/* Large Resource Data Type Tag Item Names */
1602#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1603#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1604#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1605
1606#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1607#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1608#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1609
1610/* Small Resource Data Type Tag Item Names */
1611#define PCI_VPD_STIN_END 0x78 /* End */
1612
1613#define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1614
1615#define PCI_VPD_SRDT_TIN_MASK 0x78
1616#define PCI_VPD_SRDT_LEN_MASK 0x07
1617
1618#define PCI_VPD_LRDT_TAG_SIZE 3
1619#define PCI_VPD_SRDT_TAG_SIZE 1
a2ce7662 1620
e1d5bdab
MC		 1621#define PCI_VPD_INFO_FLD_HDR_SIZE 3
1622
4067a854
MC		 1623#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1624#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1625#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
d4894f3e 1626#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
4067a854 1627
a2ce7662
MC		 1628/**
1629 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1630 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1631 *
1632 * Returns the extracted Large Resource Data Type length.
1633 */
1634static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1635{
1636 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1637}
1638
7ad506fa
MC		 1639/**
1640 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1641 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1642 *
1643 * Returns the extracted Small Resource Data Type length.
1644 */
1645static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1646{
1647 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1648}
1649
e1d5bdab
MC		 1650/**
1651 * pci_vpd_info_field_size - Extracts the information field length
1652 * @lrdt: Pointer to the beginning of an information field header
1653 *
1654 * Returns the extracted information field length.
1655 */
1656static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1657{
1658 return info_field[2];
1659}
1660
b55ac1b2
MC		 1661/**
1662 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1663 * @buf: Pointer to buffered vpd data
1664 * @off: The offset into the buffer at which to begin the search
1665 * @len: The length of the vpd buffer
1666 * @rdt: The Resource Data Type to search for
1667 *
1668 * Returns the index where the Resource Data Type was found or
1669 * -ENOENT otherwise.
1670 */
1671int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1672
4067a854
MC		 1673/**
1674 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1675 * @buf: Pointer to buffered vpd data
1676 * @off: The offset into the buffer at which to begin the search
1677 * @len: The length of the buffer area, relative to off, in which to search
1678 * @kw: The keyword to search for
1679 *
1680 * Returns the index where the information field keyword was found or
1681 * -ENOENT otherwise.
1682 */
1683int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1684 unsigned int len, const char *kw);
1685
98d9f30c
BH		 1686/* PCI <-> OF binding helpers */
1687#ifdef CONFIG_OF
1688struct device_node;
1689extern void pci_set_of_node(struct pci_dev *dev);
1690extern void pci_release_of_node(struct pci_dev *dev);
1691extern void pci_set_bus_of_node(struct pci_bus *bus);
1692extern void pci_release_bus_of_node(struct pci_bus *bus);
1693
1694/* Arch may override this (weak) */
1695extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus);
1696
3df425f3
JC		 1697static inline struct device_node *
1698pci_device_to_OF_node(const struct pci_dev *pdev)
64099d98
BH		 1699{
1700 return pdev ? pdev->dev.of_node : NULL;
1701}
1702
ef3b4f8c
BH		 1703static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1704{
1705 return bus ? bus->dev.of_node : NULL;
1706}
1707
98d9f30c
BH		 1708#else /* CONFIG_OF */
1709static inline void pci_set_of_node(struct pci_dev *dev) { }
1710static inline void pci_release_of_node(struct pci_dev *dev) { }
1711static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1712static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1713#endif /* CONFIG_OF */
1714
eb740b5f
GS		 1715#ifdef CONFIG_EEH
1716static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1717{
1718 return pdev->dev.archdata.edev;
1719}
1720#endif
1721
166e9278
OBC		 1722/**
1723 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1724 * @pdev: the PCI device
1725 *
1726 * if the device is PCIE, return NULL
1727 * if the device isn't connected to a PCIe bridge (that is its parent is a
1728 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1729 * parent
1730 */
1731struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1732
1da177e4
LT		 1733#endif /* __KERNEL__ */
1734#endif /* LINUX_PCI_H */
Linux kernel - Deliverables
This page took 1.4955 seconds and 5 git commands to generate.