Commit | Line | Data |
---|---|---|
0793a61d TG |
1 | /* |
2 | * Performance counters: | |
3 | * | |
4 | * Copyright(C) 2008, Thomas Gleixner <tglx@linutronix.de> | |
5 | * Copyright(C) 2008, Red Hat, Inc., Ingo Molnar | |
6 | * | |
7 | * Data type definitions, declarations, prototypes. | |
8 | * | |
9 | * Started by: Thomas Gleixner and Ingo Molnar | |
10 | * | |
11 | * For licencing details see kernel-base/COPYING | |
12 | */ | |
13 | #ifndef _LINUX_PERF_COUNTER_H | |
14 | #define _LINUX_PERF_COUNTER_H | |
15 | ||
f3dfd265 PM |
16 | #include <linux/types.h> |
17 | #include <linux/ioctl.h> | |
9aaa131a | 18 | #include <asm/byteorder.h> |
0793a61d TG |
19 | |
20 | /* | |
9f66a381 IM |
21 | * User-space ABI bits: |
22 | */ | |
23 | ||
24 | /* | |
b8e83514 | 25 | * hw_event.type |
0793a61d | 26 | */ |
b8e83514 PZ |
27 | enum perf_event_types { |
28 | PERF_TYPE_HARDWARE = 0, | |
29 | PERF_TYPE_SOFTWARE = 1, | |
30 | PERF_TYPE_TRACEPOINT = 2, | |
31 | ||
0793a61d | 32 | /* |
b8e83514 | 33 | * available TYPE space, raw is the max value. |
0793a61d | 34 | */ |
9f66a381 | 35 | |
b8e83514 PZ |
36 | PERF_TYPE_RAW = 128, |
37 | }; | |
6c594c21 | 38 | |
b8e83514 PZ |
39 | /* |
40 | * Generalized performance counter event types, used by the hw_event.event_id | |
41 | * parameter of the sys_perf_counter_open() syscall: | |
42 | */ | |
43 | enum hw_event_ids { | |
9f66a381 | 44 | /* |
b8e83514 | 45 | * Common hardware events, generalized by the kernel: |
9f66a381 | 46 | */ |
b8e83514 PZ |
47 | PERF_COUNT_CPU_CYCLES = 0, |
48 | PERF_COUNT_INSTRUCTIONS = 1, | |
49 | PERF_COUNT_CACHE_REFERENCES = 2, | |
50 | PERF_COUNT_CACHE_MISSES = 3, | |
51 | PERF_COUNT_BRANCH_INSTRUCTIONS = 4, | |
52 | PERF_COUNT_BRANCH_MISSES = 5, | |
53 | PERF_COUNT_BUS_CYCLES = 6, | |
54 | ||
55 | PERF_HW_EVENTS_MAX = 7, | |
56 | }; | |
e077df4f | 57 | |
b8e83514 PZ |
58 | /* |
59 | * Special "software" counters provided by the kernel, even if the hardware | |
60 | * does not support performance counters. These counters measure various | |
61 | * physical and sw events of the kernel (and allow the profiling of them as | |
62 | * well): | |
63 | */ | |
64 | enum sw_event_ids { | |
65 | PERF_COUNT_CPU_CLOCK = 0, | |
66 | PERF_COUNT_TASK_CLOCK = 1, | |
67 | PERF_COUNT_PAGE_FAULTS = 2, | |
68 | PERF_COUNT_CONTEXT_SWITCHES = 3, | |
69 | PERF_COUNT_CPU_MIGRATIONS = 4, | |
70 | PERF_COUNT_PAGE_FAULTS_MIN = 5, | |
71 | PERF_COUNT_PAGE_FAULTS_MAJ = 6, | |
72 | ||
73 | PERF_SW_EVENTS_MAX = 7, | |
0793a61d TG |
74 | }; |
75 | ||
f4a2deb4 PZ |
76 | #define __PERF_COUNTER_MASK(name) \ |
77 | (((1ULL << PERF_COUNTER_##name##_BITS) - 1) << \ | |
78 | PERF_COUNTER_##name##_SHIFT) | |
79 | ||
80 | #define PERF_COUNTER_RAW_BITS 1 | |
81 | #define PERF_COUNTER_RAW_SHIFT 63 | |
82 | #define PERF_COUNTER_RAW_MASK __PERF_COUNTER_MASK(RAW) | |
83 | ||
84 | #define PERF_COUNTER_CONFIG_BITS 63 | |
85 | #define PERF_COUNTER_CONFIG_SHIFT 0 | |
86 | #define PERF_COUNTER_CONFIG_MASK __PERF_COUNTER_MASK(CONFIG) | |
87 | ||
88 | #define PERF_COUNTER_TYPE_BITS 7 | |
89 | #define PERF_COUNTER_TYPE_SHIFT 56 | |
90 | #define PERF_COUNTER_TYPE_MASK __PERF_COUNTER_MASK(TYPE) | |
91 | ||
92 | #define PERF_COUNTER_EVENT_BITS 56 | |
93 | #define PERF_COUNTER_EVENT_SHIFT 0 | |
94 | #define PERF_COUNTER_EVENT_MASK __PERF_COUNTER_MASK(EVENT) | |
95 | ||
8a057d84 PZ |
96 | /* |
97 | * Bits that can be set in hw_event.record_type to request information | |
98 | * in the overflow packets. | |
99 | */ | |
100 | enum perf_counter_record_format { | |
101 | PERF_RECORD_IP = 1U << 0, | |
102 | PERF_RECORD_TID = 1U << 1, | |
103 | PERF_RECORD_GROUP = 1U << 2, | |
104 | PERF_RECORD_CALLCHAIN = 1U << 3, | |
105 | }; | |
106 | ||
53cfbf59 PM |
107 | /* |
108 | * Bits that can be set in hw_event.read_format to request that | |
109 | * reads on the counter should return the indicated quantities, | |
110 | * in increasing order of bit value, after the counter value. | |
111 | */ | |
112 | enum perf_counter_read_format { | |
113 | PERF_FORMAT_TOTAL_TIME_ENABLED = 1, | |
114 | PERF_FORMAT_TOTAL_TIME_RUNNING = 2, | |
115 | }; | |
116 | ||
9f66a381 IM |
117 | /* |
118 | * Hardware event to monitor via a performance monitoring counter: | |
119 | */ | |
120 | struct perf_counter_hw_event { | |
f4a2deb4 PZ |
121 | /* |
122 | * The MSB of the config word signifies if the rest contains cpu | |
123 | * specific (raw) counter configuration data, if unset, the next | |
124 | * 7 bits are an event type and the rest of the bits are the event | |
125 | * identifier. | |
126 | */ | |
127 | __u64 config; | |
9f66a381 | 128 | |
f3dfd265 | 129 | __u64 irq_period; |
8a057d84 PZ |
130 | __u32 record_type; |
131 | __u32 read_format; | |
9f66a381 | 132 | |
2743a5b0 | 133 | __u64 disabled : 1, /* off by default */ |
0475f9ea | 134 | nmi : 1, /* NMI sampling */ |
0475f9ea PM |
135 | inherit : 1, /* children inherit it */ |
136 | pinned : 1, /* must always be on PMU */ | |
137 | exclusive : 1, /* only group on PMU */ | |
138 | exclude_user : 1, /* don't count user */ | |
139 | exclude_kernel : 1, /* ditto kernel */ | |
140 | exclude_hv : 1, /* ditto hypervisor */ | |
2743a5b0 | 141 | exclude_idle : 1, /* don't count when idle */ |
0a4a9391 PZ |
142 | mmap : 1, /* include mmap data */ |
143 | munmap : 1, /* include munmap data */ | |
0475f9ea | 144 | |
8a057d84 | 145 | __reserved_1 : 53; |
2743a5b0 PM |
146 | |
147 | __u32 extra_config_len; | |
148 | __u32 __reserved_4; | |
9f66a381 | 149 | |
f3dfd265 | 150 | __u64 __reserved_2; |
2743a5b0 | 151 | __u64 __reserved_3; |
eab656ae TG |
152 | }; |
153 | ||
d859e29f PM |
154 | /* |
155 | * Ioctls that can be done on a perf counter fd: | |
156 | */ | |
157 | #define PERF_COUNTER_IOC_ENABLE _IO('$', 0) | |
158 | #define PERF_COUNTER_IOC_DISABLE _IO('$', 1) | |
159 | ||
37d81828 PM |
160 | /* |
161 | * Structure of the page that can be mapped via mmap | |
162 | */ | |
163 | struct perf_counter_mmap_page { | |
164 | __u32 version; /* version number of this structure */ | |
165 | __u32 compat_version; /* lowest version this is compat with */ | |
38ff667b PZ |
166 | |
167 | /* | |
168 | * Bits needed to read the hw counters in user-space. | |
169 | * | |
170 | * The index and offset should be read atomically using the seqlock: | |
171 | * | |
172 | * __u32 seq, index; | |
173 | * __s64 offset; | |
174 | * | |
175 | * again: | |
176 | * rmb(); | |
177 | * seq = pc->lock; | |
178 | * | |
179 | * if (unlikely(seq & 1)) { | |
180 | * cpu_relax(); | |
181 | * goto again; | |
182 | * } | |
183 | * | |
184 | * index = pc->index; | |
185 | * offset = pc->offset; | |
186 | * | |
187 | * rmb(); | |
188 | * if (pc->lock != seq) | |
189 | * goto again; | |
190 | * | |
191 | * After this, index contains architecture specific counter index + 1, | |
192 | * so that 0 means unavailable, offset contains the value to be added | |
193 | * to the result of the raw timer read to obtain this counter's value. | |
194 | */ | |
37d81828 PM |
195 | __u32 lock; /* seqlock for synchronization */ |
196 | __u32 index; /* hardware counter identifier */ | |
197 | __s64 offset; /* add to hardware counter value */ | |
7b732a75 | 198 | |
38ff667b PZ |
199 | /* |
200 | * Control data for the mmap() data buffer. | |
201 | * | |
202 | * User-space reading this value should issue an rmb(), on SMP capable | |
203 | * platforms, after reading this value -- see perf_counter_wakeup(). | |
204 | */ | |
7b732a75 | 205 | __u32 data_head; /* head in the data section */ |
37d81828 PM |
206 | }; |
207 | ||
5c148194 PZ |
208 | struct perf_event_header { |
209 | __u32 type; | |
210 | __u32 size; | |
211 | }; | |
212 | ||
213 | enum perf_event_type { | |
5ed00415 | 214 | |
8a057d84 PZ |
215 | PERF_EVENT_MMAP = 1, |
216 | PERF_EVENT_MUNMAP = 2, | |
0a4a9391 | 217 | |
8a057d84 PZ |
218 | /* |
219 | * Half the event type space is reserved for the counter overflow | |
220 | * bitfields, as found in hw_event.record_type. | |
221 | * | |
222 | * These events will have types of the form: | |
223 | * PERF_EVENT_COUNTER_OVERFLOW { | __PERF_EVENT_* } * | |
224 | */ | |
225 | PERF_EVENT_COUNTER_OVERFLOW = 1UL << 31, | |
226 | __PERF_EVENT_IP = PERF_RECORD_IP, | |
227 | __PERF_EVENT_TID = PERF_RECORD_TID, | |
228 | __PERF_EVENT_GROUP = PERF_RECORD_GROUP, | |
229 | __PERF_EVENT_CALLCHAIN = PERF_RECORD_CALLCHAIN, | |
5c148194 PZ |
230 | }; |
231 | ||
f3dfd265 | 232 | #ifdef __KERNEL__ |
9f66a381 | 233 | /* |
f3dfd265 | 234 | * Kernel-internal data types and definitions: |
9f66a381 IM |
235 | */ |
236 | ||
f3dfd265 PM |
237 | #ifdef CONFIG_PERF_COUNTERS |
238 | # include <asm/perf_counter.h> | |
239 | #endif | |
240 | ||
241 | #include <linux/list.h> | |
242 | #include <linux/mutex.h> | |
243 | #include <linux/rculist.h> | |
244 | #include <linux/rcupdate.h> | |
245 | #include <linux/spinlock.h> | |
d6d020e9 | 246 | #include <linux/hrtimer.h> |
f3dfd265 PM |
247 | #include <asm/atomic.h> |
248 | ||
249 | struct task_struct; | |
250 | ||
f4a2deb4 PZ |
251 | static inline u64 perf_event_raw(struct perf_counter_hw_event *hw_event) |
252 | { | |
253 | return hw_event->config & PERF_COUNTER_RAW_MASK; | |
254 | } | |
255 | ||
256 | static inline u64 perf_event_config(struct perf_counter_hw_event *hw_event) | |
257 | { | |
258 | return hw_event->config & PERF_COUNTER_CONFIG_MASK; | |
259 | } | |
260 | ||
261 | static inline u64 perf_event_type(struct perf_counter_hw_event *hw_event) | |
262 | { | |
263 | return (hw_event->config & PERF_COUNTER_TYPE_MASK) >> | |
264 | PERF_COUNTER_TYPE_SHIFT; | |
265 | } | |
266 | ||
267 | static inline u64 perf_event_id(struct perf_counter_hw_event *hw_event) | |
268 | { | |
269 | return hw_event->config & PERF_COUNTER_EVENT_MASK; | |
270 | } | |
271 | ||
0793a61d | 272 | /** |
9f66a381 | 273 | * struct hw_perf_counter - performance counter hardware details: |
0793a61d TG |
274 | */ |
275 | struct hw_perf_counter { | |
ee06094f | 276 | #ifdef CONFIG_PERF_COUNTERS |
d6d020e9 PZ |
277 | union { |
278 | struct { /* hardware */ | |
279 | u64 config; | |
280 | unsigned long config_base; | |
281 | unsigned long counter_base; | |
282 | int nmi; | |
283 | unsigned int idx; | |
284 | }; | |
285 | union { /* software */ | |
286 | atomic64_t count; | |
287 | struct hrtimer hrtimer; | |
288 | }; | |
289 | }; | |
ee06094f | 290 | atomic64_t prev_count; |
9f66a381 | 291 | u64 irq_period; |
ee06094f IM |
292 | atomic64_t period_left; |
293 | #endif | |
0793a61d TG |
294 | }; |
295 | ||
621a01ea IM |
296 | struct perf_counter; |
297 | ||
298 | /** | |
299 | * struct hw_perf_counter_ops - performance counter hw ops | |
300 | */ | |
301 | struct hw_perf_counter_ops { | |
95cdd2e7 | 302 | int (*enable) (struct perf_counter *counter); |
7671581f IM |
303 | void (*disable) (struct perf_counter *counter); |
304 | void (*read) (struct perf_counter *counter); | |
621a01ea IM |
305 | }; |
306 | ||
6a930700 IM |
307 | /** |
308 | * enum perf_counter_active_state - the states of a counter | |
309 | */ | |
310 | enum perf_counter_active_state { | |
3b6f9e5c | 311 | PERF_COUNTER_STATE_ERROR = -2, |
6a930700 IM |
312 | PERF_COUNTER_STATE_OFF = -1, |
313 | PERF_COUNTER_STATE_INACTIVE = 0, | |
314 | PERF_COUNTER_STATE_ACTIVE = 1, | |
315 | }; | |
316 | ||
9b51f66d IM |
317 | struct file; |
318 | ||
7b732a75 PZ |
319 | struct perf_mmap_data { |
320 | struct rcu_head rcu_head; | |
321 | int nr_pages; | |
c7138f37 | 322 | atomic_t wakeup; |
7b732a75 PZ |
323 | atomic_t head; |
324 | struct perf_counter_mmap_page *user_page; | |
325 | void *data_pages[0]; | |
326 | }; | |
327 | ||
925d519a PZ |
328 | struct perf_wakeup_entry { |
329 | struct perf_wakeup_entry *next; | |
330 | }; | |
331 | ||
0793a61d TG |
332 | /** |
333 | * struct perf_counter - performance counter kernel representation: | |
334 | */ | |
335 | struct perf_counter { | |
ee06094f | 336 | #ifdef CONFIG_PERF_COUNTERS |
04289bb9 | 337 | struct list_head list_entry; |
592903cd | 338 | struct list_head event_entry; |
04289bb9 | 339 | struct list_head sibling_list; |
5c148194 | 340 | int nr_siblings; |
04289bb9 | 341 | struct perf_counter *group_leader; |
5c92d124 | 342 | const struct hw_perf_counter_ops *hw_ops; |
04289bb9 | 343 | |
6a930700 | 344 | enum perf_counter_active_state state; |
c07c99b6 | 345 | enum perf_counter_active_state prev_state; |
0793a61d | 346 | atomic64_t count; |
ee06094f | 347 | |
53cfbf59 PM |
348 | /* |
349 | * These are the total time in nanoseconds that the counter | |
350 | * has been enabled (i.e. eligible to run, and the task has | |
351 | * been scheduled in, if this is a per-task counter) | |
352 | * and running (scheduled onto the CPU), respectively. | |
353 | * | |
354 | * They are computed from tstamp_enabled, tstamp_running and | |
355 | * tstamp_stopped when the counter is in INACTIVE or ACTIVE state. | |
356 | */ | |
357 | u64 total_time_enabled; | |
358 | u64 total_time_running; | |
359 | ||
360 | /* | |
361 | * These are timestamps used for computing total_time_enabled | |
362 | * and total_time_running when the counter is in INACTIVE or | |
363 | * ACTIVE state, measured in nanoseconds from an arbitrary point | |
364 | * in time. | |
365 | * tstamp_enabled: the notional time when the counter was enabled | |
366 | * tstamp_running: the notional time when the counter was scheduled on | |
367 | * tstamp_stopped: in INACTIVE state, the notional time when the | |
368 | * counter was scheduled off. | |
369 | */ | |
370 | u64 tstamp_enabled; | |
371 | u64 tstamp_running; | |
372 | u64 tstamp_stopped; | |
373 | ||
9f66a381 | 374 | struct perf_counter_hw_event hw_event; |
0793a61d TG |
375 | struct hw_perf_counter hw; |
376 | ||
377 | struct perf_counter_context *ctx; | |
378 | struct task_struct *task; | |
9b51f66d | 379 | struct file *filp; |
0793a61d | 380 | |
9b51f66d | 381 | struct perf_counter *parent; |
d859e29f PM |
382 | struct list_head child_list; |
383 | ||
53cfbf59 PM |
384 | /* |
385 | * These accumulate total time (in nanoseconds) that children | |
386 | * counters have been enabled and running, respectively. | |
387 | */ | |
388 | atomic64_t child_total_time_enabled; | |
389 | atomic64_t child_total_time_running; | |
390 | ||
0793a61d | 391 | /* |
d859e29f | 392 | * Protect attach/detach and child_list: |
0793a61d TG |
393 | */ |
394 | struct mutex mutex; | |
395 | ||
396 | int oncpu; | |
397 | int cpu; | |
398 | ||
7b732a75 PZ |
399 | /* mmap bits */ |
400 | struct mutex mmap_mutex; | |
401 | atomic_t mmap_count; | |
402 | struct perf_mmap_data *data; | |
37d81828 | 403 | |
7b732a75 | 404 | /* poll related */ |
0793a61d TG |
405 | wait_queue_head_t waitq; |
406 | /* optional: for NMIs */ | |
925d519a | 407 | struct perf_wakeup_entry wakeup; |
592903cd | 408 | |
e077df4f | 409 | void (*destroy)(struct perf_counter *); |
592903cd | 410 | struct rcu_head rcu_head; |
ee06094f | 411 | #endif |
0793a61d TG |
412 | }; |
413 | ||
414 | /** | |
415 | * struct perf_counter_context - counter context structure | |
416 | * | |
417 | * Used as a container for task counters and CPU counters as well: | |
418 | */ | |
419 | struct perf_counter_context { | |
420 | #ifdef CONFIG_PERF_COUNTERS | |
421 | /* | |
d859e29f PM |
422 | * Protect the states of the counters in the list, |
423 | * nr_active, and the list: | |
0793a61d TG |
424 | */ |
425 | spinlock_t lock; | |
d859e29f PM |
426 | /* |
427 | * Protect the list of counters. Locking either mutex or lock | |
428 | * is sufficient to ensure the list doesn't change; to change | |
429 | * the list you need to lock both the mutex and the spinlock. | |
430 | */ | |
431 | struct mutex mutex; | |
04289bb9 IM |
432 | |
433 | struct list_head counter_list; | |
592903cd | 434 | struct list_head event_list; |
0793a61d TG |
435 | int nr_counters; |
436 | int nr_active; | |
d859e29f | 437 | int is_active; |
0793a61d | 438 | struct task_struct *task; |
53cfbf59 PM |
439 | |
440 | /* | |
441 | * time_now is the current time in nanoseconds since an arbitrary | |
442 | * point in the past. For per-task counters, this is based on the | |
443 | * task clock, and for per-cpu counters it is based on the cpu clock. | |
444 | * time_lost is an offset from the task/cpu clock, used to make it | |
445 | * appear that time only passes while the context is scheduled in. | |
446 | */ | |
447 | u64 time_now; | |
448 | u64 time_lost; | |
0793a61d TG |
449 | #endif |
450 | }; | |
451 | ||
452 | /** | |
453 | * struct perf_counter_cpu_context - per cpu counter context structure | |
454 | */ | |
455 | struct perf_cpu_context { | |
456 | struct perf_counter_context ctx; | |
457 | struct perf_counter_context *task_ctx; | |
458 | int active_oncpu; | |
459 | int max_pertask; | |
3b6f9e5c | 460 | int exclusive; |
96f6d444 PZ |
461 | |
462 | /* | |
463 | * Recursion avoidance: | |
464 | * | |
465 | * task, softirq, irq, nmi context | |
466 | */ | |
467 | int recursion[4]; | |
0793a61d TG |
468 | }; |
469 | ||
470 | /* | |
471 | * Set by architecture code: | |
472 | */ | |
473 | extern int perf_max_counters; | |
474 | ||
475 | #ifdef CONFIG_PERF_COUNTERS | |
5c92d124 | 476 | extern const struct hw_perf_counter_ops * |
621a01ea IM |
477 | hw_perf_counter_init(struct perf_counter *counter); |
478 | ||
0793a61d TG |
479 | extern void perf_counter_task_sched_in(struct task_struct *task, int cpu); |
480 | extern void perf_counter_task_sched_out(struct task_struct *task, int cpu); | |
481 | extern void perf_counter_task_tick(struct task_struct *task, int cpu); | |
9b51f66d IM |
482 | extern void perf_counter_init_task(struct task_struct *child); |
483 | extern void perf_counter_exit_task(struct task_struct *child); | |
925d519a | 484 | extern void perf_counter_do_pending(void); |
0793a61d | 485 | extern void perf_counter_print_debug(void); |
1b023a96 | 486 | extern void perf_counter_unthrottle(void); |
01b2838c IM |
487 | extern u64 hw_perf_save_disable(void); |
488 | extern void hw_perf_restore(u64 ctrl); | |
1d1c7ddb IM |
489 | extern int perf_counter_task_disable(void); |
490 | extern int perf_counter_task_enable(void); | |
3cbed429 PM |
491 | extern int hw_perf_group_sched_in(struct perf_counter *group_leader, |
492 | struct perf_cpu_context *cpuctx, | |
493 | struct perf_counter_context *ctx, int cpu); | |
37d81828 | 494 | extern void perf_counter_update_userpage(struct perf_counter *counter); |
5c92d124 | 495 | |
0322cd6e PZ |
496 | extern void perf_counter_output(struct perf_counter *counter, |
497 | int nmi, struct pt_regs *regs); | |
3b6f9e5c PM |
498 | /* |
499 | * Return 1 for a software counter, 0 for a hardware counter | |
500 | */ | |
501 | static inline int is_software_counter(struct perf_counter *counter) | |
502 | { | |
f4a2deb4 PZ |
503 | return !perf_event_raw(&counter->hw_event) && |
504 | perf_event_type(&counter->hw_event) != PERF_TYPE_HARDWARE; | |
3b6f9e5c PM |
505 | } |
506 | ||
b8e83514 | 507 | extern void perf_swcounter_event(u32, u64, int, struct pt_regs *); |
15dbf27c | 508 | |
0a4a9391 PZ |
509 | extern void perf_counter_mmap(unsigned long addr, unsigned long len, |
510 | unsigned long pgoff, struct file *file); | |
511 | ||
512 | extern void perf_counter_munmap(unsigned long addr, unsigned long len, | |
513 | unsigned long pgoff, struct file *file); | |
514 | ||
394ee076 PZ |
515 | #define MAX_STACK_DEPTH 255 |
516 | ||
517 | struct perf_callchain_entry { | |
518 | u64 nr; | |
519 | u64 ip[MAX_STACK_DEPTH]; | |
520 | }; | |
521 | ||
522 | extern struct perf_callchain_entry *perf_callchain(struct pt_regs *regs); | |
523 | ||
0793a61d TG |
524 | #else |
525 | static inline void | |
526 | perf_counter_task_sched_in(struct task_struct *task, int cpu) { } | |
527 | static inline void | |
528 | perf_counter_task_sched_out(struct task_struct *task, int cpu) { } | |
529 | static inline void | |
530 | perf_counter_task_tick(struct task_struct *task, int cpu) { } | |
9b51f66d IM |
531 | static inline void perf_counter_init_task(struct task_struct *child) { } |
532 | static inline void perf_counter_exit_task(struct task_struct *child) { } | |
925d519a | 533 | static inline void perf_counter_do_pending(void) { } |
0793a61d | 534 | static inline void perf_counter_print_debug(void) { } |
1b023a96 | 535 | static inline void perf_counter_unthrottle(void) { } |
15dbf27c | 536 | static inline void hw_perf_restore(u64 ctrl) { } |
01b2838c | 537 | static inline u64 hw_perf_save_disable(void) { return 0; } |
1d1c7ddb IM |
538 | static inline int perf_counter_task_disable(void) { return -EINVAL; } |
539 | static inline int perf_counter_task_enable(void) { return -EINVAL; } | |
15dbf27c | 540 | |
925d519a PZ |
541 | static inline void |
542 | perf_swcounter_event(u32 event, u64 nr, int nmi, struct pt_regs *regs) { } | |
543 | ||
0a4a9391 PZ |
544 | |
545 | static inline void | |
546 | perf_counter_mmap(unsigned long addr, unsigned long len, | |
547 | unsigned long pgoff, struct file *file) { } | |
548 | ||
549 | static inline void | |
550 | perf_counter_munmap(unsigned long addr, unsigned long len, | |
551 | unsigned long pgoff, struct file *file) { } | |
552 | ||
0793a61d TG |
553 | #endif |
554 | ||
f3dfd265 | 555 | #endif /* __KERNEL__ */ |
0793a61d | 556 | #endif /* _LINUX_PERF_COUNTER_H */ |