Commit | Line | Data |
---|---|---|
0793a61d TG |
1 | /* |
2 | * Performance counters: | |
3 | * | |
a308444c IM |
4 | * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009, Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2008-2009, Red Hat, Inc., Peter Zijlstra | |
0793a61d TG |
7 | * |
8 | * Data type definitions, declarations, prototypes. | |
9 | * | |
a308444c | 10 | * Started by: Thomas Gleixner and Ingo Molnar |
0793a61d TG |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | #ifndef _LINUX_PERF_COUNTER_H | |
15 | #define _LINUX_PERF_COUNTER_H | |
16 | ||
f3dfd265 PM |
17 | #include <linux/types.h> |
18 | #include <linux/ioctl.h> | |
9aaa131a | 19 | #include <asm/byteorder.h> |
0793a61d TG |
20 | |
21 | /* | |
9f66a381 IM |
22 | * User-space ABI bits: |
23 | */ | |
24 | ||
25 | /* | |
0d48696f | 26 | * attr.type |
0793a61d | 27 | */ |
1c432d89 | 28 | enum perf_type_id { |
a308444c IM |
29 | PERF_TYPE_HARDWARE = 0, |
30 | PERF_TYPE_SOFTWARE = 1, | |
31 | PERF_TYPE_TRACEPOINT = 2, | |
32 | PERF_TYPE_HW_CACHE = 3, | |
33 | PERF_TYPE_RAW = 4, | |
b8e83514 | 34 | |
a308444c | 35 | PERF_TYPE_MAX, /* non-ABI */ |
b8e83514 | 36 | }; |
6c594c21 | 37 | |
b8e83514 | 38 | /* |
a308444c IM |
39 | * Generalized performance counter event types, used by the |
40 | * attr.event_id parameter of the sys_perf_counter_open() | |
41 | * syscall: | |
b8e83514 | 42 | */ |
1c432d89 | 43 | enum perf_hw_id { |
9f66a381 | 44 | /* |
b8e83514 | 45 | * Common hardware events, generalized by the kernel: |
9f66a381 | 46 | */ |
f4dbfa8f PZ |
47 | PERF_COUNT_HW_CPU_CYCLES = 0, |
48 | PERF_COUNT_HW_INSTRUCTIONS = 1, | |
49 | PERF_COUNT_HW_CACHE_REFERENCES = 2, | |
50 | PERF_COUNT_HW_CACHE_MISSES = 3, | |
51 | PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, | |
52 | PERF_COUNT_HW_BRANCH_MISSES = 5, | |
53 | PERF_COUNT_HW_BUS_CYCLES = 6, | |
54 | ||
a308444c | 55 | PERF_COUNT_HW_MAX, /* non-ABI */ |
b8e83514 | 56 | }; |
e077df4f | 57 | |
8326f44d IM |
58 | /* |
59 | * Generalized hardware cache counters: | |
60 | * | |
8be6e8f3 | 61 | * { L1-D, L1-I, LLC, ITLB, DTLB, BPU } x |
8326f44d IM |
62 | * { read, write, prefetch } x |
63 | * { accesses, misses } | |
64 | */ | |
1c432d89 | 65 | enum perf_hw_cache_id { |
a308444c IM |
66 | PERF_COUNT_HW_CACHE_L1D = 0, |
67 | PERF_COUNT_HW_CACHE_L1I = 1, | |
68 | PERF_COUNT_HW_CACHE_LL = 2, | |
69 | PERF_COUNT_HW_CACHE_DTLB = 3, | |
70 | PERF_COUNT_HW_CACHE_ITLB = 4, | |
71 | PERF_COUNT_HW_CACHE_BPU = 5, | |
72 | ||
73 | PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ | |
8326f44d IM |
74 | }; |
75 | ||
1c432d89 | 76 | enum perf_hw_cache_op_id { |
a308444c IM |
77 | PERF_COUNT_HW_CACHE_OP_READ = 0, |
78 | PERF_COUNT_HW_CACHE_OP_WRITE = 1, | |
79 | PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, | |
8326f44d | 80 | |
a308444c | 81 | PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ |
8326f44d IM |
82 | }; |
83 | ||
1c432d89 PZ |
84 | enum perf_hw_cache_op_result_id { |
85 | PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, | |
86 | PERF_COUNT_HW_CACHE_RESULT_MISS = 1, | |
8326f44d | 87 | |
a308444c | 88 | PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ |
8326f44d IM |
89 | }; |
90 | ||
b8e83514 PZ |
91 | /* |
92 | * Special "software" counters provided by the kernel, even if the hardware | |
93 | * does not support performance counters. These counters measure various | |
94 | * physical and sw events of the kernel (and allow the profiling of them as | |
95 | * well): | |
96 | */ | |
1c432d89 | 97 | enum perf_sw_ids { |
a308444c IM |
98 | PERF_COUNT_SW_CPU_CLOCK = 0, |
99 | PERF_COUNT_SW_TASK_CLOCK = 1, | |
100 | PERF_COUNT_SW_PAGE_FAULTS = 2, | |
101 | PERF_COUNT_SW_CONTEXT_SWITCHES = 3, | |
102 | PERF_COUNT_SW_CPU_MIGRATIONS = 4, | |
103 | PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, | |
104 | PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, | |
105 | ||
106 | PERF_COUNT_SW_MAX, /* non-ABI */ | |
0793a61d TG |
107 | }; |
108 | ||
8a057d84 | 109 | /* |
0d48696f | 110 | * Bits that can be set in attr.sample_type to request information |
8a057d84 PZ |
111 | * in the overflow packets. |
112 | */ | |
b23f3325 | 113 | enum perf_counter_sample_format { |
a308444c IM |
114 | PERF_SAMPLE_IP = 1U << 0, |
115 | PERF_SAMPLE_TID = 1U << 1, | |
116 | PERF_SAMPLE_TIME = 1U << 2, | |
117 | PERF_SAMPLE_ADDR = 1U << 3, | |
118 | PERF_SAMPLE_GROUP = 1U << 4, | |
119 | PERF_SAMPLE_CALLCHAIN = 1U << 5, | |
120 | PERF_SAMPLE_ID = 1U << 6, | |
121 | PERF_SAMPLE_CPU = 1U << 7, | |
122 | PERF_SAMPLE_PERIOD = 1U << 8, | |
7f453c24 | 123 | PERF_SAMPLE_STREAM_ID = 1U << 9, |
3a43ce68 | 124 | PERF_SAMPLE_RAW = 1U << 10, |
974802ea | 125 | |
f413cdb8 | 126 | PERF_SAMPLE_MAX = 1U << 11, /* non-ABI */ |
8a057d84 PZ |
127 | }; |
128 | ||
53cfbf59 | 129 | /* |
0d48696f | 130 | * Bits that can be set in attr.read_format to request that |
53cfbf59 PM |
131 | * reads on the counter should return the indicated quantities, |
132 | * in increasing order of bit value, after the counter value. | |
133 | */ | |
134 | enum perf_counter_read_format { | |
a308444c IM |
135 | PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, |
136 | PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, | |
137 | PERF_FORMAT_ID = 1U << 2, | |
974802ea PZ |
138 | |
139 | PERF_FORMAT_MAX = 1U << 3, /* non-ABI */ | |
53cfbf59 PM |
140 | }; |
141 | ||
974802ea PZ |
142 | #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ |
143 | ||
9f66a381 IM |
144 | /* |
145 | * Hardware event to monitor via a performance monitoring counter: | |
146 | */ | |
0d48696f | 147 | struct perf_counter_attr { |
974802ea | 148 | |
f4a2deb4 | 149 | /* |
a21ca2ca IM |
150 | * Major type: hardware/software/tracepoint/etc. |
151 | */ | |
152 | __u32 type; | |
974802ea PZ |
153 | |
154 | /* | |
155 | * Size of the attr structure, for fwd/bwd compat. | |
156 | */ | |
157 | __u32 size; | |
a21ca2ca IM |
158 | |
159 | /* | |
160 | * Type specific configuration information. | |
f4a2deb4 PZ |
161 | */ |
162 | __u64 config; | |
9f66a381 | 163 | |
60db5e09 | 164 | union { |
b23f3325 PZ |
165 | __u64 sample_period; |
166 | __u64 sample_freq; | |
60db5e09 PZ |
167 | }; |
168 | ||
b23f3325 PZ |
169 | __u64 sample_type; |
170 | __u64 read_format; | |
9f66a381 | 171 | |
2743a5b0 | 172 | __u64 disabled : 1, /* off by default */ |
0475f9ea PM |
173 | inherit : 1, /* children inherit it */ |
174 | pinned : 1, /* must always be on PMU */ | |
175 | exclusive : 1, /* only group on PMU */ | |
176 | exclude_user : 1, /* don't count user */ | |
177 | exclude_kernel : 1, /* ditto kernel */ | |
178 | exclude_hv : 1, /* ditto hypervisor */ | |
2743a5b0 | 179 | exclude_idle : 1, /* don't count when idle */ |
0a4a9391 | 180 | mmap : 1, /* include mmap data */ |
8d1b2d93 | 181 | comm : 1, /* include comm data */ |
60db5e09 | 182 | freq : 1, /* use freq, not period */ |
bfbd3381 | 183 | inherit_stat : 1, /* per task counts */ |
57e7986e | 184 | enable_on_exec : 1, /* next exec enables */ |
9f498cc5 | 185 | task : 1, /* trace fork/exit */ |
0475f9ea | 186 | |
9f498cc5 | 187 | __reserved_1 : 50; |
2743a5b0 | 188 | |
c457810a | 189 | __u32 wakeup_events; /* wakeup every n events */ |
974802ea | 190 | __u32 __reserved_2; |
9f66a381 | 191 | |
974802ea | 192 | __u64 __reserved_3; |
eab656ae TG |
193 | }; |
194 | ||
d859e29f PM |
195 | /* |
196 | * Ioctls that can be done on a perf counter fd: | |
197 | */ | |
08247e31 PZ |
198 | #define PERF_COUNTER_IOC_ENABLE _IO ('$', 0) |
199 | #define PERF_COUNTER_IOC_DISABLE _IO ('$', 1) | |
200 | #define PERF_COUNTER_IOC_REFRESH _IO ('$', 2) | |
201 | #define PERF_COUNTER_IOC_RESET _IO ('$', 3) | |
202 | #define PERF_COUNTER_IOC_PERIOD _IOW('$', 4, u64) | |
3df5edad PZ |
203 | |
204 | enum perf_counter_ioc_flags { | |
205 | PERF_IOC_FLAG_GROUP = 1U << 0, | |
206 | }; | |
d859e29f | 207 | |
37d81828 PM |
208 | /* |
209 | * Structure of the page that can be mapped via mmap | |
210 | */ | |
211 | struct perf_counter_mmap_page { | |
212 | __u32 version; /* version number of this structure */ | |
213 | __u32 compat_version; /* lowest version this is compat with */ | |
38ff667b PZ |
214 | |
215 | /* | |
216 | * Bits needed to read the hw counters in user-space. | |
217 | * | |
92f22a38 PZ |
218 | * u32 seq; |
219 | * s64 count; | |
38ff667b | 220 | * |
a2e87d06 PZ |
221 | * do { |
222 | * seq = pc->lock; | |
38ff667b | 223 | * |
a2e87d06 PZ |
224 | * barrier() |
225 | * if (pc->index) { | |
226 | * count = pmc_read(pc->index - 1); | |
227 | * count += pc->offset; | |
228 | * } else | |
229 | * goto regular_read; | |
38ff667b | 230 | * |
a2e87d06 PZ |
231 | * barrier(); |
232 | * } while (pc->lock != seq); | |
38ff667b | 233 | * |
92f22a38 PZ |
234 | * NOTE: for obvious reason this only works on self-monitoring |
235 | * processes. | |
38ff667b | 236 | */ |
37d81828 PM |
237 | __u32 lock; /* seqlock for synchronization */ |
238 | __u32 index; /* hardware counter identifier */ | |
239 | __s64 offset; /* add to hardware counter value */ | |
7f8b4e4e PZ |
240 | __u64 time_enabled; /* time counter active */ |
241 | __u64 time_running; /* time counter on cpu */ | |
7b732a75 | 242 | |
41f95331 PZ |
243 | /* |
244 | * Hole for extension of the self monitor capabilities | |
245 | */ | |
246 | ||
7f8b4e4e | 247 | __u64 __reserved[123]; /* align to 1k */ |
41f95331 | 248 | |
38ff667b PZ |
249 | /* |
250 | * Control data for the mmap() data buffer. | |
251 | * | |
43a21ea8 PZ |
252 | * User-space reading the @data_head value should issue an rmb(), on |
253 | * SMP capable platforms, after reading this value -- see | |
254 | * perf_counter_wakeup(). | |
255 | * | |
256 | * When the mapping is PROT_WRITE the @data_tail value should be | |
257 | * written by userspace to reflect the last read data. In this case | |
258 | * the kernel will not over-write unread data. | |
38ff667b | 259 | */ |
8e3747c1 | 260 | __u64 data_head; /* head in the data section */ |
43a21ea8 | 261 | __u64 data_tail; /* user-space written tail */ |
37d81828 PM |
262 | }; |
263 | ||
a308444c IM |
264 | #define PERF_EVENT_MISC_CPUMODE_MASK (3 << 0) |
265 | #define PERF_EVENT_MISC_CPUMODE_UNKNOWN (0 << 0) | |
266 | #define PERF_EVENT_MISC_KERNEL (1 << 0) | |
267 | #define PERF_EVENT_MISC_USER (2 << 0) | |
268 | #define PERF_EVENT_MISC_HYPERVISOR (3 << 0) | |
6fab0192 | 269 | |
5c148194 PZ |
270 | struct perf_event_header { |
271 | __u32 type; | |
6fab0192 PZ |
272 | __u16 misc; |
273 | __u16 size; | |
5c148194 PZ |
274 | }; |
275 | ||
276 | enum perf_event_type { | |
5ed00415 | 277 | |
0c593b34 PZ |
278 | /* |
279 | * The MMAP events record the PROT_EXEC mappings so that we can | |
280 | * correlate userspace IPs to code. They have the following structure: | |
281 | * | |
282 | * struct { | |
0127c3ea | 283 | * struct perf_event_header header; |
0c593b34 | 284 | * |
0127c3ea IM |
285 | * u32 pid, tid; |
286 | * u64 addr; | |
287 | * u64 len; | |
288 | * u64 pgoff; | |
289 | * char filename[]; | |
0c593b34 PZ |
290 | * }; |
291 | */ | |
8a057d84 | 292 | PERF_EVENT_MMAP = 1, |
0a4a9391 | 293 | |
43a21ea8 PZ |
294 | /* |
295 | * struct { | |
296 | * struct perf_event_header header; | |
297 | * u64 id; | |
298 | * u64 lost; | |
299 | * }; | |
300 | */ | |
301 | PERF_EVENT_LOST = 2, | |
302 | ||
8d1b2d93 PZ |
303 | /* |
304 | * struct { | |
0127c3ea | 305 | * struct perf_event_header header; |
8d1b2d93 | 306 | * |
0127c3ea IM |
307 | * u32 pid, tid; |
308 | * char comm[]; | |
8d1b2d93 PZ |
309 | * }; |
310 | */ | |
311 | PERF_EVENT_COMM = 3, | |
312 | ||
9f498cc5 PZ |
313 | /* |
314 | * struct { | |
315 | * struct perf_event_header header; | |
316 | * u32 pid, ppid; | |
317 | * u32 tid, ptid; | |
318 | * }; | |
319 | */ | |
320 | PERF_EVENT_EXIT = 4, | |
321 | ||
26b119bc PZ |
322 | /* |
323 | * struct { | |
0127c3ea IM |
324 | * struct perf_event_header header; |
325 | * u64 time; | |
689802b2 | 326 | * u64 id; |
7f453c24 | 327 | * u64 stream_id; |
a78ac325 PZ |
328 | * }; |
329 | */ | |
330 | PERF_EVENT_THROTTLE = 5, | |
331 | PERF_EVENT_UNTHROTTLE = 6, | |
332 | ||
60313ebe PZ |
333 | /* |
334 | * struct { | |
a21ca2ca IM |
335 | * struct perf_event_header header; |
336 | * u32 pid, ppid; | |
9f498cc5 | 337 | * u32 tid, ptid; |
60313ebe PZ |
338 | * }; |
339 | */ | |
340 | PERF_EVENT_FORK = 7, | |
341 | ||
38b200d6 PZ |
342 | /* |
343 | * struct { | |
344 | * struct perf_event_header header; | |
345 | * u32 pid, tid; | |
346 | * u64 value; | |
347 | * { u64 time_enabled; } && PERF_FORMAT_ENABLED | |
348 | * { u64 time_running; } && PERF_FORMAT_RUNNING | |
349 | * { u64 parent_id; } && PERF_FORMAT_ID | |
350 | * }; | |
351 | */ | |
352 | PERF_EVENT_READ = 8, | |
353 | ||
8a057d84 | 354 | /* |
0c593b34 | 355 | * struct { |
0127c3ea | 356 | * struct perf_event_header header; |
0c593b34 | 357 | * |
43a21ea8 PZ |
358 | * { u64 ip; } && PERF_SAMPLE_IP |
359 | * { u32 pid, tid; } && PERF_SAMPLE_TID | |
360 | * { u64 time; } && PERF_SAMPLE_TIME | |
361 | * { u64 addr; } && PERF_SAMPLE_ADDR | |
e6e18ec7 | 362 | * { u64 id; } && PERF_SAMPLE_ID |
7f453c24 | 363 | * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID |
43a21ea8 | 364 | * { u32 cpu, res; } && PERF_SAMPLE_CPU |
e6e18ec7 | 365 | * { u64 period; } && PERF_SAMPLE_PERIOD |
0c593b34 | 366 | * |
0127c3ea | 367 | * { u64 nr; |
43a21ea8 | 368 | * { u64 id, val; } cnt[nr]; } && PERF_SAMPLE_GROUP |
0c593b34 | 369 | * |
f9188e02 | 370 | * { u64 nr, |
43a21ea8 | 371 | * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN |
a044560c PZ |
372 | * { u32 size; |
373 | * char data[size];}&& PERF_SAMPLE_RAW | |
0c593b34 | 374 | * }; |
8a057d84 | 375 | */ |
e6e18ec7 PZ |
376 | PERF_EVENT_SAMPLE = 9, |
377 | ||
378 | PERF_EVENT_MAX, /* non-ABI */ | |
5c148194 PZ |
379 | }; |
380 | ||
f9188e02 PZ |
381 | enum perf_callchain_context { |
382 | PERF_CONTEXT_HV = (__u64)-32, | |
383 | PERF_CONTEXT_KERNEL = (__u64)-128, | |
384 | PERF_CONTEXT_USER = (__u64)-512, | |
7522060c | 385 | |
f9188e02 PZ |
386 | PERF_CONTEXT_GUEST = (__u64)-2048, |
387 | PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, | |
388 | PERF_CONTEXT_GUEST_USER = (__u64)-2560, | |
389 | ||
390 | PERF_CONTEXT_MAX = (__u64)-4095, | |
7522060c IM |
391 | }; |
392 | ||
f3dfd265 | 393 | #ifdef __KERNEL__ |
9f66a381 | 394 | /* |
f3dfd265 | 395 | * Kernel-internal data types and definitions: |
9f66a381 IM |
396 | */ |
397 | ||
f3dfd265 PM |
398 | #ifdef CONFIG_PERF_COUNTERS |
399 | # include <asm/perf_counter.h> | |
400 | #endif | |
401 | ||
402 | #include <linux/list.h> | |
403 | #include <linux/mutex.h> | |
404 | #include <linux/rculist.h> | |
405 | #include <linux/rcupdate.h> | |
406 | #include <linux/spinlock.h> | |
d6d020e9 | 407 | #include <linux/hrtimer.h> |
3c446b3d | 408 | #include <linux/fs.h> |
709e50cf | 409 | #include <linux/pid_namespace.h> |
f3dfd265 PM |
410 | #include <asm/atomic.h> |
411 | ||
f9188e02 PZ |
412 | #define PERF_MAX_STACK_DEPTH 255 |
413 | ||
414 | struct perf_callchain_entry { | |
415 | __u64 nr; | |
416 | __u64 ip[PERF_MAX_STACK_DEPTH]; | |
417 | }; | |
418 | ||
3a43ce68 FW |
419 | struct perf_raw_record { |
420 | u32 size; | |
421 | void *data; | |
f413cdb8 FW |
422 | }; |
423 | ||
f3dfd265 PM |
424 | struct task_struct; |
425 | ||
0793a61d | 426 | /** |
9f66a381 | 427 | * struct hw_perf_counter - performance counter hardware details: |
0793a61d TG |
428 | */ |
429 | struct hw_perf_counter { | |
ee06094f | 430 | #ifdef CONFIG_PERF_COUNTERS |
d6d020e9 PZ |
431 | union { |
432 | struct { /* hardware */ | |
a308444c IM |
433 | u64 config; |
434 | unsigned long config_base; | |
435 | unsigned long counter_base; | |
436 | int idx; | |
d6d020e9 PZ |
437 | }; |
438 | union { /* software */ | |
a308444c IM |
439 | atomic64_t count; |
440 | struct hrtimer hrtimer; | |
d6d020e9 PZ |
441 | }; |
442 | }; | |
ee06094f | 443 | atomic64_t prev_count; |
b23f3325 | 444 | u64 sample_period; |
9e350de3 | 445 | u64 last_period; |
ee06094f | 446 | atomic64_t period_left; |
60db5e09 | 447 | u64 interrupts; |
6a24ed6c PZ |
448 | |
449 | u64 freq_count; | |
450 | u64 freq_interrupts; | |
bd2b5b12 | 451 | u64 freq_stamp; |
ee06094f | 452 | #endif |
0793a61d TG |
453 | }; |
454 | ||
621a01ea IM |
455 | struct perf_counter; |
456 | ||
457 | /** | |
4aeb0b42 | 458 | * struct pmu - generic performance monitoring unit |
621a01ea | 459 | */ |
4aeb0b42 | 460 | struct pmu { |
95cdd2e7 | 461 | int (*enable) (struct perf_counter *counter); |
7671581f IM |
462 | void (*disable) (struct perf_counter *counter); |
463 | void (*read) (struct perf_counter *counter); | |
a78ac325 | 464 | void (*unthrottle) (struct perf_counter *counter); |
621a01ea IM |
465 | }; |
466 | ||
6a930700 IM |
467 | /** |
468 | * enum perf_counter_active_state - the states of a counter | |
469 | */ | |
470 | enum perf_counter_active_state { | |
3b6f9e5c | 471 | PERF_COUNTER_STATE_ERROR = -2, |
6a930700 IM |
472 | PERF_COUNTER_STATE_OFF = -1, |
473 | PERF_COUNTER_STATE_INACTIVE = 0, | |
474 | PERF_COUNTER_STATE_ACTIVE = 1, | |
475 | }; | |
476 | ||
9b51f66d IM |
477 | struct file; |
478 | ||
7b732a75 PZ |
479 | struct perf_mmap_data { |
480 | struct rcu_head rcu_head; | |
8740f941 | 481 | int nr_pages; /* nr of data pages */ |
43a21ea8 | 482 | int writable; /* are we writable */ |
c5078f78 | 483 | int nr_locked; /* nr pages mlocked */ |
8740f941 | 484 | |
c33a0bc4 | 485 | atomic_t poll; /* POLL_ for wakeups */ |
8740f941 PZ |
486 | atomic_t events; /* event limit */ |
487 | ||
8e3747c1 PZ |
488 | atomic_long_t head; /* write position */ |
489 | atomic_long_t done_head; /* completed head */ | |
490 | ||
c33a0bc4 | 491 | atomic_t lock; /* concurrent writes */ |
c66de4a5 | 492 | atomic_t wakeup; /* needs a wakeup */ |
43a21ea8 | 493 | atomic_t lost; /* nr records lost */ |
c66de4a5 | 494 | |
7b732a75 | 495 | struct perf_counter_mmap_page *user_page; |
0127c3ea | 496 | void *data_pages[0]; |
7b732a75 PZ |
497 | }; |
498 | ||
671dec5d PZ |
499 | struct perf_pending_entry { |
500 | struct perf_pending_entry *next; | |
501 | void (*func)(struct perf_pending_entry *); | |
925d519a PZ |
502 | }; |
503 | ||
0793a61d TG |
504 | /** |
505 | * struct perf_counter - performance counter kernel representation: | |
506 | */ | |
507 | struct perf_counter { | |
ee06094f | 508 | #ifdef CONFIG_PERF_COUNTERS |
04289bb9 | 509 | struct list_head list_entry; |
592903cd | 510 | struct list_head event_entry; |
04289bb9 | 511 | struct list_head sibling_list; |
0127c3ea | 512 | int nr_siblings; |
04289bb9 | 513 | struct perf_counter *group_leader; |
4aeb0b42 | 514 | const struct pmu *pmu; |
04289bb9 | 515 | |
6a930700 | 516 | enum perf_counter_active_state state; |
0793a61d | 517 | atomic64_t count; |
ee06094f | 518 | |
53cfbf59 PM |
519 | /* |
520 | * These are the total time in nanoseconds that the counter | |
521 | * has been enabled (i.e. eligible to run, and the task has | |
522 | * been scheduled in, if this is a per-task counter) | |
523 | * and running (scheduled onto the CPU), respectively. | |
524 | * | |
525 | * They are computed from tstamp_enabled, tstamp_running and | |
526 | * tstamp_stopped when the counter is in INACTIVE or ACTIVE state. | |
527 | */ | |
528 | u64 total_time_enabled; | |
529 | u64 total_time_running; | |
530 | ||
531 | /* | |
532 | * These are timestamps used for computing total_time_enabled | |
533 | * and total_time_running when the counter is in INACTIVE or | |
534 | * ACTIVE state, measured in nanoseconds from an arbitrary point | |
535 | * in time. | |
536 | * tstamp_enabled: the notional time when the counter was enabled | |
537 | * tstamp_running: the notional time when the counter was scheduled on | |
538 | * tstamp_stopped: in INACTIVE state, the notional time when the | |
539 | * counter was scheduled off. | |
540 | */ | |
541 | u64 tstamp_enabled; | |
542 | u64 tstamp_running; | |
543 | u64 tstamp_stopped; | |
544 | ||
0d48696f | 545 | struct perf_counter_attr attr; |
0793a61d TG |
546 | struct hw_perf_counter hw; |
547 | ||
548 | struct perf_counter_context *ctx; | |
9b51f66d | 549 | struct file *filp; |
0793a61d | 550 | |
53cfbf59 PM |
551 | /* |
552 | * These accumulate total time (in nanoseconds) that children | |
553 | * counters have been enabled and running, respectively. | |
554 | */ | |
555 | atomic64_t child_total_time_enabled; | |
556 | atomic64_t child_total_time_running; | |
557 | ||
0793a61d | 558 | /* |
d859e29f | 559 | * Protect attach/detach and child_list: |
0793a61d | 560 | */ |
fccc714b PZ |
561 | struct mutex child_mutex; |
562 | struct list_head child_list; | |
563 | struct perf_counter *parent; | |
0793a61d TG |
564 | |
565 | int oncpu; | |
566 | int cpu; | |
567 | ||
082ff5a2 PZ |
568 | struct list_head owner_entry; |
569 | struct task_struct *owner; | |
570 | ||
7b732a75 PZ |
571 | /* mmap bits */ |
572 | struct mutex mmap_mutex; | |
573 | atomic_t mmap_count; | |
574 | struct perf_mmap_data *data; | |
37d81828 | 575 | |
7b732a75 | 576 | /* poll related */ |
0793a61d | 577 | wait_queue_head_t waitq; |
3c446b3d | 578 | struct fasync_struct *fasync; |
79f14641 PZ |
579 | |
580 | /* delayed work for NMIs and such */ | |
581 | int pending_wakeup; | |
4c9e2542 | 582 | int pending_kill; |
79f14641 | 583 | int pending_disable; |
671dec5d | 584 | struct perf_pending_entry pending; |
592903cd | 585 | |
79f14641 PZ |
586 | atomic_t event_limit; |
587 | ||
e077df4f | 588 | void (*destroy)(struct perf_counter *); |
592903cd | 589 | struct rcu_head rcu_head; |
709e50cf PZ |
590 | |
591 | struct pid_namespace *ns; | |
8e5799b1 | 592 | u64 id; |
ee06094f | 593 | #endif |
0793a61d TG |
594 | }; |
595 | ||
596 | /** | |
597 | * struct perf_counter_context - counter context structure | |
598 | * | |
599 | * Used as a container for task counters and CPU counters as well: | |
600 | */ | |
601 | struct perf_counter_context { | |
0793a61d | 602 | /* |
d859e29f PM |
603 | * Protect the states of the counters in the list, |
604 | * nr_active, and the list: | |
0793a61d | 605 | */ |
a308444c | 606 | spinlock_t lock; |
d859e29f PM |
607 | /* |
608 | * Protect the list of counters. Locking either mutex or lock | |
609 | * is sufficient to ensure the list doesn't change; to change | |
610 | * the list you need to lock both the mutex and the spinlock. | |
611 | */ | |
a308444c | 612 | struct mutex mutex; |
04289bb9 | 613 | |
a308444c IM |
614 | struct list_head counter_list; |
615 | struct list_head event_list; | |
616 | int nr_counters; | |
617 | int nr_active; | |
618 | int is_active; | |
bfbd3381 | 619 | int nr_stat; |
a308444c IM |
620 | atomic_t refcount; |
621 | struct task_struct *task; | |
53cfbf59 PM |
622 | |
623 | /* | |
4af4998b | 624 | * Context clock, runs when context enabled. |
53cfbf59 | 625 | */ |
a308444c IM |
626 | u64 time; |
627 | u64 timestamp; | |
564c2b21 PM |
628 | |
629 | /* | |
630 | * These fields let us detect when two contexts have both | |
631 | * been cloned (inherited) from a common ancestor. | |
632 | */ | |
a308444c IM |
633 | struct perf_counter_context *parent_ctx; |
634 | u64 parent_gen; | |
635 | u64 generation; | |
636 | int pin_count; | |
637 | struct rcu_head rcu_head; | |
0793a61d TG |
638 | }; |
639 | ||
640 | /** | |
641 | * struct perf_counter_cpu_context - per cpu counter context structure | |
642 | */ | |
643 | struct perf_cpu_context { | |
644 | struct perf_counter_context ctx; | |
645 | struct perf_counter_context *task_ctx; | |
646 | int active_oncpu; | |
647 | int max_pertask; | |
3b6f9e5c | 648 | int exclusive; |
96f6d444 PZ |
649 | |
650 | /* | |
651 | * Recursion avoidance: | |
652 | * | |
653 | * task, softirq, irq, nmi context | |
654 | */ | |
22a4f650 | 655 | int recursion[4]; |
0793a61d TG |
656 | }; |
657 | ||
829b42dd RR |
658 | #ifdef CONFIG_PERF_COUNTERS |
659 | ||
0793a61d TG |
660 | /* |
661 | * Set by architecture code: | |
662 | */ | |
663 | extern int perf_max_counters; | |
664 | ||
4aeb0b42 | 665 | extern const struct pmu *hw_perf_counter_init(struct perf_counter *counter); |
621a01ea | 666 | |
0793a61d | 667 | extern void perf_counter_task_sched_in(struct task_struct *task, int cpu); |
564c2b21 PM |
668 | extern void perf_counter_task_sched_out(struct task_struct *task, |
669 | struct task_struct *next, int cpu); | |
0793a61d | 670 | extern void perf_counter_task_tick(struct task_struct *task, int cpu); |
6ab423e0 | 671 | extern int perf_counter_init_task(struct task_struct *child); |
9b51f66d | 672 | extern void perf_counter_exit_task(struct task_struct *child); |
bbbee908 | 673 | extern void perf_counter_free_task(struct task_struct *task); |
9974458e | 674 | extern void set_perf_counter_pending(void); |
925d519a | 675 | extern void perf_counter_do_pending(void); |
0793a61d | 676 | extern void perf_counter_print_debug(void); |
9e35ad38 PZ |
677 | extern void __perf_disable(void); |
678 | extern bool __perf_enable(void); | |
679 | extern void perf_disable(void); | |
680 | extern void perf_enable(void); | |
1d1c7ddb IM |
681 | extern int perf_counter_task_disable(void); |
682 | extern int perf_counter_task_enable(void); | |
3cbed429 PM |
683 | extern int hw_perf_group_sched_in(struct perf_counter *group_leader, |
684 | struct perf_cpu_context *cpuctx, | |
685 | struct perf_counter_context *ctx, int cpu); | |
37d81828 | 686 | extern void perf_counter_update_userpage(struct perf_counter *counter); |
5c92d124 | 687 | |
df1a132b | 688 | struct perf_sample_data { |
a308444c IM |
689 | struct pt_regs *regs; |
690 | u64 addr; | |
691 | u64 period; | |
3a43ce68 | 692 | struct perf_raw_record *raw; |
df1a132b PZ |
693 | }; |
694 | ||
695 | extern int perf_counter_overflow(struct perf_counter *counter, int nmi, | |
696 | struct perf_sample_data *data); | |
697 | ||
3b6f9e5c PM |
698 | /* |
699 | * Return 1 for a software counter, 0 for a hardware counter | |
700 | */ | |
701 | static inline int is_software_counter(struct perf_counter *counter) | |
702 | { | |
a21ca2ca | 703 | return (counter->attr.type != PERF_TYPE_RAW) && |
f1a3c979 PZ |
704 | (counter->attr.type != PERF_TYPE_HARDWARE) && |
705 | (counter->attr.type != PERF_TYPE_HW_CACHE); | |
3b6f9e5c PM |
706 | } |
707 | ||
f29ac756 PZ |
708 | extern atomic_t perf_swcounter_enabled[PERF_COUNT_SW_MAX]; |
709 | ||
710 | extern void __perf_swcounter_event(u32, u64, int, struct pt_regs *, u64); | |
711 | ||
712 | static inline void | |
713 | perf_swcounter_event(u32 event, u64 nr, int nmi, struct pt_regs *regs, u64 addr) | |
714 | { | |
715 | if (atomic_read(&perf_swcounter_enabled[event])) | |
716 | __perf_swcounter_event(event, nr, nmi, regs, addr); | |
717 | } | |
15dbf27c | 718 | |
089dd79d PZ |
719 | extern void __perf_counter_mmap(struct vm_area_struct *vma); |
720 | ||
721 | static inline void perf_counter_mmap(struct vm_area_struct *vma) | |
722 | { | |
723 | if (vma->vm_flags & VM_EXEC) | |
724 | __perf_counter_mmap(vma); | |
725 | } | |
0a4a9391 | 726 | |
8d1b2d93 | 727 | extern void perf_counter_comm(struct task_struct *tsk); |
60313ebe | 728 | extern void perf_counter_fork(struct task_struct *tsk); |
8d1b2d93 | 729 | |
394ee076 PZ |
730 | extern struct perf_callchain_entry *perf_callchain(struct pt_regs *regs); |
731 | ||
0764771d | 732 | extern int sysctl_perf_counter_paranoid; |
c5078f78 | 733 | extern int sysctl_perf_counter_mlock; |
df58ab24 | 734 | extern int sysctl_perf_counter_sample_rate; |
1ccd1549 | 735 | |
0d905bca IM |
736 | extern void perf_counter_init(void); |
737 | ||
9d23a90a PM |
738 | #ifndef perf_misc_flags |
739 | #define perf_misc_flags(regs) (user_mode(regs) ? PERF_EVENT_MISC_USER : \ | |
740 | PERF_EVENT_MISC_KERNEL) | |
741 | #define perf_instruction_pointer(regs) instruction_pointer(regs) | |
742 | #endif | |
743 | ||
0793a61d TG |
744 | #else |
745 | static inline void | |
746 | perf_counter_task_sched_in(struct task_struct *task, int cpu) { } | |
747 | static inline void | |
910431c7 IM |
748 | perf_counter_task_sched_out(struct task_struct *task, |
749 | struct task_struct *next, int cpu) { } | |
0793a61d TG |
750 | static inline void |
751 | perf_counter_task_tick(struct task_struct *task, int cpu) { } | |
d3e78ee3 | 752 | static inline int perf_counter_init_task(struct task_struct *child) { return 0; } |
9b51f66d | 753 | static inline void perf_counter_exit_task(struct task_struct *child) { } |
bbbee908 | 754 | static inline void perf_counter_free_task(struct task_struct *task) { } |
925d519a | 755 | static inline void perf_counter_do_pending(void) { } |
0793a61d | 756 | static inline void perf_counter_print_debug(void) { } |
9e35ad38 PZ |
757 | static inline void perf_disable(void) { } |
758 | static inline void perf_enable(void) { } | |
1d1c7ddb IM |
759 | static inline int perf_counter_task_disable(void) { return -EINVAL; } |
760 | static inline int perf_counter_task_enable(void) { return -EINVAL; } | |
15dbf27c | 761 | |
925d519a | 762 | static inline void |
78f13e95 PZ |
763 | perf_swcounter_event(u32 event, u64 nr, int nmi, |
764 | struct pt_regs *regs, u64 addr) { } | |
0a4a9391 | 765 | |
089dd79d | 766 | static inline void perf_counter_mmap(struct vm_area_struct *vma) { } |
8d1b2d93 | 767 | static inline void perf_counter_comm(struct task_struct *tsk) { } |
60313ebe | 768 | static inline void perf_counter_fork(struct task_struct *tsk) { } |
0d905bca | 769 | static inline void perf_counter_init(void) { } |
0793a61d TG |
770 | #endif |
771 | ||
f3dfd265 | 772 | #endif /* __KERNEL__ */ |
0793a61d | 773 | #endif /* _LINUX_PERF_COUNTER_H */ |