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2744e8af LW |
1 | /* |
2 | * Interface the pinctrl subsystem | |
3 | * | |
4 | * Copyright (C) 2011 ST-Ericsson SA | |
5 | * Written on behalf of Linaro for ST-Ericsson | |
6 | * This interface is used in the core to keep track of pins. | |
7 | * | |
8 | * Author: Linus Walleij <linus.walleij@linaro.org> | |
9 | * | |
10 | * License terms: GNU General Public License (GPL) version 2 | |
11 | */ | |
12 | #ifndef __LINUX_PINCTRL_PINCTRL_H | |
13 | #define __LINUX_PINCTRL_PINCTRL_H | |
14 | ||
15 | #ifdef CONFIG_PINCTRL | |
16 | ||
17 | #include <linux/radix-tree.h> | |
2744e8af LW |
18 | #include <linux/list.h> |
19 | #include <linux/seq_file.h> | |
20 | ||
46919ae6 SW |
21 | #define PINCTRL_STATE_DEFAULT "default" |
22 | ||
2744e8af LW |
23 | struct pinctrl_dev; |
24 | struct pinmux_ops; | |
ae6b4d85 | 25 | struct pinconf_ops; |
2744e8af LW |
26 | struct gpio_chip; |
27 | ||
28 | /** | |
29 | * struct pinctrl_pin_desc - boards/machines provide information on their | |
30 | * pins, pads or other muxable units in this struct | |
31 | * @number: unique pin number from the global pin number space | |
32 | * @name: a name for this pin | |
33 | */ | |
34 | struct pinctrl_pin_desc { | |
35 | unsigned number; | |
36 | const char *name; | |
37 | }; | |
38 | ||
39 | /* Convenience macro to define a single named or anonymous pin descriptor */ | |
40 | #define PINCTRL_PIN(a, b) { .number = a, .name = b } | |
41 | #define PINCTRL_PIN_ANON(a) { .number = a } | |
42 | ||
43 | /** | |
44 | * struct pinctrl_gpio_range - each pin controller can provide subranges of | |
45 | * the GPIO number space to be handled by the controller | |
46 | * @node: list node for internal use | |
47 | * @name: a name for the chip in this range | |
48 | * @id: an ID number for the chip in this range | |
49 | * @base: base offset of the GPIO range | |
3c739ad0 | 50 | * @pin_base: base pin number of the GPIO range |
2744e8af LW |
51 | * @npins: number of pins in the GPIO range, including the base number |
52 | * @gc: an optional pointer to a gpio_chip | |
53 | */ | |
54 | struct pinctrl_gpio_range { | |
55 | struct list_head node; | |
56 | const char *name; | |
57 | unsigned int id; | |
58 | unsigned int base; | |
3c739ad0 | 59 | unsigned int pin_base; |
2744e8af LW |
60 | unsigned int npins; |
61 | struct gpio_chip *gc; | |
62 | }; | |
63 | ||
64 | /** | |
65 | * struct pinctrl_ops - global pin control operations, to be implemented by | |
66 | * pin controller drivers. | |
67 | * @list_groups: list the number of selectable named groups available | |
68 | * in this pinmux driver, the core will begin on 0 and call this | |
69 | * repeatedly as long as it returns >= 0 to enumerate the groups | |
70 | * @get_group_name: return the group name of the pin group | |
71 | * @get_group_pins: return an array of pins corresponding to a certain | |
72 | * group selector @pins, and the size of the array in @num_pins | |
73 | * @pin_dbg_show: optional debugfs display hook that will provide per-device | |
74 | * info for a certain pin in debugfs | |
75 | */ | |
76 | struct pinctrl_ops { | |
77 | int (*list_groups) (struct pinctrl_dev *pctldev, unsigned selector); | |
78 | const char *(*get_group_name) (struct pinctrl_dev *pctldev, | |
79 | unsigned selector); | |
80 | int (*get_group_pins) (struct pinctrl_dev *pctldev, | |
81 | unsigned selector, | |
a5818a8b SW |
82 | const unsigned **pins, |
83 | unsigned *num_pins); | |
2744e8af LW |
84 | void (*pin_dbg_show) (struct pinctrl_dev *pctldev, struct seq_file *s, |
85 | unsigned offset); | |
86 | }; | |
87 | ||
88 | /** | |
89 | * struct pinctrl_desc - pin controller descriptor, register this to pin | |
90 | * control subsystem | |
91 | * @name: name for the pin controller | |
92 | * @pins: an array of pin descriptors describing all the pins handled by | |
93 | * this pin controller | |
94 | * @npins: number of descriptors in the array, usually just ARRAY_SIZE() | |
95 | * of the pins field above | |
2744e8af LW |
96 | * @pctlops: pin control operation vtable, to support global concepts like |
97 | * grouping of pins, this is optional. | |
ae6b4d85 LW |
98 | * @pmxops: pinmux operations vtable, if you support pinmuxing in your driver |
99 | * @confops: pin config operations vtable, if you support pin configuration in | |
100 | * your driver | |
2744e8af LW |
101 | * @owner: module providing the pin controller, used for refcounting |
102 | */ | |
103 | struct pinctrl_desc { | |
104 | const char *name; | |
105 | struct pinctrl_pin_desc const *pins; | |
106 | unsigned int npins; | |
2744e8af LW |
107 | struct pinctrl_ops *pctlops; |
108 | struct pinmux_ops *pmxops; | |
ae6b4d85 | 109 | struct pinconf_ops *confops; |
2744e8af LW |
110 | struct module *owner; |
111 | }; | |
112 | ||
113 | /* External interface to pin controller */ | |
114 | extern struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc, | |
115 | struct device *dev, void *driver_data); | |
116 | extern void pinctrl_unregister(struct pinctrl_dev *pctldev); | |
117 | extern bool pin_is_valid(struct pinctrl_dev *pctldev, int pin); | |
118 | extern void pinctrl_add_gpio_range(struct pinctrl_dev *pctldev, | |
119 | struct pinctrl_gpio_range *range); | |
120 | extern void pinctrl_remove_gpio_range(struct pinctrl_dev *pctldev, | |
121 | struct pinctrl_gpio_range *range); | |
122 | extern const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev); | |
123 | extern void *pinctrl_dev_get_drvdata(struct pinctrl_dev *pctldev); | |
124 | #else | |
125 | ||
e0e20753 | 126 | struct pinctrl_dev; |
2744e8af | 127 | |
ae6b4d85 | 128 | /* Sufficiently stupid default functions when pinctrl is not in use */ |
2744e8af LW |
129 | static inline bool pin_is_valid(struct pinctrl_dev *pctldev, int pin) |
130 | { | |
131 | return pin >= 0; | |
132 | } | |
133 | ||
134 | #endif /* !CONFIG_PINCTRL */ | |
135 | ||
136 | #endif /* __LINUX_PINCTRL_PINCTRL_H */ |