projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 3bfb1d20 | 1 | /* |
| dd5720b3 | 2 | * Driver for the Synopsys DesignWare DMA Controller |
| 3bfb1d20 HS |
3 | * |
| 4 | * Copyright (C) 2007 Atmel Corporation | |
| aecb7b64 | 5 | * Copyright (C) 2010-2011 ST Microelectronics |
| 3bfb1d20 HS |
6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License version 2 as | |
| 9 | * published by the Free Software Foundation. | |
| 10 | */ | |
| 3d588f83 AS |
11 | #ifndef _PLATFORM_DATA_DMA_DW_H |
| 12 | #define _PLATFORM_DATA_DMA_DW_H | |
| 3bfb1d20 | 13 | |
| 3d588f83 | 14 | #include <linux/device.h> |
| 3bfb1d20 | 15 | |
| d8ded50f AS |
16 | #define DW_DMA_MAX_NR_MASTERS 4 |
| 17 | ||
| a9ddb575 VK |
18 | /** |
| 19 | * struct dw_dma_slave - Controller-specific information about a slave | |
| 20 | * | |
| cfd8fef3 | 21 | * @dma_dev: required DMA master device |
| 7e1e2f27 AS |
22 | * @src_id: src request line |
| 23 | * @dst_id: dst request line | |
| a9ddb575 VK |
24 | * @src_master: src master for transfers on allocated channel. |
| 25 | * @dst_master: dest master for transfers on allocated channel. | |
| 26 | */ | |
| 27 | struct dw_dma_slave { | |
| 28 | struct device *dma_dev; | |
| 7e1e2f27 AS |
29 | u8 src_id; |
| 30 | u8 dst_id; | |
| a9ddb575 VK |
31 | u8 src_master; |
| 32 | u8 dst_master; | |
| 33 | }; | |
| 34 | ||
| 3bfb1d20 HS |
35 | /** |
| 36 | * struct dw_dma_platform_data - Controller configuration parameters | |
| 37 | * @nr_channels: Number of channels supported by hardware (max 8) | |
| 95ea759e JI |
38 | * @is_private: The device channels should be marked as private and not for |
| 39 | * by the general purpose DMA channel allocator. | |
| df5c7386 | 40 | * @is_memcpy: The device channels do support memory-to-memory transfers. |
| 177d2bf5 VK |
41 | * @chan_allocation_order: Allocate channels starting from 0 or 7 |
| 42 | * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. | |
| 4a63a8b3 | 43 | * @block_size: Maximum block size supported by the controller |
| a0982004 AS |
44 | * @nr_masters: Number of AHB masters supported by the controller |
| 45 | * @data_width: Maximum data width supported by hardware per AHB master | |
| 46 | * (0 - 8bits, 1 - 16bits, ..., 5 - 256bits) | |
| 3bfb1d20 HS |
47 | */ |
| 48 | struct dw_dma_platform_data { | |
| 49 | unsigned int nr_channels; | |
| 95ea759e | 50 | bool is_private; |
| df5c7386 | 51 | bool is_memcpy; |
| b0c3130d VK |
52 | #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ |
| 53 | #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ | |
| 54 | unsigned char chan_allocation_order; | |
| 93317e8e VK |
55 | #define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ |
| 56 | #define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ | |
| 57 | unsigned char chan_priority; | |
| 4a63a8b3 | 58 | unsigned short block_size; |
| a0982004 | 59 | unsigned char nr_masters; |
| d8ded50f | 60 | unsigned char data_width[DW_DMA_MAX_NR_MASTERS]; |
| 3bfb1d20 HS |
61 | }; |
| 62 | ||
| 3d588f83 | 63 | #endif /* _PLATFORM_DATA_DMA_DW_H */ |