Commit | Line | Data |
---|---|---|
a4768d22 | 1 | /* |
3ad7a42d | 2 | * TI EDMA definitions |
a4768d22 | 3 | * |
3ad7a42d | 4 | * Copyright (C) 2006-2013 Texas Instruments. |
a4768d22 KH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
a4768d22 KH |
10 | */ |
11 | ||
12 | /* | |
13 | * This EDMA3 programming framework exposes two basic kinds of resource: | |
14 | * | |
15 | * Channel Triggers transfers, usually from a hardware event but | |
16 | * also manually or by "chaining" from DMA completions. | |
17 | * Each channel is coupled to a Parameter RAM (PaRAM) slot. | |
18 | * | |
19 | * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM | |
20 | * "set"), source and destination addresses, a link to a | |
21 | * next PaRAM slot (if any), options for the transfer, and | |
22 | * instructions for updating those addresses. There are | |
23 | * more than twice as many slots as event channels. | |
24 | * | |
25 | * Each PaRAM set describes a sequence of transfers, either for one large | |
26 | * buffer or for several discontiguous smaller buffers. An EDMA transfer | |
27 | * is driven only from a channel, which performs the transfers specified | |
28 | * in its PaRAM slot until there are no more transfers. When that last | |
29 | * transfer completes, the "link" field may be used to reload the channel's | |
30 | * PaRAM slot with a new transfer descriptor. | |
31 | * | |
32 | * The EDMA Channel Controller (CC) maps requests from channels into physical | |
33 | * Transfer Controller (TC) requests when the channel triggers (by hardware | |
34 | * or software events, or by chaining). The two physical DMA channels provided | |
35 | * by the TCs are thus shared by many logical channels. | |
36 | * | |
37 | * DaVinci hardware also has a "QDMA" mechanism which is not currently | |
38 | * supported through this interface. (DSP firmware uses it though.) | |
39 | */ | |
40 | ||
41 | #ifndef EDMA_H_ | |
42 | #define EDMA_H_ | |
43 | ||
a4768d22 KH |
44 | enum dma_event_q { |
45 | EVENTQ_0 = 0, | |
46 | EVENTQ_1 = 1, | |
10eef5a8 SP |
47 | EVENTQ_2 = 2, |
48 | EVENTQ_3 = 3, | |
a4768d22 KH |
49 | EVENTQ_DEFAULT = -1 |
50 | }; | |
51 | ||
60902a2c SR |
52 | #define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) |
53 | #define EDMA_CTLR(i) ((i) >> 16) | |
54 | #define EDMA_CHAN_SLOT(i) ((i) & 0xffff) | |
55 | ||
23e6723c PU |
56 | #define EDMA_FILTER_PARAM(ctlr, chan) ((int[]) { EDMA_CTLR_CHAN(ctlr, chan) }) |
57 | ||
90bd4e6d RS |
58 | struct edma_rsv_info { |
59 | ||
60 | const s16 (*rsv_chans)[2]; | |
61 | const s16 (*rsv_slots)[2]; | |
62 | }; | |
63 | ||
23e6723c PU |
64 | struct dma_slave_map; |
65 | ||
a4768d22 KH |
66 | /* platform_data for EDMA driver */ |
67 | struct edma_soc_info { | |
0b7580ba HS |
68 | /* |
69 | * Default queue is expected to be a low-priority queue. | |
70 | * This way, long transfers on the default queue started | |
71 | * by the codec engine will not cause audio defects. | |
72 | */ | |
a0f0202e | 73 | enum dma_event_q default_queue; |
a4768d22 | 74 | |
90bd4e6d RS |
75 | /* Resource reservation for other cores */ |
76 | struct edma_rsv_info *rsv; | |
77 | ||
1be5336b | 78 | /* List of channels allocated for memcpy, terminated with -1 */ |
ecb7dece | 79 | s32 *memcpy_channels; |
1be5336b | 80 | |
6cba4355 | 81 | s8 (*queue_priority_mapping)[2]; |
2646a0e5 | 82 | const s16 (*xbar_chans)[2]; |
23e6723c PU |
83 | |
84 | const struct dma_slave_map *slave_map; | |
85 | int slavecnt; | |
a4768d22 KH |
86 | }; |
87 | ||
88 | #endif |