Commit | Line | Data |
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9abd5f05 SH |
1 | /* |
2 | * Si5351A/B/C programmable clock generator platform_data. | |
3 | */ | |
4 | ||
5 | #ifndef __LINUX_PLATFORM_DATA_SI5351_H__ | |
6 | #define __LINUX_PLATFORM_DATA_SI5351_H__ | |
7 | ||
8 | struct clk; | |
9 | ||
9abd5f05 SH |
10 | /** |
11 | * enum si5351_pll_src - Si5351 pll clock source | |
12 | * @SI5351_PLL_SRC_DEFAULT: default, do not change eeprom config | |
13 | * @SI5351_PLL_SRC_XTAL: pll source clock is XTAL input | |
14 | * @SI5351_PLL_SRC_CLKIN: pll source clock is CLKIN input (Si5351C only) | |
15 | */ | |
16 | enum si5351_pll_src { | |
17 | SI5351_PLL_SRC_DEFAULT = 0, | |
18 | SI5351_PLL_SRC_XTAL = 1, | |
19 | SI5351_PLL_SRC_CLKIN = 2, | |
20 | }; | |
21 | ||
22 | /** | |
23 | * enum si5351_multisynth_src - Si5351 multisynth clock source | |
24 | * @SI5351_MULTISYNTH_SRC_DEFAULT: default, do not change eeprom config | |
25 | * @SI5351_MULTISYNTH_SRC_VCO0: multisynth source clock is VCO0 | |
26 | * @SI5351_MULTISYNTH_SRC_VCO1: multisynth source clock is VCO1/VXCO | |
27 | */ | |
28 | enum si5351_multisynth_src { | |
29 | SI5351_MULTISYNTH_SRC_DEFAULT = 0, | |
30 | SI5351_MULTISYNTH_SRC_VCO0 = 1, | |
31 | SI5351_MULTISYNTH_SRC_VCO1 = 2, | |
32 | }; | |
33 | ||
34 | /** | |
35 | * enum si5351_clkout_src - Si5351 clock output clock source | |
36 | * @SI5351_CLKOUT_SRC_DEFAULT: default, do not change eeprom config | |
37 | * @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N | |
38 | * @SI5351_CLKOUT_SRC_MSYNTH_0_4: clkout N source clock is multisynth 0 (N<4) | |
39 | * or 4 (N>=4) | |
40 | * @SI5351_CLKOUT_SRC_XTAL: clkout N source clock is XTAL | |
41 | * @SI5351_CLKOUT_SRC_CLKIN: clkout N source clock is CLKIN (Si5351C only) | |
42 | */ | |
43 | enum si5351_clkout_src { | |
44 | SI5351_CLKOUT_SRC_DEFAULT = 0, | |
45 | SI5351_CLKOUT_SRC_MSYNTH_N = 1, | |
46 | SI5351_CLKOUT_SRC_MSYNTH_0_4 = 2, | |
47 | SI5351_CLKOUT_SRC_XTAL = 3, | |
48 | SI5351_CLKOUT_SRC_CLKIN = 4, | |
49 | }; | |
50 | ||
51 | /** | |
52 | * enum si5351_drive_strength - Si5351 clock output drive strength | |
53 | * @SI5351_DRIVE_DEFAULT: default, do not change eeprom config | |
54 | * @SI5351_DRIVE_2MA: 2mA clock output drive strength | |
55 | * @SI5351_DRIVE_4MA: 4mA clock output drive strength | |
56 | * @SI5351_DRIVE_6MA: 6mA clock output drive strength | |
57 | * @SI5351_DRIVE_8MA: 8mA clock output drive strength | |
58 | */ | |
59 | enum si5351_drive_strength { | |
60 | SI5351_DRIVE_DEFAULT = 0, | |
61 | SI5351_DRIVE_2MA = 2, | |
62 | SI5351_DRIVE_4MA = 4, | |
63 | SI5351_DRIVE_6MA = 6, | |
64 | SI5351_DRIVE_8MA = 8, | |
65 | }; | |
66 | ||
1a0483d2 SH |
67 | /** |
68 | * enum si5351_disable_state - Si5351 clock output disable state | |
69 | * @SI5351_DISABLE_DEFAULT: default, do not change eeprom config | |
70 | * @SI5351_DISABLE_LOW: CLKx is set to a LOW state when disabled | |
71 | * @SI5351_DISABLE_HIGH: CLKx is set to a HIGH state when disabled | |
72 | * @SI5351_DISABLE_FLOATING: CLKx is set to a FLOATING state when | |
73 | * disabled | |
74 | * @SI5351_DISABLE_NEVER: CLKx is NEVER disabled | |
75 | */ | |
76 | enum si5351_disable_state { | |
77 | SI5351_DISABLE_DEFAULT = 0, | |
78 | SI5351_DISABLE_LOW, | |
79 | SI5351_DISABLE_HIGH, | |
80 | SI5351_DISABLE_FLOATING, | |
81 | SI5351_DISABLE_NEVER, | |
82 | }; | |
83 | ||
9abd5f05 SH |
84 | /** |
85 | * struct si5351_clkout_config - Si5351 clock output configuration | |
86 | * @clkout: clkout number | |
87 | * @multisynth_src: multisynth source clock | |
88 | * @clkout_src: clkout source clock | |
89 | * @pll_master: if true, clkout can also change pll rate | |
90 | * @drive: output drive strength | |
91 | * @rate: initial clkout rate, or default if 0 | |
92 | */ | |
93 | struct si5351_clkout_config { | |
94 | enum si5351_multisynth_src multisynth_src; | |
95 | enum si5351_clkout_src clkout_src; | |
96 | enum si5351_drive_strength drive; | |
1a0483d2 | 97 | enum si5351_disable_state disable_state; |
9abd5f05 SH |
98 | bool pll_master; |
99 | unsigned long rate; | |
100 | }; | |
101 | ||
102 | /** | |
103 | * struct si5351_platform_data - Platform data for the Si5351 clock driver | |
9abd5f05 SH |
104 | * @clk_xtal: xtal input clock |
105 | * @clk_clkin: clkin input clock | |
106 | * @pll_src: array of pll source clock setting | |
107 | * @clkout: array of clkout configuration | |
108 | */ | |
109 | struct si5351_platform_data { | |
9abd5f05 SH |
110 | struct clk *clk_xtal; |
111 | struct clk *clk_clkin; | |
112 | enum si5351_pll_src pll_src[2]; | |
113 | struct si5351_clkout_config clkout[8]; | |
114 | }; | |
115 | ||
116 | #endif |