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b5f3294f SH |
1 | |
2 | #ifndef __MACH_SPI_H_ | |
3 | #define __MACH_SPI_H_ | |
4 | ||
5 | /* | |
6 | * struct spi_imx_master - device.platform_data for SPI controller devices. | |
7 | * @chipselect: Array of chipselects for this master. Numbers >= 0 mean gpio | |
8 | * pins, numbers < 0 mean internal CSPI chipselects according | |
9 | * to MXC_SPI_CS(). Normally you want to use gpio based chip | |
10 | * selects as the CSPI module tries to be intelligent about | |
11 | * when to assert the chipselect: The CSPI module deasserts the | |
12 | * chipselect once it runs out of input data. The other problem | |
13 | * is that it is not possible to mix between high active and low | |
14 | * active chipselects on one single bus using the internal | |
15 | * chipselects. Unfortunately Freescale decided to put some | |
16 | * chipselects on dedicated pins which are not usable as gpios, | |
17 | * so we have to support the internal chipselects. | |
18 | * @num_chipselect: ARRAY_SIZE(chipselect) | |
19 | */ | |
20 | struct spi_imx_master { | |
21 | int *chipselect; | |
22 | int num_chipselect; | |
23 | }; | |
24 | ||
25 | #define MXC_SPI_CS(no) ((no) - 32) | |
26 | ||
27 | #endif /* __MACH_SPI_H_*/ |