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1da177e4 | 1 | /* |
8348c259 | 2 | * pxa2xx_ssp.h |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Russell King, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This driver supports the following PXA CPU/SSP ports:- | |
11 | * | |
12 | * PXA250 SSP | |
13 | * PXA255 SSP, NSSP | |
14 | * PXA26x SSP, NSSP, ASSP | |
15 | * PXA27x SSP1, SSP2, SSP3 | |
88286450 | 16 | * PXA3xx SSP1, SSP2, SSP3, SSP4 |
1da177e4 LT |
17 | */ |
18 | ||
8348c259 SAS |
19 | #ifndef __LINUX_SSP_H |
20 | #define __LINUX_SSP_H | |
88286450 | 21 | |
22 | #include <linux/list.h> | |
63bef547 | 23 | #include <linux/io.h> |
88286450 | 24 | |
83f28896 EM |
25 | /* |
26 | * SSP Serial Port Registers | |
27 | * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different. | |
28 | * PXA255, PXA26x and PXA27x have extra ports, registers and bits. | |
29 | */ | |
30 | ||
31 | #define SSCR0 (0x00) /* SSP Control Register 0 */ | |
32 | #define SSCR1 (0x04) /* SSP Control Register 1 */ | |
33 | #define SSSR (0x08) /* SSP Status Register */ | |
34 | #define SSITR (0x0C) /* SSP Interrupt Test Register */ | |
35 | #define SSDR (0x10) /* SSP Data Write/Data Read Register */ | |
36 | ||
37 | #define SSTO (0x28) /* SSP Time Out Register */ | |
38 | #define SSPSP (0x2C) /* SSP Programmable Serial Protocol */ | |
39 | #define SSTSA (0x30) /* SSP Tx Timeslot Active */ | |
40 | #define SSRSA (0x34) /* SSP Rx Timeslot Active */ | |
41 | #define SSTSS (0x38) /* SSP Timeslot Status */ | |
42 | #define SSACD (0x3C) /* SSP Audio Clock Divider */ | |
83f28896 | 43 | #define SSACDD (0x40) /* SSP Audio Clock Dither Divider */ |
83f28896 EM |
44 | |
45 | /* Common PXA2xx bits first */ | |
46 | #define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ | |
47 | #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ | |
48 | #define SSCR0_FRF (0x00000030) /* FRame Format (mask) */ | |
49 | #define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */ | |
50 | #define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */ | |
51 | #define SSCR0_National (0x2 << 4) /* National Microwire */ | |
52 | #define SSCR0_ECS (1 << 6) /* External clock select */ | |
53 | #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ | |
54 | #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */ | |
55 | ||
004690f0 | 56 | /* PXA27x, PXA3xx */ |
83f28896 EM |
57 | #define SSCR0_EDSS (1 << 20) /* Extended data size select */ |
58 | #define SSCR0_NCS (1 << 21) /* Network clock select */ | |
59 | #define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */ | |
60 | #define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ | |
61 | #define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ | |
62 | #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ | |
004690f0 | 63 | #define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */ |
83f28896 EM |
64 | #define SSCR0_ACS (1 << 30) /* Audio clock select */ |
65 | #define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ | |
83f28896 | 66 | |
83f28896 EM |
67 | |
68 | #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ | |
69 | #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ | |
70 | #define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ | |
71 | #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */ | |
72 | #define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ | |
73 | #define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ | |
83f28896 | 74 | |
2a8626a9 | 75 | #define SSSR_ALT_FRM_MASK 3 /* Masks the SFRM signal number */ |
83f28896 EM |
76 | #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ |
77 | #define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ | |
78 | #define SSSR_BSY (1 << 4) /* SSP Busy */ | |
79 | #define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ | |
80 | #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ | |
81 | #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ | |
d0777f2c SAS |
82 | |
83 | #ifdef CONFIG_ARCH_PXA | |
84 | #define RX_THRESH_DFLT 8 | |
85 | #define TX_THRESH_DFLT 8 | |
86 | ||
87 | #define SSSR_TFL_MASK (0xf << 8) /* Transmit FIFO Level mask */ | |
88 | #define SSSR_RFL_MASK (0xf << 12) /* Receive FIFO Level mask */ | |
89 | ||
90 | #define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */ | |
91 | #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */ | |
92 | #define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */ | |
93 | #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ | |
94 | ||
95 | #else | |
96 | ||
97 | #define RX_THRESH_DFLT 2 | |
98 | #define TX_THRESH_DFLT 2 | |
99 | ||
100 | #define SSSR_TFL_MASK (0x3 << 8) /* Transmit FIFO Level mask */ | |
101 | #define SSSR_RFL_MASK (0x3 << 12) /* Receive FIFO Level mask */ | |
102 | ||
103 | #define SSCR1_TFT (0x000000c0) /* Transmit FIFO Threshold (mask) */ | |
104 | #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */ | |
105 | #define SSCR1_RFT (0x00000c00) /* Receive FIFO Threshold (mask) */ | |
106 | #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */ | |
107 | #endif | |
83f28896 EM |
108 | |
109 | /* extra bits in PXA255, PXA26x and PXA27x SSP ports */ | |
110 | #define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */ | |
111 | #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */ | |
112 | #define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */ | |
113 | #define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */ | |
114 | #define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */ | |
115 | #define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */ | |
116 | #define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */ | |
117 | #define SSCR1_ECRB (1 << 26) /* Enable Clock request B */ | |
118 | #define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */ | |
119 | #define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */ | |
120 | #define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */ | |
121 | #define SSCR1_TRAIL (1 << 22) /* Trailing Byte */ | |
122 | #define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */ | |
123 | #define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */ | |
124 | #define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */ | |
125 | #define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */ | |
126 | #define SSCR1_IFS (1 << 16) /* Invert Frame Signal */ | |
127 | #define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */ | |
128 | #define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */ | |
129 | ||
130 | #define SSSR_BCE (1 << 23) /* Bit Count Error */ | |
131 | #define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */ | |
132 | #define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */ | |
133 | #define SSSR_EOC (1 << 20) /* End Of Chain */ | |
134 | #define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ | |
135 | #define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ | |
136 | ||
83f28896 | 137 | |
83f28896 | 138 | #define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */ |
004690f0 HZ |
139 | #define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */ |
140 | #define SSPSP_ETDS (1 << 3) /* End of Transfer data State */ | |
141 | #define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */ | |
142 | #define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */ | |
143 | #define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */ | |
144 | #define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ | |
145 | #define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ | |
146 | #define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ | |
147 | ||
148 | /* PXA3xx */ | |
149 | #define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */ | |
150 | #define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */ | |
151 | #define SSPSP_TIMING_MASK (0x7f8001f0) | |
83f28896 EM |
152 | |
153 | #define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */ | |
154 | #define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ | |
155 | #define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ | |
83f28896 | 156 | #define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */ |
83f28896 | 157 | |
88286450 | 158 | enum pxa_ssp_type { |
159 | SSP_UNDEFINED = 0, | |
160 | PXA25x_SSP, /* pxa 210, 250, 255, 26x */ | |
161 | PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */ | |
162 | PXA27x_SSP, | |
7e499228 | 163 | PXA168_SSP, |
2a8626a9 | 164 | CE4100_SSP, |
88286450 | 165 | }; |
166 | ||
167 | struct ssp_device { | |
168 | struct platform_device *pdev; | |
169 | struct list_head node; | |
170 | ||
171 | struct clk *clk; | |
172 | void __iomem *mmio_base; | |
173 | unsigned long phys_base; | |
174 | ||
175 | const char *label; | |
176 | int port_id; | |
177 | int type; | |
178 | int use_count; | |
179 | int irq; | |
180 | int drcmr_rx; | |
181 | int drcmr_tx; | |
182 | }; | |
1da177e4 | 183 | |
63bef547 | 184 | /** |
baffe169 | 185 | * pxa_ssp_write_reg - Write to a SSP register |
63bef547 MB |
186 | * |
187 | * @dev: SSP device to access | |
188 | * @reg: Register to write to | |
189 | * @val: Value to be written. | |
190 | */ | |
baffe169 | 191 | static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val) |
63bef547 MB |
192 | { |
193 | __raw_writel(val, dev->mmio_base + reg); | |
194 | } | |
195 | ||
196 | /** | |
baffe169 | 197 | * pxa_ssp_read_reg - Read from a SSP register |
63bef547 MB |
198 | * |
199 | * @dev: SSP device to access | |
200 | * @reg: Register to read from | |
201 | */ | |
baffe169 | 202 | static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg) |
63bef547 MB |
203 | { |
204 | return __raw_readl(dev->mmio_base + reg); | |
205 | } | |
206 | ||
baffe169 HZ |
207 | struct ssp_device *pxa_ssp_request(int port, const char *label); |
208 | void pxa_ssp_free(struct ssp_device *); | |
8348c259 | 209 | #endif |