[deliverable/linux.git] / include / linux / qed / eth_common.h

/* QLogic qed NIC Driver
 * Copyright (c) 2015 QLogic Corporation
 *
 * This software is available under the terms of the GNU General Public License
 * (GPL) Version 2, available from the file COPYING in the main directory of
 * this source tree.
 */

#ifndef __ETH_COMMON__
#define __ETH_COMMON__

/********************/
/* ETH FW CONSTANTS */
/********************/
#define ETH_CACHE_LINE_SIZE                 64

#define ETH_MAX_RAMROD_PER_CON                          8
#define ETH_TX_BD_PAGE_SIZE_BYTES                       4096
#define ETH_RX_BD_PAGE_SIZE_BYTES                       4096
#define ETH_RX_CQE_PAGE_SIZE_BYTES                      4096
#define ETH_RX_NUM_NEXT_PAGE_BDS                        2

#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT                          1
#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET                       18
#define ETH_TX_MAX_LSO_HDR_NBD                                          4
#define ETH_TX_MIN_BDS_PER_LSO_PKT                                      3
#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT       3
#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT            2
#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE          2
#define ETH_TX_MAX_NON_LSO_PKT_LEN                  (9700 - (4 + 12 + 8))
#define ETH_TX_MAX_LSO_HDR_BYTES                    510

#define ETH_NUM_STATISTIC_COUNTERS                      MAX_NUM_VPORTS

/* Maximum number of buffers, used for RX packet placement */
#define ETH_RX_MAX_BUFF_PER_PKT             5

/* num of MAC/VLAN filters */
#define ETH_NUM_MAC_FILTERS                                     512
#define ETH_NUM_VLAN_FILTERS                            512

/* approx. multicast constants */
#define ETH_MULTICAST_BIN_FROM_MAC_SEED     0
#define ETH_MULTICAST_MAC_BINS                          256
#define ETH_MULTICAST_MAC_BINS_IN_REGS          (ETH_MULTICAST_MAC_BINS / 32)

/*  ethernet vport update constants */
#define ETH_FILTER_RULES_COUNT                          10
#define ETH_RSS_IND_TABLE_ENTRIES_NUM           128
#define ETH_RSS_KEY_SIZE_REGS                       10
#define ETH_RSS_ENGINE_NUM_K2               207
#define ETH_RSS_ENGINE_NUM_BB               127

/* TPA constants */
#define ETH_TPA_MAX_AGGS_NUM              64
#define ETH_TPA_CQE_START_LEN_LIST_SIZE   ETH_RX_MAX_BUFF_PER_PKT
#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE    6
#define ETH_TPA_CQE_END_LEN_LIST_SIZE     4

/* Queue Zone sizes */
#define TSTORM_QZONE_SIZE    0
#define MSTORM_QZONE_SIZE    sizeof(struct mstorm_eth_queue_zone)
#define USTORM_QZONE_SIZE    sizeof(struct ustorm_eth_queue_zone)
#define XSTORM_QZONE_SIZE    0
#define YSTORM_QZONE_SIZE    sizeof(struct ystorm_eth_queue_zone)
#define PSTORM_QZONE_SIZE    0

/* Interrupt coalescing TimeSet */
struct coalescing_timeset {
	u8	timeset;
	u8	valid;
};

struct eth_tx_1st_bd_flags {
	u8 bitfields;
#define ETH_TX_1ST_BD_FLAGS_START_BD_MASK         0x1
#define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT        0
#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK  0x1
#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK          0x1
#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT         2
#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK          0x1
#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT         3
#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK   0x1
#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT  4
#define ETH_TX_1ST_BD_FLAGS_LSO_MASK              0x1
#define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT             5
#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK     0x1
#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT    6
#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK     0x1
#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT    7
};

/* The parsing information data fo rthe first tx bd of a given packet. */
struct eth_tx_data_1st_bd {
	__le16				vlan;
	u8				nbds;
	struct eth_tx_1st_bd_flags	bd_flags;
	__le16				bitfields;
#define ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_MASK  0x1
#define ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_SHIFT 0
#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK          0x1
#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT         1
#define ETH_TX_DATA_1ST_BD_FW_USE_ONLY_MASK        0x3FFF
#define ETH_TX_DATA_1ST_BD_FW_USE_ONLY_SHIFT       2
};

/* The parsing information data for the second tx bd of a given packet. */
struct eth_tx_data_2nd_bd {
	__le16	tunn_ip_size;
	__le16	bitfields1;
#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK  0xF
#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK       0x3
#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT      4
#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK            0x3
#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT           6
#define ETH_TX_DATA_2ND_BD_START_BD_MASK                  0x1
#define ETH_TX_DATA_2ND_BD_START_BD_SHIFT                 8
#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK                 0x3
#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT                9
#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK           0x1
#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT          11
#define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK                  0x1
#define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT                 12
#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK             0x1
#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT            13
#define ETH_TX_DATA_2ND_BD_L4_UDP_MASK                    0x1
#define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT                   14
#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK       0x1
#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT      15
	__le16 bitfields2;
#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK     0x1FFF
#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT    0
#define ETH_TX_DATA_2ND_BD_RESERVED0_MASK                 0x7
#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT                13
};

/* Regular ETH Rx FP CQE. */
struct eth_fast_path_rx_reg_cqe {
	u8	type;
	u8	bitfields;
#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK  0x7
#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
#define ETH_FAST_PATH_RX_REG_CQE_TC_MASK             0xF
#define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT            3
#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK      0x1
#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT     7
	__le16				pkt_len;
	struct parsing_and_err_flags	pars_flags;
	__le16				vlan_tag;
	__le32				rss_hash;
	__le16				len_on_first_bd;
	u8				placement_offset;
	struct tunnel_parsing_flags	tunnel_pars_flags;
	u8				bd_num;
	u8				reserved[7];
	u32				fw_debug;
	u8				reserved1[3];
	u8				flags;
#define ETH_FAST_PATH_RX_REG_CQE_VALID_MASK          0x1
#define ETH_FAST_PATH_RX_REG_CQE_VALID_SHIFT         0
#define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_MASK   0x1
#define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_SHIFT  1
#define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_MASK      0x3F
#define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_SHIFT     2
};

/* TPA-continue ETH Rx FP CQE. */
struct eth_fast_path_rx_tpa_cont_cqe {
	u8	type;
	u8	tpa_agg_index;
	__le16	len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
	u8	reserved[5];
	u8	reserved1;
	__le16	reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
};

/* TPA-end ETH Rx FP CQE. */
struct eth_fast_path_rx_tpa_end_cqe {
	u8	type;
	u8	tpa_agg_index;
	__le16	total_packet_len;
	u8	num_of_bds;
	u8	end_reason;
	__le16	num_of_coalesced_segs;
	__le32	ts_delta;
	__le16	len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE];
	u8	reserved1[3];
	u8	reserved2;
	__le16	reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE];
};

/* TPA-start ETH Rx FP CQE. */
struct eth_fast_path_rx_tpa_start_cqe {
	u8	type;
	u8	bitfields;
#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK  0x7
#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK             0xF
#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT            3
#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK      0x1
#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT     7
	__le16	seg_len;
	struct parsing_and_err_flags pars_flags;
	__le16	vlan_tag;
	__le32	rss_hash;
	__le16	len_on_first_bd;
	u8	placement_offset;
	struct tunnel_parsing_flags tunnel_pars_flags;
	u8	tpa_agg_index;
	u8	header_len;
	__le16	ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE];
	u32	fw_debug;
};

/* The L4 pseudo checksum mode for Ethernet */
enum eth_l4_pseudo_checksum_mode {
	ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH,
	ETH_L4_PSEUDO_CSUM_ZERO_LENGTH,
	MAX_ETH_L4_PSEUDO_CHECKSUM_MODE
};

struct eth_rx_bd {
	struct regpair addr;
};

/* regular ETH Rx SP CQE */
struct eth_slow_path_rx_cqe {
	u8	type;
	u8	ramrod_cmd_id;
	u8	error_flag;
	u8	reserved[25];
	__le16	echo;
	u8	reserved1;
	u8	flags;
/* for PMD mode - valid indication */
#define ETH_SLOW_PATH_RX_CQE_VALID_MASK         0x1
#define ETH_SLOW_PATH_RX_CQE_VALID_SHIFT        0
/* for PMD mode - valid toggle indication */
#define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_MASK  0x1
#define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_SHIFT 1
#define ETH_SLOW_PATH_RX_CQE_RESERVED2_MASK     0x3F
#define ETH_SLOW_PATH_RX_CQE_RESERVED2_SHIFT    2
};

/* union for all ETH Rx CQE types */
union eth_rx_cqe {
	struct eth_fast_path_rx_reg_cqe		fast_path_regular;
	struct eth_fast_path_rx_tpa_start_cqe	fast_path_tpa_start;
	struct eth_fast_path_rx_tpa_cont_cqe	fast_path_tpa_cont;
	struct eth_fast_path_rx_tpa_end_cqe	fast_path_tpa_end;
	struct eth_slow_path_rx_cqe		slow_path;
};

/* ETH Rx CQE type */
enum eth_rx_cqe_type {
	ETH_RX_CQE_TYPE_UNUSED,
	ETH_RX_CQE_TYPE_REGULAR,
	ETH_RX_CQE_TYPE_SLOW_PATH,
	ETH_RX_CQE_TYPE_TPA_START,
	ETH_RX_CQE_TYPE_TPA_CONT,
	ETH_RX_CQE_TYPE_TPA_END,
	MAX_ETH_RX_CQE_TYPE
};

/* ETH Rx producers data */
struct eth_rx_prod_data {
	__le16	bd_prod;
	__le16	cqe_prod;
	__le16	reserved;
	__le16	reserved1;
};

/* The first tx bd of a given packet */
struct eth_tx_1st_bd {
	struct regpair			addr;
	__le16				nbytes;
	struct eth_tx_data_1st_bd	data;
};

/* The second tx bd of a given packet */
struct eth_tx_2nd_bd {
	struct regpair			addr;
	__le16				nbytes;
	struct eth_tx_data_2nd_bd	data;
};

/* The parsing information data for the third tx bd of a given packet. */
struct eth_tx_data_3rd_bd {
	__le16	lso_mss;
	__le16	bitfields;
#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK  0xF
#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK         0xF
#define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT        4
#define ETH_TX_DATA_3RD_BD_START_BD_MASK        0x1
#define ETH_TX_DATA_3RD_BD_START_BD_SHIFT       8
#define ETH_TX_DATA_3RD_BD_RESERVED0_MASK       0x7F
#define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT      9
	u8	tunn_l4_hdr_start_offset_w;
	u8	tunn_hdr_size_w;
};

/* The third tx bd of a given packet */
struct eth_tx_3rd_bd {
	struct regpair			addr;
	__le16				nbytes;
	struct eth_tx_data_3rd_bd	data;
};

/* Complementary information for the regular tx bd of a given packet. */
struct eth_tx_data_bd {
	__le16	reserved0;
	__le16	bitfields;
#define ETH_TX_DATA_BD_RESERVED1_MASK  0xFF
#define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
#define ETH_TX_DATA_BD_START_BD_MASK   0x1
#define ETH_TX_DATA_BD_START_BD_SHIFT  8
#define ETH_TX_DATA_BD_RESERVED2_MASK  0x7F
#define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
	__le16 reserved3;
};

/* The common non-special TX BD ring element */
struct eth_tx_bd {
	struct regpair	addr;
	__le16		nbytes;
	struct eth_tx_data_bd	data;
};

union eth_tx_bd_types {
	struct eth_tx_1st_bd	first_bd;
	struct eth_tx_2nd_bd	second_bd;
	struct eth_tx_3rd_bd	third_bd;
	struct eth_tx_bd	reg_bd;
};

/* Mstorm Queue Zone */
struct mstorm_eth_queue_zone {
	struct eth_rx_prod_data rx_producers;
	__le32			reserved[2];
};

/* Ustorm Queue Zone */
struct ustorm_eth_queue_zone {
	struct coalescing_timeset	int_coalescing_timeset;
	__le16				reserved[3];
};

/* Ystorm Queue Zone */
struct ystorm_eth_queue_zone {
	struct coalescing_timeset	int_coalescing_timeset;
	__le16				reserved[3];
};

/* ETH doorbell data */
struct eth_db_data {
	u8 params;
#define ETH_DB_DATA_DEST_MASK         0x3
#define ETH_DB_DATA_DEST_SHIFT        0
#define ETH_DB_DATA_AGG_CMD_MASK      0x3
#define ETH_DB_DATA_AGG_CMD_SHIFT     2
#define ETH_DB_DATA_BYPASS_EN_MASK    0x1
#define ETH_DB_DATA_BYPASS_EN_SHIFT   4
#define ETH_DB_DATA_RESERVED_MASK     0x1
#define ETH_DB_DATA_RESERVED_SHIFT    5
#define ETH_DB_DATA_AGG_VAL_SEL_MASK  0x3
#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
	u8	agg_flags;
	__le16	bd_prod;
};

#endif /* __ETH_COMMON__ */
Commit	Line	Data
25c089d7 YM	1	/* QLogic qed NIC Driver
	2	* Copyright (c) 2015 QLogic Corporation
	3	*
	4	* This software is available under the terms of the GNU General Public License
	5	* (GPL) Version 2, available from the file COPYING in the main directory of
	6	* this source tree.
	7	*/
	8
	9	#ifndef __ETH_COMMON__
	10	#define __ETH_COMMON__
	11
	12	/********************/
	13	/* ETH FW CONSTANTS */
	14	/********************/
	15	#define ETH_CACHE_LINE_SIZE 64
	16
	17	#define ETH_MAX_RAMROD_PER_CON 8
	18	#define ETH_TX_BD_PAGE_SIZE_BYTES 4096
	19	#define ETH_RX_BD_PAGE_SIZE_BYTES 4096
25c089d7 YM	20	#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
25c089d7 YM	21	#define ETH_RX_NUM_NEXT_PAGE_BDS 2
25c089d7 YM	22
	23	#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
	24	#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
	25	#define ETH_TX_MAX_LSO_HDR_NBD 4
	26	#define ETH_TX_MIN_BDS_PER_LSO_PKT 3
	27	#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
	28	#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
	29	#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
	30	#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 12 + 8))
	31	#define ETH_TX_MAX_LSO_HDR_BYTES 510
	32
	33	#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
	34
fc48b7a6 YM	35	/* Maximum number of buffers, used for RX packet placement */
fc48b7a6 YM	36	#define ETH_RX_MAX_BUFF_PER_PKT 5
25c089d7 YM	37
	38	/* num of MAC/VLAN filters */
	39	#define ETH_NUM_MAC_FILTERS 512
	40	#define ETH_NUM_VLAN_FILTERS 512
	41
	42	/* approx. multicast constants */
	43	#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
	44	#define ETH_MULTICAST_MAC_BINS 256
	45	#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
	46
	47	/* ethernet vport update constants */
	48	#define ETH_FILTER_RULES_COUNT 10
	49	#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
	50	#define ETH_RSS_KEY_SIZE_REGS 10
	51	#define ETH_RSS_ENGINE_NUM_K2 207
	52	#define ETH_RSS_ENGINE_NUM_BB 127
	53
	54	/* TPA constants */
	55	#define ETH_TPA_MAX_AGGS_NUM 64
fc48b7a6 YM	56	#define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT
	57	#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
	58	#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
25c089d7 YM	59
	60	/* Queue Zone sizes */
	61	#define TSTORM_QZONE_SIZE 0
	62	#define MSTORM_QZONE_SIZE sizeof(struct mstorm_eth_queue_zone)
	63	#define USTORM_QZONE_SIZE sizeof(struct ustorm_eth_queue_zone)
	64	#define XSTORM_QZONE_SIZE 0
	65	#define YSTORM_QZONE_SIZE sizeof(struct ystorm_eth_queue_zone)
	66	#define PSTORM_QZONE_SIZE 0
	67
	68	/* Interrupt coalescing TimeSet */
	69	struct coalescing_timeset {
	70	u8 timeset;
	71	u8 valid;
	72	};
	73
	74	struct eth_tx_1st_bd_flags {
	75	u8 bitfields;
fc48b7a6 YM	76	#define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
fc48b7a6 YM	77	#define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0
25c089d7	78	#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
fc48b7a6	79	#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
25c089d7	80	#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
fc48b7a6	81	#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2
25c089d7	82	#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
fc48b7a6	83	#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3
25c089d7	84	#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
fc48b7a6	85	#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4
25c089d7	86	#define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
fc48b7a6	87	#define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5
25c089d7 YM	88	#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
	89	#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
	90	#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
	91	#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
	92	};
	93
	94	/* The parsing information data fo rthe first tx bd of a given packet. */
	95	struct eth_tx_data_1st_bd {
	96	__le16 vlan;
	97	u8 nbds;
	98	struct eth_tx_1st_bd_flags bd_flags;
fc48b7a6 YM	99	__le16 bitfields;
	100	#define ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_MASK 0x1
	101	#define ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_SHIFT 0
	102	#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
	103	#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
	104	#define ETH_TX_DATA_1ST_BD_FW_USE_ONLY_MASK 0x3FFF
	105	#define ETH_TX_DATA_1ST_BD_FW_USE_ONLY_SHIFT 2
25c089d7 YM	106	};
	107
	108	/* The parsing information data for the second tx bd of a given packet. */
	109	struct eth_tx_data_2nd_bd {
	110	__le16 tunn_ip_size;
fc48b7a6	111	__le16 bitfields1;
25c089d7 YM	112	#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
	113	#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
	114	#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
	115	#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
	116	#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
	117	#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
fc48b7a6 YM	118	#define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1
fc48b7a6 YM	119	#define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8
25c089d7	120	#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
fc48b7a6	121	#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9
25c089d7	122	#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
fc48b7a6	123	#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11
25c089d7	124	#define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
fc48b7a6	125	#define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12
25c089d7	126	#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
fc48b7a6	127	#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13
25c089d7	128	#define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
fc48b7a6	129	#define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14
25c089d7	130	#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
fc48b7a6 YM	131	#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15
	132	__le16 bitfields2;
	133	#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
	134	#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
	135	#define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
	136	#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
25c089d7 YM	137	};
	138
	139	/* Regular ETH Rx FP CQE. */
	140	struct eth_fast_path_rx_reg_cqe {
	141	u8 type;
	142	u8 bitfields;
	143	#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
	144	#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
	145	#define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
	146	#define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
	147	#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
	148	#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
	149	__le16 pkt_len;
	150	struct parsing_and_err_flags pars_flags;
	151	__le16 vlan_tag;
	152	__le32 rss_hash;
fc48b7a6	153	__le16 len_on_first_bd;
25c089d7	154	u8 placement_offset;
fc48b7a6 YM	155	struct tunnel_parsing_flags tunnel_pars_flags;
	156	u8 bd_num;
	157	u8 reserved[7];
	158	u32 fw_debug;
	159	u8 reserved1[3];
	160	u8 flags;
	161	#define ETH_FAST_PATH_RX_REG_CQE_VALID_MASK 0x1
	162	#define ETH_FAST_PATH_RX_REG_CQE_VALID_SHIFT 0
	163	#define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_MASK 0x1
	164	#define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_SHIFT 1
	165	#define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_MASK 0x3F
	166	#define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_SHIFT 2
	167	};
	168
	169	/* TPA-continue ETH Rx FP CQE. */
	170	struct eth_fast_path_rx_tpa_cont_cqe {
	171	u8 type;
	172	u8 tpa_agg_index;
	173	__le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
	174	u8 reserved[5];
	175	u8 reserved1;
	176	__le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
	177	};
	178
	179	/* TPA-end ETH Rx FP CQE. */
	180	struct eth_fast_path_rx_tpa_end_cqe {
	181	u8 type;
	182	u8 tpa_agg_index;
	183	__le16 total_packet_len;
	184	u8 num_of_bds;
	185	u8 end_reason;
	186	__le16 num_of_coalesced_segs;
	187	__le32 ts_delta;
	188	__le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE];
	189	u8 reserved1[3];
	190	u8 reserved2;
	191	__le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE];
	192	};
	193
	194	/* TPA-start ETH Rx FP CQE. */
	195	struct eth_fast_path_rx_tpa_start_cqe {
	196	u8 type;
	197	u8 bitfields;
	198	#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
	199	#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
	200	#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
	201	#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
	202	#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
	203	#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
	204	__le16 seg_len;
	205	struct parsing_and_err_flags pars_flags;
	206	__le16 vlan_tag;
	207	__le32 rss_hash;
	208	__le16 len_on_first_bd;
	209	u8 placement_offset;
	210	struct tunnel_parsing_flags tunnel_pars_flags;
	211	u8 tpa_agg_index;
	212	u8 header_len;
	213	__le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE];
	214	u32 fw_debug;
25c089d7 YM	215	};
	216
	217	/* The L4 pseudo checksum mode for Ethernet */
	218	enum eth_l4_pseudo_checksum_mode {
	219	ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH,
	220	ETH_L4_PSEUDO_CSUM_ZERO_LENGTH,
	221	MAX_ETH_L4_PSEUDO_CHECKSUM_MODE
	222	};
	223
	224	struct eth_rx_bd {
	225	struct regpair addr;
	226	};
	227
	228	/* regular ETH Rx SP CQE */
	229	struct eth_slow_path_rx_cqe {
	230	u8 type;
	231	u8 ramrod_cmd_id;
	232	u8 error_flag;
fc48b7a6	233	u8 reserved[25];
25c089d7	234	__le16 echo;
fc48b7a6 YM	235	u8 reserved1;
	236	u8 flags;
	237	/* for PMD mode - valid indication */
	238	#define ETH_SLOW_PATH_RX_CQE_VALID_MASK 0x1
	239	#define ETH_SLOW_PATH_RX_CQE_VALID_SHIFT 0
	240	/* for PMD mode - valid toggle indication */
	241	#define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_MASK 0x1
	242	#define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_SHIFT 1
	243	#define ETH_SLOW_PATH_RX_CQE_RESERVED2_MASK 0x3F
	244	#define ETH_SLOW_PATH_RX_CQE_RESERVED2_SHIFT 2
25c089d7 YM	245	};
	246
	247	/* union for all ETH Rx CQE types */
	248	union eth_rx_cqe {
	249	struct eth_fast_path_rx_reg_cqe fast_path_regular;
fc48b7a6 YM	250	struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start;
	251	struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont;
	252	struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end;
25c089d7 YM	253	struct eth_slow_path_rx_cqe slow_path;
	254	};
	255
	256	/* ETH Rx CQE type */
	257	enum eth_rx_cqe_type {
	258	ETH_RX_CQE_TYPE_UNUSED,
	259	ETH_RX_CQE_TYPE_REGULAR,
	260	ETH_RX_CQE_TYPE_SLOW_PATH,
fc48b7a6 YM	261	ETH_RX_CQE_TYPE_TPA_START,
	262	ETH_RX_CQE_TYPE_TPA_CONT,
	263	ETH_RX_CQE_TYPE_TPA_END,
25c089d7 YM	264	MAX_ETH_RX_CQE_TYPE
	265	};
	266
	267	/* ETH Rx producers data */
	268	struct eth_rx_prod_data {
	269	__le16 bd_prod;
25c089d7 YM	270	__le16 cqe_prod;
25c089d7 YM	271	__le16 reserved;
fc48b7a6	272	__le16 reserved1;
25c089d7 YM	273	};
	274
	275	/* The first tx bd of a given packet */
	276	struct eth_tx_1st_bd {
	277	struct regpair addr;
	278	__le16 nbytes;
	279	struct eth_tx_data_1st_bd data;
	280	};
	281
	282	/* The second tx bd of a given packet */
	283	struct eth_tx_2nd_bd {
	284	struct regpair addr;
	285	__le16 nbytes;
	286	struct eth_tx_data_2nd_bd data;
	287	};
	288
	289	/* The parsing information data for the third tx bd of a given packet. */
	290	struct eth_tx_data_3rd_bd {
	291	__le16 lso_mss;
fc48b7a6	292	__le16 bitfields;
25c089d7 YM	293	#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
	294	#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
	295	#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
	296	#define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
fc48b7a6 YM	297	#define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1
	298	#define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
	299	#define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
	300	#define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
	301	u8 tunn_l4_hdr_start_offset_w;
	302	u8 tunn_hdr_size_w;
25c089d7 YM	303	};
	304
	305	/* The third tx bd of a given packet */
	306	struct eth_tx_3rd_bd {
	307	struct regpair addr;
	308	__le16 nbytes;
	309	struct eth_tx_data_3rd_bd data;
	310	};
	311
fc48b7a6 YM	312	/* Complementary information for the regular tx bd of a given packet. */
	313	struct eth_tx_data_bd {
	314	__le16 reserved0;
	315	__le16 bitfields;
	316	#define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF
	317	#define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
	318	#define ETH_TX_DATA_BD_START_BD_MASK 0x1
	319	#define ETH_TX_DATA_BD_START_BD_SHIFT 8
	320	#define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F
	321	#define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
	322	__le16 reserved3;
	323	};
	324
25c089d7 YM	325	/* The common non-special TX BD ring element */
	326	struct eth_tx_bd {
	327	struct regpair addr;
	328	__le16 nbytes;
fc48b7a6	329	struct eth_tx_data_bd data;
25c089d7 YM	330	};
	331
	332	union eth_tx_bd_types {
	333	struct eth_tx_1st_bd first_bd;
	334	struct eth_tx_2nd_bd second_bd;
	335	struct eth_tx_3rd_bd third_bd;
	336	struct eth_tx_bd reg_bd;
	337	};
	338
	339	/* Mstorm Queue Zone */
	340	struct mstorm_eth_queue_zone {
	341	struct eth_rx_prod_data rx_producers;
	342	__le32 reserved[2];
	343	};
	344
	345	/* Ustorm Queue Zone */
	346	struct ustorm_eth_queue_zone {
	347	struct coalescing_timeset int_coalescing_timeset;
	348	__le16 reserved[3];
	349	};
	350
	351	/* Ystorm Queue Zone */
	352	struct ystorm_eth_queue_zone {
	353	struct coalescing_timeset int_coalescing_timeset;
	354	__le16 reserved[3];
	355	};
	356
	357	/* ETH doorbell data */
	358	struct eth_db_data {
	359	u8 params;
	360	#define ETH_DB_DATA_DEST_MASK 0x3
	361	#define ETH_DB_DATA_DEST_SHIFT 0
	362	#define ETH_DB_DATA_AGG_CMD_MASK 0x3
	363	#define ETH_DB_DATA_AGG_CMD_SHIFT 2
	364	#define ETH_DB_DATA_BYPASS_EN_MASK 0x1
	365	#define ETH_DB_DATA_BYPASS_EN_SHIFT 4
	366	#define ETH_DB_DATA_RESERVED_MASK 0x1
	367	#define ETH_DB_DATA_RESERVED_SHIFT 5
	368	#define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
	369	#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
	370	u8 agg_flags;
	371	__le16 bd_prod;
	372	};
	373
	374	#endif /* __ETH_COMMON__ */