[deliverable/linux.git] / include / linux / qed / qed_if.h

/* QLogic qed NIC Driver
 *
 * Copyright (c) 2015 QLogic Corporation
 *
 * This software is available under the terms of the GNU General Public License
 * (GPL) Version 2, available from the file COPYING in the main directory of
 * this source tree.
 */

#ifndef _QED_IF_H
#define _QED_IF_H

#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/netdevice.h>
#include <linux/pci.h>
#include <linux/skbuff.h>
#include <linux/types.h>
#include <asm/byteorder.h>
#include <linux/io.h>
#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/qed/common_hsi.h>
#include <linux/qed/qed_chain.h>

enum qed_led_mode {
	QED_LED_MODE_OFF,
	QED_LED_MODE_ON,
	QED_LED_MODE_RESTORE
};

#define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
					    (void __iomem *)(reg_addr))

#define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))

#define QED_COALESCE_MAX 0xFF

/* forward */
struct qed_dev;

struct qed_eth_pf_params {
	/* The following parameters are used during HW-init
	 * and these parameters need to be passed as arguments
	 * to update_pf_params routine invoked before slowpath start
	 */
	u16 num_cons;
};

struct qed_pf_params {
	struct qed_eth_pf_params eth_pf_params;
};

enum qed_int_mode {
	QED_INT_MODE_INTA,
	QED_INT_MODE_MSIX,
	QED_INT_MODE_MSI,
	QED_INT_MODE_POLL,
};

struct qed_sb_info {
	struct status_block	*sb_virt;
	dma_addr_t		sb_phys;
	u32			sb_ack; /* Last given ack */
	u16			igu_sb_id;
	void __iomem		*igu_addr;
	u8			flags;
#define QED_SB_INFO_INIT        0x1
#define QED_SB_INFO_SETUP       0x2

	struct qed_dev		*cdev;
};

struct qed_dev_info {
	unsigned long	pci_mem_start;
	unsigned long	pci_mem_end;
	unsigned int	pci_irq;
	u8		num_hwfns;

	u8		hw_mac[ETH_ALEN];
	bool		is_mf_default;

	/* FW version */
	u16		fw_major;
	u16		fw_minor;
	u16		fw_rev;
	u16		fw_eng;

	/* MFW version */
	u32		mfw_rev;

	u32		flash_size;
	u8		mf_mode;
};

enum qed_sb_type {
	QED_SB_TYPE_L2_QUEUE,
};

enum qed_protocol {
	QED_PROTOCOL_ETH,
};

struct qed_link_params {
	bool	link_up;

#define QED_LINK_OVERRIDE_SPEED_AUTONEG         BIT(0)
#define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS      BIT(1)
#define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED    BIT(2)
#define QED_LINK_OVERRIDE_PAUSE_CONFIG          BIT(3)
	u32	override_flags;
	bool	autoneg;
	u32	adv_speeds;
	u32	forced_speed;
#define QED_LINK_PAUSE_AUTONEG_ENABLE           BIT(0)
#define QED_LINK_PAUSE_RX_ENABLE                BIT(1)
#define QED_LINK_PAUSE_TX_ENABLE                BIT(2)
	u32	pause_config;
};

struct qed_link_output {
	bool	link_up;

	u32	supported_caps;         /* In SUPPORTED defs */
	u32	advertised_caps;        /* In ADVERTISED defs */
	u32	lp_caps;                /* In ADVERTISED defs */
	u32	speed;                  /* In Mb/s */
	u8	duplex;                 /* In DUPLEX defs */
	u8	port;                   /* In PORT defs */
	bool	autoneg;
	u32	pause_config;
};

#define QED_DRV_VER_STR_SIZE 12
struct qed_slowpath_params {
	u32	int_mode;
	u8	drv_major;
	u8	drv_minor;
	u8	drv_rev;
	u8	drv_eng;
	u8	name[QED_DRV_VER_STR_SIZE];
};

#define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */

struct qed_int_info {
	struct msix_entry	*msix;
	u8			msix_cnt;

	/* This should be updated by the protocol driver */
	u8			used_cnt;
};

struct qed_common_cb_ops {
	void	(*link_update)(void			*dev,
			       struct qed_link_output	*link);
};

struct qed_common_ops {
	struct qed_dev*	(*probe)(struct pci_dev *dev,
				 enum qed_protocol protocol,
				 u32 dp_module, u8 dp_level);

	void		(*remove)(struct qed_dev *cdev);

	int		(*set_power_state)(struct qed_dev *cdev,
					   pci_power_t state);

	void		(*set_id)(struct qed_dev *cdev,
				  char name[],
				  char ver_str[]);

	/* Client drivers need to make this call before slowpath_start.
	 * PF params required for the call before slowpath_start is
	 * documented within the qed_pf_params structure definition.
	 */
	void		(*update_pf_params)(struct qed_dev *cdev,
					    struct qed_pf_params *params);
	int		(*slowpath_start)(struct qed_dev *cdev,
					  struct qed_slowpath_params *params);

	int		(*slowpath_stop)(struct qed_dev *cdev);

	/* Requests to use `cnt' interrupts for fastpath.
	 * upon success, returns number of interrupts allocated for fastpath.
	 */
	int		(*set_fp_int)(struct qed_dev *cdev,
				      u16 cnt);

	/* Fills `info' with pointers required for utilizing interrupts */
	int		(*get_fp_int)(struct qed_dev *cdev,
				      struct qed_int_info *info);

	u32		(*sb_init)(struct qed_dev *cdev,
				   struct qed_sb_info *sb_info,
				   void *sb_virt_addr,
				   dma_addr_t sb_phy_addr,
				   u16 sb_id,
				   enum qed_sb_type type);

	u32		(*sb_release)(struct qed_dev *cdev,
				      struct qed_sb_info *sb_info,
				      u16 sb_id);

	void		(*simd_handler_config)(struct qed_dev *cdev,
					       void *token,
					       int index,
					       void (*handler)(void *));

	void		(*simd_handler_clean)(struct qed_dev *cdev,
					      int index);
/**
 * @brief set_link - set links according to params
 *
 * @param cdev
 * @param params - values used to override the default link configuration
 *
 * @return 0 on success, error otherwise.
 */
	int		(*set_link)(struct qed_dev *cdev,
				    struct qed_link_params *params);

/**
 * @brief get_link - returns the current link state.
 *
 * @param cdev
 * @param if_link - structure to be filled with current link configuration.
 */
	void		(*get_link)(struct qed_dev *cdev,
				    struct qed_link_output *if_link);

/**
 * @brief - drains chip in case Tx completions fail to arrive due to pause.
 *
 * @param cdev
 */
	int		(*drain)(struct qed_dev *cdev);

/**
 * @brief update_msglvl - update module debug level
 *
 * @param cdev
 * @param dp_module
 * @param dp_level
 */
	void		(*update_msglvl)(struct qed_dev *cdev,
					 u32 dp_module,
					 u8 dp_level);

	int		(*chain_alloc)(struct qed_dev *cdev,
				       enum qed_chain_use_mode intended_use,
				       enum qed_chain_mode mode,
				       u16 num_elems,
				       size_t elem_size,
				       struct qed_chain *p_chain);

	void		(*chain_free)(struct qed_dev *cdev,
				      struct qed_chain *p_chain);

/**
 * @brief set_led - Configure LED mode
 *
 * @param cdev
 * @param mode - LED mode
 *
 * @return 0 on success, error otherwise.
 */
	int (*set_led)(struct qed_dev *cdev,
		       enum qed_led_mode mode);
};

#define MASK_FIELD(_name, _value) \
	((_value) &= (_name ## _MASK))

#define FIELD_VALUE(_name, _value) \
	((_value & _name ## _MASK) << _name ## _SHIFT)

#define SET_FIELD(value, name, flag)			       \
	do {						       \
		(value) &= ~(name ## _MASK << name ## _SHIFT); \
		(value) |= (((u64)flag) << (name ## _SHIFT));  \
	} while (0)

#define GET_FIELD(value, name) \
	(((value) >> (name ## _SHIFT)) & name ## _MASK)

/* Debug print definitions */
#define DP_ERR(cdev, fmt, ...)						     \
		pr_err("[%s:%d(%s)]" fmt,				     \
		       __func__, __LINE__,				     \
		       DP_NAME(cdev) ? DP_NAME(cdev) : "",		     \
		       ## __VA_ARGS__)					     \

#define DP_NOTICE(cdev, fmt, ...)				      \
	do {							      \
		if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
			pr_notice("[%s:%d(%s)]" fmt,		      \
				  __func__, __LINE__,		      \
				  DP_NAME(cdev) ? DP_NAME(cdev) : "", \
				  ## __VA_ARGS__);		      \
								      \
		}						      \
	} while (0)

#define DP_INFO(cdev, fmt, ...)					      \
	do {							      \
		if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) {   \
			pr_notice("[%s:%d(%s)]" fmt,		      \
				  __func__, __LINE__,		      \
				  DP_NAME(cdev) ? DP_NAME(cdev) : "", \
				  ## __VA_ARGS__);		      \
		}						      \
	} while (0)

#define DP_VERBOSE(cdev, module, fmt, ...)				\
	do {								\
		if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) &&	\
			     ((cdev)->dp_module & module))) {		\
			pr_notice("[%s:%d(%s)]" fmt,			\
				  __func__, __LINE__,			\
				  DP_NAME(cdev) ? DP_NAME(cdev) : "",	\
				  ## __VA_ARGS__);			\
		}							\
	} while (0)

enum DP_LEVEL {
	QED_LEVEL_VERBOSE	= 0x0,
	QED_LEVEL_INFO		= 0x1,
	QED_LEVEL_NOTICE	= 0x2,
	QED_LEVEL_ERR		= 0x3,
};

#define QED_LOG_LEVEL_SHIFT     (30)
#define QED_LOG_VERBOSE_MASK    (0x3fffffff)
#define QED_LOG_INFO_MASK       (0x40000000)
#define QED_LOG_NOTICE_MASK     (0x80000000)

enum DP_MODULE {
	QED_MSG_SPQ	= 0x10000,
	QED_MSG_STATS	= 0x20000,
	QED_MSG_DCB	= 0x40000,
	QED_MSG_IOV	= 0x80000,
	QED_MSG_SP	= 0x100000,
	QED_MSG_STORAGE = 0x200000,
	QED_MSG_CXT	= 0x800000,
	QED_MSG_ILT	= 0x2000000,
	QED_MSG_ROCE	= 0x4000000,
	QED_MSG_DEBUG	= 0x8000000,
	/* to be added...up to 0x8000000 */
};

enum qed_mf_mode {
	QED_MF_DEFAULT,
	QED_MF_OVLAN,
	QED_MF_NPAR,
};

struct qed_eth_stats {
	u64	no_buff_discards;
	u64	packet_too_big_discard;
	u64	ttl0_discard;
	u64	rx_ucast_bytes;
	u64	rx_mcast_bytes;
	u64	rx_bcast_bytes;
	u64	rx_ucast_pkts;
	u64	rx_mcast_pkts;
	u64	rx_bcast_pkts;
	u64	mftag_filter_discards;
	u64	mac_filter_discards;
	u64	tx_ucast_bytes;
	u64	tx_mcast_bytes;
	u64	tx_bcast_bytes;
	u64	tx_ucast_pkts;
	u64	tx_mcast_pkts;
	u64	tx_bcast_pkts;
	u64	tx_err_drop_pkts;
	u64	tpa_coalesced_pkts;
	u64	tpa_coalesced_events;
	u64	tpa_aborts_num;
	u64	tpa_not_coalesced_pkts;
	u64	tpa_coalesced_bytes;

	/* port */
	u64	rx_64_byte_packets;
	u64	rx_65_to_127_byte_packets;
	u64	rx_128_to_255_byte_packets;
	u64	rx_256_to_511_byte_packets;
	u64	rx_512_to_1023_byte_packets;
	u64	rx_1024_to_1518_byte_packets;
	u64	rx_1519_to_1522_byte_packets;
	u64	rx_1519_to_2047_byte_packets;
	u64	rx_2048_to_4095_byte_packets;
	u64	rx_4096_to_9216_byte_packets;
	u64	rx_9217_to_16383_byte_packets;
	u64	rx_crc_errors;
	u64	rx_mac_crtl_frames;
	u64	rx_pause_frames;
	u64	rx_pfc_frames;
	u64	rx_align_errors;
	u64	rx_carrier_errors;
	u64	rx_oversize_packets;
	u64	rx_jabbers;
	u64	rx_undersize_packets;
	u64	rx_fragments;
	u64	tx_64_byte_packets;
	u64	tx_65_to_127_byte_packets;
	u64	tx_128_to_255_byte_packets;
	u64	tx_256_to_511_byte_packets;
	u64	tx_512_to_1023_byte_packets;
	u64	tx_1024_to_1518_byte_packets;
	u64	tx_1519_to_2047_byte_packets;
	u64	tx_2048_to_4095_byte_packets;
	u64	tx_4096_to_9216_byte_packets;
	u64	tx_9217_to_16383_byte_packets;
	u64	tx_pause_frames;
	u64	tx_pfc_frames;
	u64	tx_lpi_entry_count;
	u64	tx_total_collisions;
	u64	brb_truncates;
	u64	brb_discards;
	u64	rx_mac_bytes;
	u64	rx_mac_uc_packets;
	u64	rx_mac_mc_packets;
	u64	rx_mac_bc_packets;
	u64	rx_mac_frames_ok;
	u64	tx_mac_bytes;
	u64	tx_mac_uc_packets;
	u64	tx_mac_mc_packets;
	u64	tx_mac_bc_packets;
	u64	tx_mac_ctrl_frames;
};

#define QED_SB_IDX              0x0002

#define RX_PI           0
#define TX_PI(tc)       (RX_PI + 1 + tc)

struct qed_sb_cnt_info {
	int	sb_cnt;
	int	sb_iov_cnt;
	int	sb_free_blk;
};

static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
{
	u32 prod = 0;
	u16 rc = 0;

	prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
	       STATUS_BLOCK_PROD_INDEX_MASK;
	if (sb_info->sb_ack != prod) {
		sb_info->sb_ack = prod;
		rc |= QED_SB_IDX;
	}

	/* Let SB update */
	mmiowb();
	return rc;
}

/**
 *
 * @brief This function creates an update command for interrupts that is
 *        written to the IGU.
 *
 * @param sb_info       - This is the structure allocated and
 *                 initialized per status block. Assumption is
 *                 that it was initialized using qed_sb_init
 * @param int_cmd       - Enable/Disable/Nop
 * @param upd_flg       - whether igu consumer should be
 *                 updated.
 *
 * @return inline void
 */
static inline void qed_sb_ack(struct qed_sb_info *sb_info,
			      enum igu_int_cmd int_cmd,
			      u8 upd_flg)
{
	struct igu_prod_cons_update igu_ack = { 0 };

	igu_ack.sb_id_and_flags =
		((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
		 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
		 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
		 (IGU_SEG_ACCESS_REG <<
		  IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));

	DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags);

	/* Both segments (interrupts & acks) are written to same place address;
	 * Need to guarantee all commands will be received (in-order) by HW.
	 */
	mmiowb();
	barrier();
}

static inline void __internal_ram_wr(void *p_hwfn,
				     void __iomem *addr,
				     int size,
				     u32 *data)

{
	unsigned int i;

	for (i = 0; i < size / sizeof(*data); i++)
		DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
}

static inline void internal_ram_wr(void __iomem *addr,
				   int size,
				   u32 *data)
{
	__internal_ram_wr(NULL, addr, size, data);
}

enum qed_rss_caps {
	QED_RSS_IPV4		= 0x1,
	QED_RSS_IPV6		= 0x2,
	QED_RSS_IPV4_TCP	= 0x4,
	QED_RSS_IPV6_TCP	= 0x8,
	QED_RSS_IPV4_UDP	= 0x10,
	QED_RSS_IPV6_UDP	= 0x20,
};

#define QED_RSS_IND_TABLE_SIZE 128
#define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */
#endif
Commit	Line	Data
fe56b9e6 YM	1	/* QLogic qed NIC Driver
	2	*
	3	* Copyright (c) 2015 QLogic Corporation
	4	*
	5	* This software is available under the terms of the GNU General Public License
	6	* (GPL) Version 2, available from the file COPYING in the main directory of
	7	* this source tree.
	8	*/
	9
	10	#ifndef _QED_IF_H
	11	#define _QED_IF_H
	12
	13	#include <linux/types.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/netdevice.h>
	16	#include <linux/pci.h>
	17	#include <linux/skbuff.h>
	18	#include <linux/types.h>
	19	#include <asm/byteorder.h>
	20	#include <linux/io.h>
	21	#include <linux/compiler.h>
	22	#include <linux/kernel.h>
	23	#include <linux/list.h>
	24	#include <linux/slab.h>
	25	#include <linux/qed/common_hsi.h>
	26	#include <linux/qed/qed_chain.h>
	27
91420b83 SK	28	enum qed_led_mode {
	29	QED_LED_MODE_OFF,
	30	QED_LED_MODE_ON,
	31	QED_LED_MODE_RESTORE
	32	};
	33
fe56b9e6 YM	34	#define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
	35	(void __iomem *)(reg_addr))
	36
	37	#define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
	38
	39	#define QED_COALESCE_MAX 0xFF
	40
	41	/* forward */
	42	struct qed_dev;
	43
	44	struct qed_eth_pf_params {
	45	/* The following parameters are used during HW-init
	46	* and these parameters need to be passed as arguments
	47	* to update_pf_params routine invoked before slowpath start
	48	*/
	49	u16 num_cons;
	50	};
	51
	52	struct qed_pf_params {
	53	struct qed_eth_pf_params eth_pf_params;
	54	};
	55
	56	enum qed_int_mode {
	57	QED_INT_MODE_INTA,
	58	QED_INT_MODE_MSIX,
	59	QED_INT_MODE_MSI,
	60	QED_INT_MODE_POLL,
	61	};
	62
	63	struct qed_sb_info {
	64	struct status_block *sb_virt;
	65	dma_addr_t sb_phys;
	66	u32 sb_ack; /* Last given ack */
	67	u16 igu_sb_id;
	68	void __iomem *igu_addr;
	69	u8 flags;
	70	#define QED_SB_INFO_INIT 0x1
	71	#define QED_SB_INFO_SETUP 0x2
	72
	73	struct qed_dev *cdev;
	74	};
	75
	76	struct qed_dev_info {
	77	unsigned long pci_mem_start;
	78	unsigned long pci_mem_end;
	79	unsigned int pci_irq;
	80	u8 num_hwfns;
	81
	82	u8 hw_mac[ETH_ALEN];
fc48b7a6	83	bool is_mf_default;
fe56b9e6 YM	84
	85	/* FW version */
	86	u16 fw_major;
	87	u16 fw_minor;
	88	u16 fw_rev;
	89	u16 fw_eng;
	90
	91	/* MFW version */
	92	u32 mfw_rev;
	93
	94	u32 flash_size;
	95	u8 mf_mode;
	96	};
	97
	98	enum qed_sb_type {
	99	QED_SB_TYPE_L2_QUEUE,
	100	};
	101
	102	enum qed_protocol {
	103	QED_PROTOCOL_ETH,
	104	};
	105
	106	struct qed_link_params {
	107	bool link_up;
	108
	109	#define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0)
	110	#define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1)
	111	#define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2)
	112	#define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3)
	113	u32 override_flags;
	114	bool autoneg;
	115	u32 adv_speeds;
	116	u32 forced_speed;
	117	#define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0)
	118	#define QED_LINK_PAUSE_RX_ENABLE BIT(1)
	119	#define QED_LINK_PAUSE_TX_ENABLE BIT(2)
	120	u32 pause_config;
	121	};
	122
	123	struct qed_link_output {
	124	bool link_up;
	125
	126	u32 supported_caps; /* In SUPPORTED defs */
	127	u32 advertised_caps; /* In ADVERTISED defs */
	128	u32 lp_caps; /* In ADVERTISED defs */
	129	u32 speed; /* In Mb/s */
	130	u8 duplex; /* In DUPLEX defs */
	131	u8 port; /* In PORT defs */
	132	bool autoneg;
	133	u32 pause_config;
	134	};
	135
	136	#define QED_DRV_VER_STR_SIZE 12
	137	struct qed_slowpath_params {
	138	u32 int_mode;
	139	u8 drv_major;
	140	u8 drv_minor;
	141	u8 drv_rev;
	142	u8 drv_eng;
	143	u8 name[QED_DRV_VER_STR_SIZE];
	144	};
	145
	146	#define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
	147
148	struct qed_int_info {
149	struct msix_entry *msix;
150	u8 msix_cnt;
151
152	/* This should be updated by the protocol driver */
153	u8 used_cnt;
154	};
155
156	struct qed_common_cb_ops {
157	void (link_update)(void dev,
158	struct qed_link_output *link);
159	};
160
161	struct qed_common_ops {
162	struct qed_dev* (probe)(struct pci_dev dev,
163	enum qed_protocol protocol,
164	u32 dp_module, u8 dp_level);
165
166	void (remove)(struct qed_dev cdev);
167
168	int (set_power_state)(struct qed_dev cdev,
169	pci_power_t state);
170
171	void (set_id)(struct qed_dev cdev,
172	char name[],
173	char ver_str[]);
174
175	/* Client drivers need to make this call before slowpath_start.
176	* PF params required for the call before slowpath_start is
177	* documented within the qed_pf_params structure definition.
178	*/
179	void (update_pf_params)(struct qed_dev cdev,
180	struct qed_pf_params *params);
181	int (slowpath_start)(struct qed_dev cdev,
182	struct qed_slowpath_params *params);
183
184	int (slowpath_stop)(struct qed_dev cdev);
185
186	/* Requests to use `cnt' interrupts for fastpath.
187	* upon success, returns number of interrupts allocated for fastpath.
188	*/
189	int (set_fp_int)(struct qed_dev cdev,
190	u16 cnt);
191
192	/* Fills `info' with pointers required for utilizing interrupts */
193	int (get_fp_int)(struct qed_dev cdev,
194	struct qed_int_info *info);
195
196	u32 (sb_init)(struct qed_dev cdev,
197	struct qed_sb_info *sb_info,
198	void *sb_virt_addr,
199	dma_addr_t sb_phy_addr,
200	u16 sb_id,
201	enum qed_sb_type type);
202
203	u32 (sb_release)(struct qed_dev cdev,
204	struct qed_sb_info *sb_info,
205	u16 sb_id);
206
207	void (simd_handler_config)(struct qed_dev cdev,
208	void *token,
209	int index,
210	void (handler)(void ));
211
212	void (simd_handler_clean)(struct qed_dev cdev,
213	int index);
214	/**
215	* @brief set_link - set links according to params
216	*
217	* @param cdev
218	* @param params - values used to override the default link configuration
219	*
220	* @return 0 on success, error otherwise.
221	*/
222	int (set_link)(struct qed_dev cdev,
223	struct qed_link_params *params);
224
225	/**
226	* @brief get_link - returns the current link state.
227	*
228	* @param cdev
229	* @param if_link - structure to be filled with current link configuration.
230	*/
231	void (get_link)(struct qed_dev cdev,
232	struct qed_link_output *if_link);
233
234	/**
235	* @brief - drains chip in case Tx completions fail to arrive due to pause.
236	*
237	* @param cdev
238	*/
239	int (drain)(struct qed_dev cdev);
240
241	/**
242	* @brief update_msglvl - update module debug level
243	*
244	* @param cdev
245	* @param dp_module
246	* @param dp_level
247	*/
248	void (update_msglvl)(struct qed_dev cdev,
249	u32 dp_module,
250	u8 dp_level);
251
252	int (chain_alloc)(struct qed_dev cdev,
253	enum qed_chain_use_mode intended_use,
254	enum qed_chain_mode mode,
255	u16 num_elems,
256	size_t elem_size,
257	struct qed_chain *p_chain);
258
259	void (chain_free)(struct qed_dev cdev,
260	struct qed_chain *p_chain);
91420b83 SK	261
	262	/**
	263	* @brief set_led - Configure LED mode
	264	*
	265	* @param cdev
	266	* @param mode - LED mode
	267	*
	268	* @return 0 on success, error otherwise.
	269	*/
	270	int (set_led)(struct qed_dev cdev,
	271	enum qed_led_mode mode);
fe56b9e6 YM	272	};
fe56b9e6 YM	273
fe56b9e6 YM	274	#define MASK_FIELD(_name, _value) \
	275	((_value) &= (_name ## _MASK))
	276
	277	#define FIELD_VALUE(_name, _value) \
	278	((_value & _name ## _MASK) << _name ## _SHIFT)
	279
	280	#define SET_FIELD(value, name, flag) \
	281	do { \
	282	(value) &= ~(name ## _MASK << name ## _SHIFT); \
	283	(value) \|= (((u64)flag) << (name ## _SHIFT)); \
	284	} while (0)
	285
	286	#define GET_FIELD(value, name) \
	287	(((value) >> (name ## _SHIFT)) & name ## _MASK)
	288
	289	/* Debug print definitions */
	290	#define DP_ERR(cdev, fmt, ...) \
	291	pr_err("[%s:%d(%s)]" fmt, \
	292	__func__, __LINE__, \
	293	DP_NAME(cdev) ? DP_NAME(cdev) : "", \
	294	## __VA_ARGS__) \
	295
	296	#define DP_NOTICE(cdev, fmt, ...) \
	297	do { \
	298	if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
	299	pr_notice("[%s:%d(%s)]" fmt, \
	300	__func__, __LINE__, \
	301	DP_NAME(cdev) ? DP_NAME(cdev) : "", \
	302	## __VA_ARGS__); \
	303	\
	304	} \
	305	} while (0)
	306
	307	#define DP_INFO(cdev, fmt, ...) \
	308	do { \
	309	if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \
	310	pr_notice("[%s:%d(%s)]" fmt, \
	311	__func__, __LINE__, \
	312	DP_NAME(cdev) ? DP_NAME(cdev) : "", \
	313	## __VA_ARGS__); \
	314	} \
	315	} while (0)
	316
	317	#define DP_VERBOSE(cdev, module, fmt, ...) \
	318	do { \
	319	if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \
	320	((cdev)->dp_module & module))) { \
	321	pr_notice("[%s:%d(%s)]" fmt, \
	322	__func__, __LINE__, \
	323	DP_NAME(cdev) ? DP_NAME(cdev) : "", \
	324	## __VA_ARGS__); \
	325	} \
	326	} while (0)
	327
	328	enum DP_LEVEL {
	329	QED_LEVEL_VERBOSE = 0x0,
	330	QED_LEVEL_INFO = 0x1,
	331	QED_LEVEL_NOTICE = 0x2,
	332	QED_LEVEL_ERR = 0x3,
	333	};
	334
	335	#define QED_LOG_LEVEL_SHIFT (30)
	336	#define QED_LOG_VERBOSE_MASK (0x3fffffff)
	337	#define QED_LOG_INFO_MASK (0x40000000)
338	#define QED_LOG_NOTICE_MASK (0x80000000)
339
340	enum DP_MODULE {
341	QED_MSG_SPQ = 0x10000,
342	QED_MSG_STATS = 0x20000,
343	QED_MSG_DCB = 0x40000,
344	QED_MSG_IOV = 0x80000,
345	QED_MSG_SP = 0x100000,
346	QED_MSG_STORAGE = 0x200000,
347	QED_MSG_CXT = 0x800000,
348	QED_MSG_ILT = 0x2000000,
349	QED_MSG_ROCE = 0x4000000,
350	QED_MSG_DEBUG = 0x8000000,
351	/* to be added...up to 0x8000000 */
352	};
353
fc48b7a6 YM	354	enum qed_mf_mode {
	355	QED_MF_DEFAULT,
	356	QED_MF_OVLAN,
	357	QED_MF_NPAR,
	358	};
	359
fe56b9e6 YM	360	struct qed_eth_stats {
	361	u64 no_buff_discards;
	362	u64 packet_too_big_discard;
	363	u64 ttl0_discard;
	364	u64 rx_ucast_bytes;
	365	u64 rx_mcast_bytes;
	366	u64 rx_bcast_bytes;
	367	u64 rx_ucast_pkts;
	368	u64 rx_mcast_pkts;
	369	u64 rx_bcast_pkts;
	370	u64 mftag_filter_discards;
	371	u64 mac_filter_discards;
	372	u64 tx_ucast_bytes;
	373	u64 tx_mcast_bytes;
	374	u64 tx_bcast_bytes;
	375	u64 tx_ucast_pkts;
	376	u64 tx_mcast_pkts;
	377	u64 tx_bcast_pkts;
	378	u64 tx_err_drop_pkts;
	379	u64 tpa_coalesced_pkts;
	380	u64 tpa_coalesced_events;
	381	u64 tpa_aborts_num;
	382	u64 tpa_not_coalesced_pkts;
	383	u64 tpa_coalesced_bytes;
	384
	385	/* port */
	386	u64 rx_64_byte_packets;
d4967cf3 YM	387	u64 rx_65_to_127_byte_packets;
	388	u64 rx_128_to_255_byte_packets;
	389	u64 rx_256_to_511_byte_packets;
	390	u64 rx_512_to_1023_byte_packets;
	391	u64 rx_1024_to_1518_byte_packets;
	392	u64 rx_1519_to_1522_byte_packets;
	393	u64 rx_1519_to_2047_byte_packets;
	394	u64 rx_2048_to_4095_byte_packets;
	395	u64 rx_4096_to_9216_byte_packets;
	396	u64 rx_9217_to_16383_byte_packets;
fe56b9e6 YM	397	u64 rx_crc_errors;
	398	u64 rx_mac_crtl_frames;
	399	u64 rx_pause_frames;
	400	u64 rx_pfc_frames;
	401	u64 rx_align_errors;
	402	u64 rx_carrier_errors;
	403	u64 rx_oversize_packets;
	404	u64 rx_jabbers;
	405	u64 rx_undersize_packets;
	406	u64 rx_fragments;
	407	u64 tx_64_byte_packets;
	408	u64 tx_65_to_127_byte_packets;
	409	u64 tx_128_to_255_byte_packets;
	410	u64 tx_256_to_511_byte_packets;
	411	u64 tx_512_to_1023_byte_packets;
	412	u64 tx_1024_to_1518_byte_packets;
	413	u64 tx_1519_to_2047_byte_packets;
	414	u64 tx_2048_to_4095_byte_packets;
	415	u64 tx_4096_to_9216_byte_packets;
	416	u64 tx_9217_to_16383_byte_packets;
	417	u64 tx_pause_frames;
	418	u64 tx_pfc_frames;
	419	u64 tx_lpi_entry_count;
	420	u64 tx_total_collisions;
	421	u64 brb_truncates;
	422	u64 brb_discards;
	423	u64 rx_mac_bytes;
	424	u64 rx_mac_uc_packets;
	425	u64 rx_mac_mc_packets;
	426	u64 rx_mac_bc_packets;
	427	u64 rx_mac_frames_ok;
	428	u64 tx_mac_bytes;
	429	u64 tx_mac_uc_packets;
	430	u64 tx_mac_mc_packets;
	431	u64 tx_mac_bc_packets;
	432	u64 tx_mac_ctrl_frames;
	433	};
	434
	435	#define QED_SB_IDX 0x0002
	436
	437	#define RX_PI 0
	438	#define TX_PI(tc) (RX_PI + 1 + tc)
	439
4ac801b7 YM	440	struct qed_sb_cnt_info {
	441	int sb_cnt;
	442	int sb_iov_cnt;
	443	int sb_free_blk;
	444	};
	445
fe56b9e6 YM	446	static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
	447	{
	448	u32 prod = 0;
	449	u16 rc = 0;
	450
	451	prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
	452	STATUS_BLOCK_PROD_INDEX_MASK;
	453	if (sb_info->sb_ack != prod) {
	454	sb_info->sb_ack = prod;
	455	rc \|= QED_SB_IDX;
	456	}
	457
	458	/* Let SB update */
	459	mmiowb();
	460	return rc;
	461	}
	462
	463	/**
	464	*
	465	* @brief This function creates an update command for interrupts that is
	466	* written to the IGU.
	467	*
	468	* @param sb_info - This is the structure allocated and
	469	* initialized per status block. Assumption is
	470	* that it was initialized using qed_sb_init
	471	* @param int_cmd - Enable/Disable/Nop
	472	* @param upd_flg - whether igu consumer should be
	473	* updated.
	474	*
	475	* @return inline void
	476	*/
	477	static inline void qed_sb_ack(struct qed_sb_info *sb_info,
	478	enum igu_int_cmd int_cmd,
	479	u8 upd_flg)
	480	{
	481	struct igu_prod_cons_update igu_ack = { 0 };
	482
	483	igu_ack.sb_id_and_flags =
	484	((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) \|
	485	(upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) \|
	486	(int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) \|
	487	(IGU_SEG_ACCESS_REG <<
	488	IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
	489
	490	DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags);
	491
	492	/* Both segments (interrupts & acks) are written to same place address;
	493	* Need to guarantee all commands will be received (in-order) by HW.
	494	*/
	495	mmiowb();
	496	barrier();
	497	}
	498
	499	static inline void __internal_ram_wr(void *p_hwfn,
	500	void __iomem *addr,
	501	int size,
	502	u32 *data)
	503
	504	{
	505	unsigned int i;
	506
	507	for (i = 0; i < size / sizeof(*data); i++)
	508	DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
	509	}
510
511	static inline void internal_ram_wr(void __iomem *addr,
512	int size,
513	u32 *data)
514	{
515	__internal_ram_wr(NULL, addr, size, data);
516	}
517
8c5ebd0c SRK	518	enum qed_rss_caps {
	519	QED_RSS_IPV4 = 0x1,
	520	QED_RSS_IPV6 = 0x2,
	521	QED_RSS_IPV4_TCP = 0x4,
	522	QED_RSS_IPV6_TCP = 0x8,
	523	QED_RSS_IPV4_UDP = 0x10,
	524	QED_RSS_IPV6_UDP = 0x20,
	525	};
	526
	527	#define QED_RSS_IND_TABLE_SIZE 128
	528	#define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */
fe56b9e6	529	#endif