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d28bdf05 MD |
1 | #ifndef __SH_CLOCK_H |
2 | #define __SH_CLOCK_H | |
3 | ||
4 | #include <linux/list.h> | |
5 | #include <linux/seq_file.h> | |
6 | #include <linux/cpufreq.h> | |
28085bc5 PM |
7 | #include <linux/types.h> |
8 | #include <linux/kref.h> | |
d28bdf05 MD |
9 | #include <linux/clk.h> |
10 | #include <linux/err.h> | |
11 | ||
12 | struct clk; | |
13 | ||
28085bc5 PM |
14 | struct clk_mapping { |
15 | phys_addr_t phys; | |
16 | void __iomem *base; | |
17 | unsigned long len; | |
18 | struct kref ref; | |
19 | }; | |
20 | ||
84c36ffd | 21 | struct sh_clk_ops { |
549015c3 | 22 | #ifdef CONFIG_SH_CLK_CPG_LEGACY |
d28bdf05 | 23 | void (*init)(struct clk *clk); |
549015c3 | 24 | #endif |
d28bdf05 MD |
25 | int (*enable)(struct clk *clk); |
26 | void (*disable)(struct clk *clk); | |
27 | unsigned long (*recalc)(struct clk *clk); | |
35a96c73 | 28 | int (*set_rate)(struct clk *clk, unsigned long rate); |
d28bdf05 MD |
29 | int (*set_parent)(struct clk *clk, struct clk *parent); |
30 | long (*round_rate)(struct clk *clk, unsigned long rate); | |
31 | }; | |
32 | ||
1111cc1e PM |
33 | #define SH_CLK_DIV_MSK(div) ((1 << (div)) - 1) |
34 | #define SH_CLK_DIV4_MSK SH_CLK_DIV_MSK(4) | |
35 | #define SH_CLK_DIV6_MSK SH_CLK_DIV_MSK(6) | |
36 | ||
d28bdf05 MD |
37 | struct clk { |
38 | struct list_head node; | |
d28bdf05 | 39 | struct clk *parent; |
b5272b50 GL |
40 | struct clk **parent_table; /* list of parents to */ |
41 | unsigned short parent_num; /* choose between */ | |
42 | unsigned char src_shift; /* source clock field in the */ | |
43 | unsigned char src_width; /* configuration register */ | |
84c36ffd | 44 | struct sh_clk_ops *ops; |
d28bdf05 MD |
45 | |
46 | struct list_head children; | |
47 | struct list_head sibling; /* node for children */ | |
48 | ||
49 | int usecount; | |
50 | ||
51 | unsigned long rate; | |
52 | unsigned long flags; | |
53 | ||
54 | void __iomem *enable_reg; | |
a028c6da | 55 | void __iomem *status_reg; |
d28bdf05 | 56 | unsigned int enable_bit; |
eda2030a | 57 | void __iomem *mapped_reg; |
d28bdf05 | 58 | |
1111cc1e | 59 | unsigned int div_mask; |
d28bdf05 MD |
60 | unsigned long arch_flags; |
61 | void *priv; | |
28085bc5 | 62 | struct clk_mapping *mapping; |
d28bdf05 | 63 | struct cpufreq_frequency_table *freq_table; |
f586903d | 64 | unsigned int nr_freqs; |
d28bdf05 MD |
65 | }; |
66 | ||
4d6ddb08 PM |
67 | #define CLK_ENABLE_ON_INIT BIT(0) |
68 | ||
69 | #define CLK_ENABLE_REG_32BIT BIT(1) /* default access size */ | |
70 | #define CLK_ENABLE_REG_16BIT BIT(2) | |
71 | #define CLK_ENABLE_REG_8BIT BIT(3) | |
72 | ||
764f4e4e PM |
73 | #define CLK_MASK_DIV_ON_DISABLE BIT(4) |
74 | ||
4d6ddb08 PM |
75 | #define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT | \ |
76 | CLK_ENABLE_REG_16BIT | \ | |
77 | CLK_ENABLE_REG_8BIT) | |
d28bdf05 | 78 | |
a71ba096 | 79 | /* drivers/sh/clk.c */ |
d28bdf05 MD |
80 | unsigned long followparent_recalc(struct clk *); |
81 | void recalculate_root_clocks(void); | |
82 | void propagate_rate(struct clk *); | |
83 | int clk_reparent(struct clk *child, struct clk *parent); | |
84 | int clk_register(struct clk *); | |
85 | void clk_unregister(struct clk *); | |
8b5ee113 | 86 | void clk_enable_init_clocks(void); |
d28bdf05 | 87 | |
d28bdf05 MD |
88 | struct clk_div_mult_table { |
89 | unsigned int *divisors; | |
90 | unsigned int nr_divisors; | |
91 | unsigned int *multipliers; | |
92 | unsigned int nr_multipliers; | |
93 | }; | |
94 | ||
95 | struct cpufreq_frequency_table; | |
96 | void clk_rate_table_build(struct clk *clk, | |
97 | struct cpufreq_frequency_table *freq_table, | |
98 | int nr_freqs, | |
99 | struct clk_div_mult_table *src_table, | |
100 | unsigned long *bitmap); | |
101 | ||
102 | long clk_rate_table_round(struct clk *clk, | |
103 | struct cpufreq_frequency_table *freq_table, | |
104 | unsigned long rate); | |
105 | ||
106 | int clk_rate_table_find(struct clk *clk, | |
107 | struct cpufreq_frequency_table *freq_table, | |
108 | unsigned long rate); | |
109 | ||
8e122db6 PM |
110 | long clk_rate_div_range_round(struct clk *clk, unsigned int div_min, |
111 | unsigned int div_max, unsigned long rate); | |
112 | ||
dd2c0ca1 KM |
113 | long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min, |
114 | unsigned int mult_max, unsigned long rate); | |
115 | ||
6af26c6c GL |
116 | long clk_round_parent(struct clk *clk, unsigned long target, |
117 | unsigned long *best_freq, unsigned long *parent_freq, | |
118 | unsigned int div_min, unsigned int div_max); | |
119 | ||
a028c6da | 120 | #define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \ |
d28bdf05 MD |
121 | { \ |
122 | .parent = _parent, \ | |
123 | .enable_reg = (void __iomem *)_enable_reg, \ | |
124 | .enable_bit = _enable_bit, \ | |
a028c6da | 125 | .status_reg = _status_reg, \ |
d28bdf05 MD |
126 | .flags = _flags, \ |
127 | } | |
128 | ||
a028c6da GL |
129 | #define SH_CLK_MSTP32(_p, _r, _b, _f) \ |
130 | SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_32BIT) | |
4d6ddb08 | 131 | |
a028c6da GL |
132 | #define SH_CLK_MSTP32_STS(_p, _r, _b, _s, _f) \ |
133 | SH_CLK_MSTP(_p, _r, _b, _s, _f | CLK_ENABLE_REG_32BIT) | |
4d6ddb08 | 134 | |
a028c6da GL |
135 | #define SH_CLK_MSTP16(_p, _r, _b, _f) \ |
136 | SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_16BIT) | |
137 | ||
138 | #define SH_CLK_MSTP8(_p, _r, _b, _f) \ | |
139 | SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_8BIT) | |
4d6ddb08 PM |
140 | |
141 | int sh_clk_mstp_register(struct clk *clks, int nr); | |
142 | ||
143 | /* | |
144 | * MSTP registration never really cared about access size, despite the | |
145 | * original enable/disable pairs assuming a 32-bit access. Clocks are | |
146 | * responsible for defining their access sizes either directly or via the | |
147 | * clock definition wrappers. | |
148 | */ | |
149 | static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr) | |
150 | { | |
151 | return sh_clk_mstp_register(clks, nr); | |
152 | } | |
d28bdf05 MD |
153 | |
154 | #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ | |
155 | { \ | |
156 | .parent = _parent, \ | |
157 | .enable_reg = (void __iomem *)_reg, \ | |
158 | .enable_bit = _shift, \ | |
159 | .arch_flags = _div_bitmap, \ | |
1111cc1e | 160 | .div_mask = SH_CLK_DIV4_MSK, \ |
d28bdf05 MD |
161 | .flags = _flags, \ |
162 | } | |
163 | ||
a60977a5 | 164 | struct clk_div_table { |
d28bdf05 MD |
165 | struct clk_div_mult_table *div_mult_table; |
166 | void (*kick)(struct clk *clk); | |
167 | }; | |
168 | ||
a60977a5 PM |
169 | #define clk_div4_table clk_div_table |
170 | ||
d28bdf05 MD |
171 | int sh_clk_div4_register(struct clk *clks, int nr, |
172 | struct clk_div4_table *table); | |
173 | int sh_clk_div4_enable_register(struct clk *clks, int nr, | |
174 | struct clk_div4_table *table); | |
175 | int sh_clk_div4_reparent_register(struct clk *clks, int nr, | |
176 | struct clk_div4_table *table); | |
177 | ||
56242a1f | 178 | #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ |
b3dd51a8 GL |
179 | _num_parents, _src_shift, _src_width) \ |
180 | { \ | |
b3dd51a8 | 181 | .enable_reg = (void __iomem *)_reg, \ |
75f5f8a5 | 182 | .enable_bit = 0, /* unused */ \ |
764f4e4e | 183 | .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \ |
1111cc1e | 184 | .div_mask = SH_CLK_DIV6_MSK, \ |
b3dd51a8 GL |
185 | .parent_table = _parents, \ |
186 | .parent_num = _num_parents, \ | |
187 | .src_shift = _src_shift, \ | |
188 | .src_width = _src_width, \ | |
d28bdf05 MD |
189 | } |
190 | ||
b3dd51a8 | 191 | #define SH_CLK_DIV6(_parent, _reg, _flags) \ |
56242a1f KM |
192 | { \ |
193 | .parent = _parent, \ | |
194 | .enable_reg = (void __iomem *)_reg, \ | |
75f5f8a5 | 195 | .enable_bit = 0, /* unused */ \ |
1111cc1e | 196 | .div_mask = SH_CLK_DIV6_MSK, \ |
764f4e4e | 197 | .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \ |
56242a1f | 198 | } |
b3dd51a8 | 199 | |
d28bdf05 | 200 | int sh_clk_div6_register(struct clk *clks, int nr); |
b3dd51a8 | 201 | int sh_clk_div6_reparent_register(struct clk *clks, int nr); |
d28bdf05 | 202 | |
1522043b KM |
203 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } |
204 | #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } | |
205 | #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk } | |
206 | ||
9d626ecc KM |
207 | /* .enable_reg will be updated to .mapping on sh_clk_fsidiv_register() */ |
208 | #define SH_CLK_FSIDIV(_reg, _parent) \ | |
209 | { \ | |
210 | .enable_reg = (void __iomem *)_reg, \ | |
211 | .parent = _parent, \ | |
212 | } | |
213 | ||
214 | int sh_clk_fsidiv_register(struct clk *clks, int nr); | |
215 | ||
d28bdf05 | 216 | #endif /* __SH_CLOCK_H */ |