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8ae12a0d DB |
1 | /* |
2 | * Copyright (C) 2005 David Brownell | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
8ae12a0d DB |
13 | */ |
14 | ||
15 | #ifndef __LINUX_SPI_H | |
16 | #define __LINUX_SPI_H | |
17 | ||
0a30c5ce | 18 | #include <linux/device.h> |
75368bf6 | 19 | #include <linux/mod_devicetable.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
ffbbdd21 | 21 | #include <linux/kthread.h> |
b158935f | 22 | #include <linux/completion.h> |
6ad45a27 | 23 | #include <linux/scatterlist.h> |
0a30c5ce | 24 | |
99adef31 | 25 | struct dma_chan; |
eca2ebc7 MS |
26 | struct spi_master; |
27 | struct spi_transfer; | |
556351f1 | 28 | struct spi_flash_read_message; |
0a30c5ce | 29 | |
8ae12a0d | 30 | /* |
b885244e | 31 | * INTERFACES between SPI master-side drivers and SPI infrastructure. |
8ae12a0d | 32 | * (There's no SPI slave support for Linux yet...) |
8ae12a0d DB |
33 | */ |
34 | extern struct bus_type spi_bus_type; | |
35 | ||
eca2ebc7 MS |
36 | /** |
37 | * struct spi_statistics - statistics for spi transfers | |
0243ed44 | 38 | * @lock: lock protecting this structure |
eca2ebc7 MS |
39 | * |
40 | * @messages: number of spi-messages handled | |
41 | * @transfers: number of spi_transfers handled | |
42 | * @errors: number of errors during spi_transfer | |
43 | * @timedout: number of timeouts during spi_transfer | |
44 | * | |
45 | * @spi_sync: number of times spi_sync is used | |
46 | * @spi_sync_immediate: | |
47 | * number of times spi_sync is executed immediately | |
48 | * in calling context without queuing and scheduling | |
49 | * @spi_async: number of times spi_async is used | |
50 | * | |
51 | * @bytes: number of bytes transferred to/from device | |
52 | * @bytes_tx: number of bytes sent to device | |
53 | * @bytes_rx: number of bytes received from device | |
54 | * | |
6b7bc061 MS |
55 | * @transfer_bytes_histo: |
56 | * transfer bytes histogramm | |
d9f12122 MS |
57 | * |
58 | * @transfers_split_maxsize: | |
59 | * number of transfers that have been split because of | |
60 | * maxsize limit | |
eca2ebc7 MS |
61 | */ |
62 | struct spi_statistics { | |
63 | spinlock_t lock; /* lock for the whole structure */ | |
64 | ||
65 | unsigned long messages; | |
66 | unsigned long transfers; | |
67 | unsigned long errors; | |
68 | unsigned long timedout; | |
69 | ||
70 | unsigned long spi_sync; | |
71 | unsigned long spi_sync_immediate; | |
72 | unsigned long spi_async; | |
73 | ||
74 | unsigned long long bytes; | |
75 | unsigned long long bytes_rx; | |
76 | unsigned long long bytes_tx; | |
77 | ||
6b7bc061 MS |
78 | #define SPI_STATISTICS_HISTO_SIZE 17 |
79 | unsigned long transfer_bytes_histo[SPI_STATISTICS_HISTO_SIZE]; | |
d9f12122 MS |
80 | |
81 | unsigned long transfers_split_maxsize; | |
eca2ebc7 MS |
82 | }; |
83 | ||
84 | void spi_statistics_add_transfer_stats(struct spi_statistics *stats, | |
85 | struct spi_transfer *xfer, | |
86 | struct spi_master *master); | |
87 | ||
88 | #define SPI_STATISTICS_ADD_TO_FIELD(stats, field, count) \ | |
89 | do { \ | |
90 | unsigned long flags; \ | |
91 | spin_lock_irqsave(&(stats)->lock, flags); \ | |
92 | (stats)->field += count; \ | |
93 | spin_unlock_irqrestore(&(stats)->lock, flags); \ | |
94 | } while (0) | |
95 | ||
96 | #define SPI_STATISTICS_INCREMENT_FIELD(stats, field) \ | |
97 | SPI_STATISTICS_ADD_TO_FIELD(stats, field, 1) | |
98 | ||
8ae12a0d DB |
99 | /** |
100 | * struct spi_device - Master side proxy for an SPI slave device | |
101 | * @dev: Driver model representation of the device. | |
102 | * @master: SPI controller used with the device. | |
103 | * @max_speed_hz: Maximum clock rate to be used with this chip | |
104 | * (on this board); may be changed by the device's driver. | |
4cff33f9 | 105 | * The spi_transfer.speed_hz can override this for each transfer. |
33e34dc6 | 106 | * @chip_select: Chipselect, distinguishing chips handled by @master. |
8ae12a0d DB |
107 | * @mode: The spi mode defines how data is clocked out and in. |
108 | * This may be changed by the device's driver. | |
33e34dc6 DB |
109 | * The "active low" default for chipselect mode can be overridden |
110 | * (by specifying SPI_CS_HIGH) as can the "MSB first" default for | |
111 | * each word in a transfer (by specifying SPI_LSB_FIRST). | |
8ae12a0d | 112 | * @bits_per_word: Data transfers involve one or more words; word sizes |
747d844e | 113 | * like eight or 12 bits are common. In-memory wordsizes are |
8ae12a0d | 114 | * powers of two bytes (e.g. 20 bit samples use 32 bits). |
ccf77cc4 DB |
115 | * This may be changed by the device's driver, or left at the |
116 | * default (0) indicating protocol words are eight bit bytes. | |
4cff33f9 | 117 | * The spi_transfer.bits_per_word can override this for each transfer. |
8ae12a0d | 118 | * @irq: Negative, or the number passed to request_irq() to receive |
747d844e | 119 | * interrupts from this device. |
8ae12a0d | 120 | * @controller_state: Controller's runtime state |
b885244e | 121 | * @controller_data: Board-specific definitions for controller, such as |
747d844e | 122 | * FIFO initialization parameters; from board_info.controller_data |
33e34dc6 DB |
123 | * @modalias: Name of the driver to use with this device, or an alias |
124 | * for that name. This appears in the sysfs "modalias" attribute | |
125 | * for driver coldplugging, and in uevents used for hotplugging | |
446411e1 | 126 | * @cs_gpio: gpio number of the chipselect line (optional, -ENOENT when |
095c3752 | 127 | * when not using a GPIO line) |
8ae12a0d | 128 | * |
eca2ebc7 MS |
129 | * @statistics: statistics for the spi_device |
130 | * | |
33e34dc6 | 131 | * A @spi_device is used to interchange data between an SPI slave |
8ae12a0d DB |
132 | * (usually a discrete chip) and CPU memory. |
133 | * | |
33e34dc6 | 134 | * In @dev, the platform_data is used to hold information about this |
8ae12a0d DB |
135 | * device that's meaningful to the device's protocol driver, but not |
136 | * to its controller. One example might be an identifier for a chip | |
33e34dc6 DB |
137 | * variant with slightly different functionality; another might be |
138 | * information about how this particular board wires the chip's pins. | |
8ae12a0d DB |
139 | */ |
140 | struct spi_device { | |
141 | struct device dev; | |
142 | struct spi_master *master; | |
143 | u32 max_speed_hz; | |
144 | u8 chip_select; | |
89c1f607 | 145 | u8 bits_per_word; |
f477b7fb | 146 | u16 mode; |
b885244e DB |
147 | #define SPI_CPHA 0x01 /* clock phase */ |
148 | #define SPI_CPOL 0x02 /* clock polarity */ | |
0c868461 DB |
149 | #define SPI_MODE_0 (0|0) /* (original MicroWire) */ |
150 | #define SPI_MODE_1 (0|SPI_CPHA) | |
8ae12a0d DB |
151 | #define SPI_MODE_2 (SPI_CPOL|0) |
152 | #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) | |
b885244e | 153 | #define SPI_CS_HIGH 0x04 /* chipselect active high? */ |
ccf77cc4 | 154 | #define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ |
c06e677a | 155 | #define SPI_3WIRE 0x10 /* SI/SO signals shared */ |
4ef7af50 | 156 | #define SPI_LOOP 0x20 /* loopback mode */ |
b55f627f DB |
157 | #define SPI_NO_CS 0x40 /* 1 dev/bus, no chipselect */ |
158 | #define SPI_READY 0x80 /* slave pulls low to pause */ | |
f477b7fb | 159 | #define SPI_TX_DUAL 0x100 /* transmit with 2 wires */ |
160 | #define SPI_TX_QUAD 0x200 /* transmit with 4 wires */ | |
161 | #define SPI_RX_DUAL 0x400 /* receive with 2 wires */ | |
162 | #define SPI_RX_QUAD 0x800 /* receive with 4 wires */ | |
8ae12a0d DB |
163 | int irq; |
164 | void *controller_state; | |
b885244e | 165 | void *controller_data; |
75368bf6 | 166 | char modalias[SPI_NAME_SIZE]; |
74317984 | 167 | int cs_gpio; /* chip select gpio */ |
8ae12a0d | 168 | |
eca2ebc7 MS |
169 | /* the statistics */ |
170 | struct spi_statistics statistics; | |
171 | ||
33e34dc6 DB |
172 | /* |
173 | * likely need more hooks for more protocol options affecting how | |
174 | * the controller talks to each chip, like: | |
175 | * - memory packing (12 bit samples into low bits, others zeroed) | |
176 | * - priority | |
177 | * - drop chipselect after each word | |
178 | * - chipselect delays | |
179 | * - ... | |
180 | */ | |
8ae12a0d DB |
181 | }; |
182 | ||
183 | static inline struct spi_device *to_spi_device(struct device *dev) | |
184 | { | |
b885244e | 185 | return dev ? container_of(dev, struct spi_device, dev) : NULL; |
8ae12a0d DB |
186 | } |
187 | ||
188 | /* most drivers won't need to care about device refcounting */ | |
189 | static inline struct spi_device *spi_dev_get(struct spi_device *spi) | |
190 | { | |
191 | return (spi && get_device(&spi->dev)) ? spi : NULL; | |
192 | } | |
193 | ||
194 | static inline void spi_dev_put(struct spi_device *spi) | |
195 | { | |
196 | if (spi) | |
197 | put_device(&spi->dev); | |
198 | } | |
199 | ||
200 | /* ctldata is for the bus_master driver's runtime state */ | |
201 | static inline void *spi_get_ctldata(struct spi_device *spi) | |
202 | { | |
203 | return spi->controller_state; | |
204 | } | |
205 | ||
206 | static inline void spi_set_ctldata(struct spi_device *spi, void *state) | |
207 | { | |
208 | spi->controller_state = state; | |
209 | } | |
210 | ||
9b40ff4d BD |
211 | /* device driver data */ |
212 | ||
213 | static inline void spi_set_drvdata(struct spi_device *spi, void *data) | |
214 | { | |
215 | dev_set_drvdata(&spi->dev, data); | |
216 | } | |
217 | ||
218 | static inline void *spi_get_drvdata(struct spi_device *spi) | |
219 | { | |
220 | return dev_get_drvdata(&spi->dev); | |
221 | } | |
8ae12a0d DB |
222 | |
223 | struct spi_message; | |
b158935f | 224 | struct spi_transfer; |
b885244e | 225 | |
2604288f DB |
226 | /** |
227 | * struct spi_driver - Host side "protocol" driver | |
75368bf6 | 228 | * @id_table: List of SPI devices supported by this driver |
2604288f DB |
229 | * @probe: Binds this driver to the spi device. Drivers can verify |
230 | * that the device is actually present, and may need to configure | |
231 | * characteristics (such as bits_per_word) which weren't needed for | |
232 | * the initial configuration done during system setup. | |
233 | * @remove: Unbinds this driver from the spi device | |
234 | * @shutdown: Standard shutdown callback used during system state | |
235 | * transitions such as powerdown/halt and kexec | |
2604288f DB |
236 | * @driver: SPI device drivers should initialize the name and owner |
237 | * field of this structure. | |
238 | * | |
239 | * This represents the kind of device driver that uses SPI messages to | |
240 | * interact with the hardware at the other end of a SPI link. It's called | |
241 | * a "protocol" driver because it works through messages rather than talking | |
242 | * directly to SPI hardware (which is what the underlying SPI controller | |
243 | * driver does to pass those messages). These protocols are defined in the | |
244 | * specification for the device(s) supported by the driver. | |
245 | * | |
246 | * As a rule, those device protocols represent the lowest level interface | |
247 | * supported by a driver, and it will support upper level interfaces too. | |
248 | * Examples of such upper levels include frameworks like MTD, networking, | |
249 | * MMC, RTC, filesystem character device nodes, and hardware monitoring. | |
250 | */ | |
b885244e | 251 | struct spi_driver { |
75368bf6 | 252 | const struct spi_device_id *id_table; |
b885244e DB |
253 | int (*probe)(struct spi_device *spi); |
254 | int (*remove)(struct spi_device *spi); | |
255 | void (*shutdown)(struct spi_device *spi); | |
b885244e DB |
256 | struct device_driver driver; |
257 | }; | |
258 | ||
259 | static inline struct spi_driver *to_spi_driver(struct device_driver *drv) | |
260 | { | |
261 | return drv ? container_of(drv, struct spi_driver, driver) : NULL; | |
262 | } | |
263 | ||
ca5d2485 | 264 | extern int __spi_register_driver(struct module *owner, struct spi_driver *sdrv); |
b885244e | 265 | |
33e34dc6 DB |
266 | /** |
267 | * spi_unregister_driver - reverse effect of spi_register_driver | |
268 | * @sdrv: the driver to unregister | |
269 | * Context: can sleep | |
270 | */ | |
b885244e DB |
271 | static inline void spi_unregister_driver(struct spi_driver *sdrv) |
272 | { | |
ddc1e975 BD |
273 | if (sdrv) |
274 | driver_unregister(&sdrv->driver); | |
b885244e DB |
275 | } |
276 | ||
ca5d2485 AD |
277 | /* use a define to avoid include chaining to get THIS_MODULE */ |
278 | #define spi_register_driver(driver) \ | |
279 | __spi_register_driver(THIS_MODULE, driver) | |
280 | ||
3acbb014 LPC |
281 | /** |
282 | * module_spi_driver() - Helper macro for registering a SPI driver | |
283 | * @__spi_driver: spi_driver struct | |
284 | * | |
285 | * Helper macro for SPI drivers which do not do anything special in module | |
286 | * init/exit. This eliminates a lot of boilerplate. Each module may only | |
287 | * use this macro once, and calling it replaces module_init() and module_exit() | |
288 | */ | |
289 | #define module_spi_driver(__spi_driver) \ | |
290 | module_driver(__spi_driver, spi_register_driver, \ | |
291 | spi_unregister_driver) | |
b885244e | 292 | |
8ae12a0d DB |
293 | /** |
294 | * struct spi_master - interface to SPI master controller | |
49dce689 | 295 | * @dev: device interface to this driver |
2b9603a0 | 296 | * @list: link with the global spi_master list |
8ae12a0d | 297 | * @bus_num: board-specific (and often SOC-specific) identifier for a |
747d844e | 298 | * given SPI controller. |
b885244e | 299 | * @num_chipselect: chipselects are used to distinguish individual |
747d844e DB |
300 | * SPI slaves, and are numbered from zero to num_chipselects. |
301 | * each slave has a chipselect signal, but it's common that not | |
302 | * every chipselect is connected to a slave. | |
fd5e191e | 303 | * @dma_alignment: SPI controller constraint on DMA buffers alignment. |
b73b2559 | 304 | * @mode_bits: flags understood by this controller driver |
543bb255 SW |
305 | * @bits_per_word_mask: A mask indicating which values of bits_per_word are |
306 | * supported by the driver. Bit n indicates that a bits_per_word n+1 is | |
e227867f | 307 | * supported. If set, the SPI core will reject any transfer with an |
543bb255 SW |
308 | * unsupported bits_per_word. If not set, this value is simply ignored, |
309 | * and it's up to the individual driver to perform any validation. | |
a2fd4f9f MB |
310 | * @min_speed_hz: Lowest supported transfer speed |
311 | * @max_speed_hz: Highest supported transfer speed | |
b73b2559 | 312 | * @flags: other constraints relevant to this driver |
ee7683a3 RD |
313 | * @max_transfer_size: function that returns the max transfer size for |
314 | * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. | |
5c79a5ae ES |
315 | * @bus_lock_spinlock: spinlock for SPI bus locking |
316 | * @bus_lock_mutex: mutex for SPI bus locking | |
317 | * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use | |
8ae12a0d | 318 | * @setup: updates the device mode and clocking records used by a |
80224561 DB |
319 | * device's SPI controller; protocol code may call this. This |
320 | * must fail if an unrecognized or unsupported mode is requested. | |
33e34dc6 DB |
321 | * It's always safe to call this unless transfers are pending on |
322 | * the device whose settings are being modified. | |
8ae12a0d DB |
323 | * @transfer: adds a message to the controller's transfer queue. |
324 | * @cleanup: frees controller-specific state | |
2c675689 | 325 | * @can_dma: determine whether this master supports DMA |
ffbbdd21 LW |
326 | * @queued: whether this master is providing an internal message queue |
327 | * @kworker: thread struct for message pump | |
328 | * @kworker_task: pointer to task for message pump kworker thread | |
329 | * @pump_messages: work struct for scheduling work to the message pump | |
330 | * @queue_lock: spinlock to syncronise access to message queue | |
331 | * @queue: message queue | |
0461a414 | 332 | * @idling: the device is entering idle state |
ffbbdd21 | 333 | * @cur_msg: the currently in-flight message |
2841a5fc MB |
334 | * @cur_msg_prepared: spi_prepare_message was called for the currently |
335 | * in-flight message | |
2c675689 | 336 | * @cur_msg_mapped: message has been mapped for DMA |
e227867f | 337 | * @xfer_completion: used by core transfer_one_message() |
ffbbdd21 LW |
338 | * @busy: message pump is busy |
339 | * @running: message pump is running | |
340 | * @rt: whether this queue is set to run as a realtime task | |
49834de2 MB |
341 | * @auto_runtime_pm: the core should ensure a runtime PM reference is held |
342 | * while the hardware is prepared, using the parent | |
343 | * device for the spidev | |
6ad45a27 | 344 | * @max_dma_len: Maximum length of a DMA transfer for the device. |
ffbbdd21 LW |
345 | * @prepare_transfer_hardware: a message will soon arrive from the queue |
346 | * so the subsystem requests the driver to prepare the transfer hardware | |
347 | * by issuing this call | |
348 | * @transfer_one_message: the subsystem calls the driver to transfer a single | |
349 | * message while queuing transfers that arrive in the meantime. When the | |
350 | * driver is finished with this message, it must call | |
351 | * spi_finalize_current_message() so the subsystem can issue the next | |
e9305331 | 352 | * message |
dbabe0d6 | 353 | * @unprepare_transfer_hardware: there are currently no more messages on the |
ffbbdd21 LW |
354 | * queue so the subsystem notifies the driver that it may relax the |
355 | * hardware by issuing this call | |
bd6857a0 | 356 | * @set_cs: set the logic level of the chip select line. May be called |
b158935f | 357 | * from interrupt context. |
2841a5fc MB |
358 | * @prepare_message: set up the controller to transfer a single message, |
359 | * for example doing DMA mapping. Called from threaded | |
360 | * context. | |
0516712c GU |
361 | * @transfer_one: transfer a single spi_transfer. |
362 | * - return 0 if the transfer is finished, | |
363 | * - return 1 if the transfer is still in progress. When | |
364 | * the driver is finished with this transfer it must | |
365 | * call spi_finalize_current_transfer() so the subsystem | |
6e5f5267 BS |
366 | * can issue the next transfer. Note: transfer_one and |
367 | * transfer_one_message are mutually exclusive; when both | |
368 | * are set, the generic subsystem does not call your | |
369 | * transfer_one callback. | |
ff61eb42 | 370 | * @handle_err: the subsystem calls the driver to handle an error that occurs |
b716c4ff | 371 | * in the generic implementation of transfer_one_message(). |
2841a5fc | 372 | * @unprepare_message: undo any work done by prepare_message(). |
556351f1 V |
373 | * @spi_flash_read: to support spi-controller hardwares that provide |
374 | * accelerated interface to read from flash devices. | |
095c3752 | 375 | * @cs_gpios: Array of GPIOs to use as chip select lines; one per CS |
446411e1 | 376 | * number. Any individual value may be -ENOENT for CS lines that |
095c3752 | 377 | * are not GPIOs (driven by the SPI controller itself). |
eca2ebc7 | 378 | * @statistics: statistics for the spi_master |
2c675689 TR |
379 | * @dma_tx: DMA transmit channel |
380 | * @dma_rx: DMA receive channel | |
381 | * @dummy_rx: dummy receive buffer for full-duplex devices | |
382 | * @dummy_tx: dummy transmit buffer for full-duplex devices | |
a0a90718 MW |
383 | * @fw_translate_cs: If the boot firmware uses different numbering scheme |
384 | * what Linux expects, this optional hook can be used to translate | |
385 | * between the two. | |
8ae12a0d | 386 | * |
33e34dc6 | 387 | * Each SPI master controller can communicate with one or more @spi_device |
8ae12a0d DB |
388 | * children. These make a small bus, sharing MOSI, MISO and SCK signals |
389 | * but not chip select signals. Each device may be configured to use a | |
390 | * different clock rate, since those shared signals are ignored unless | |
391 | * the chip is selected. | |
392 | * | |
393 | * The driver for an SPI controller manages access to those devices through | |
33e34dc6 DB |
394 | * a queue of spi_message transactions, copying data between CPU memory and |
395 | * an SPI slave device. For each such message it queues, it calls the | |
8ae12a0d DB |
396 | * message's completion function when the transaction completes. |
397 | */ | |
398 | struct spi_master { | |
49dce689 | 399 | struct device dev; |
8ae12a0d | 400 | |
2b9603a0 FT |
401 | struct list_head list; |
402 | ||
a020ed75 | 403 | /* other than negative (== assign one dynamically), bus_num is fully |
8ae12a0d | 404 | * board-specific. usually that simplifies to being SOC-specific. |
a020ed75 | 405 | * example: one SOC has three SPI controllers, numbered 0..2, |
8ae12a0d DB |
406 | * and one board's schematics might show it using SPI-2. software |
407 | * would normally use bus_num=2 for that controller. | |
408 | */ | |
a020ed75 | 409 | s16 bus_num; |
8ae12a0d DB |
410 | |
411 | /* chipselects will be integral to many controllers; some others | |
412 | * might use board-specific GPIOs. | |
413 | */ | |
414 | u16 num_chipselect; | |
415 | ||
fd5e191e MR |
416 | /* some SPI controllers pose alignment requirements on DMAable |
417 | * buffers; let protocol drivers know about these requirements. | |
418 | */ | |
419 | u16 dma_alignment; | |
420 | ||
e7db06b5 DB |
421 | /* spi_device.mode flags understood by this controller driver */ |
422 | u16 mode_bits; | |
423 | ||
543bb255 SW |
424 | /* bitmask of supported bits_per_word for transfers */ |
425 | u32 bits_per_word_mask; | |
2922a8de | 426 | #define SPI_BPW_MASK(bits) BIT((bits) - 1) |
b6aa23cc | 427 | #define SPI_BIT_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1)) |
eca8960a | 428 | #define SPI_BPW_RANGE_MASK(min, max) (SPI_BIT_MASK(max) - SPI_BIT_MASK(min - 1)) |
543bb255 | 429 | |
a2fd4f9f MB |
430 | /* limits on transfer speed */ |
431 | u32 min_speed_hz; | |
432 | u32 max_speed_hz; | |
433 | ||
70d6027f DB |
434 | /* other constraints relevant to this driver */ |
435 | u16 flags; | |
436 | #define SPI_MASTER_HALF_DUPLEX BIT(0) /* can't do full duplex */ | |
568d0697 DB |
437 | #define SPI_MASTER_NO_RX BIT(1) /* can't do buffer read */ |
438 | #define SPI_MASTER_NO_TX BIT(2) /* can't do buffer write */ | |
3a2eba9b MB |
439 | #define SPI_MASTER_MUST_RX BIT(3) /* requires rx */ |
440 | #define SPI_MASTER_MUST_TX BIT(4) /* requires tx */ | |
70d6027f | 441 | |
4acad4aa MS |
442 | /* |
443 | * on some hardware transfer size may be constrained | |
444 | * the limit may depend on device transfer settings | |
445 | */ | |
446 | size_t (*max_transfer_size)(struct spi_device *spi); | |
447 | ||
cf32b71e ES |
448 | /* lock and mutex for SPI bus locking */ |
449 | spinlock_t bus_lock_spinlock; | |
450 | struct mutex bus_lock_mutex; | |
451 | ||
452 | /* flag indicating that the SPI bus is locked for exclusive use */ | |
453 | bool bus_lock_flag; | |
454 | ||
6e538aaf DB |
455 | /* Setup mode and clock, etc (spi driver may call many times). |
456 | * | |
457 | * IMPORTANT: this may be called when transfers to another | |
458 | * device are active. DO NOT UPDATE SHARED REGISTERS in ways | |
459 | * which could break those transfers. | |
460 | */ | |
8ae12a0d DB |
461 | int (*setup)(struct spi_device *spi); |
462 | ||
463 | /* bidirectional bulk transfers | |
464 | * | |
465 | * + The transfer() method may not sleep; its main role is | |
466 | * just to add the message to the queue. | |
467 | * + For now there's no remove-from-queue operation, or | |
468 | * any other request management | |
469 | * + To a given spi_device, message queueing is pure fifo | |
470 | * | |
471 | * + The master's main job is to process its message queue, | |
472 | * selecting a chip then transferring data | |
473 | * + If there are multiple spi_device children, the i/o queue | |
474 | * arbitration algorithm is unspecified (round robin, fifo, | |
475 | * priority, reservations, preemption, etc) | |
476 | * | |
477 | * + Chipselect stays active during the entire message | |
478 | * (unless modified by spi_transfer.cs_change != 0). | |
479 | * + The message transfers use clock and SPI mode parameters | |
480 | * previously established by setup() for this device | |
481 | */ | |
482 | int (*transfer)(struct spi_device *spi, | |
483 | struct spi_message *mesg); | |
484 | ||
485 | /* called on release() to free memory provided by spi_master */ | |
0ffa0285 | 486 | void (*cleanup)(struct spi_device *spi); |
ffbbdd21 | 487 | |
99adef31 MB |
488 | /* |
489 | * Used to enable core support for DMA handling, if can_dma() | |
490 | * exists and returns true then the transfer will be mapped | |
491 | * prior to transfer_one() being called. The driver should | |
492 | * not modify or store xfer and dma_tx and dma_rx must be set | |
493 | * while the device is prepared. | |
494 | */ | |
495 | bool (*can_dma)(struct spi_master *master, | |
496 | struct spi_device *spi, | |
497 | struct spi_transfer *xfer); | |
498 | ||
ffbbdd21 LW |
499 | /* |
500 | * These hooks are for drivers that want to use the generic | |
501 | * master transfer queueing mechanism. If these are used, the | |
502 | * transfer() function above must NOT be specified by the driver. | |
503 | * Over time we expect SPI drivers to be phased over to this API. | |
504 | */ | |
505 | bool queued; | |
506 | struct kthread_worker kworker; | |
507 | struct task_struct *kworker_task; | |
508 | struct kthread_work pump_messages; | |
509 | spinlock_t queue_lock; | |
510 | struct list_head queue; | |
511 | struct spi_message *cur_msg; | |
0461a414 | 512 | bool idling; |
ffbbdd21 LW |
513 | bool busy; |
514 | bool running; | |
515 | bool rt; | |
49834de2 | 516 | bool auto_runtime_pm; |
2841a5fc | 517 | bool cur_msg_prepared; |
99adef31 | 518 | bool cur_msg_mapped; |
b158935f | 519 | struct completion xfer_completion; |
6ad45a27 | 520 | size_t max_dma_len; |
ffbbdd21 LW |
521 | |
522 | int (*prepare_transfer_hardware)(struct spi_master *master); | |
523 | int (*transfer_one_message)(struct spi_master *master, | |
524 | struct spi_message *mesg); | |
525 | int (*unprepare_transfer_hardware)(struct spi_master *master); | |
2841a5fc MB |
526 | int (*prepare_message)(struct spi_master *master, |
527 | struct spi_message *message); | |
528 | int (*unprepare_message)(struct spi_master *master, | |
529 | struct spi_message *message); | |
556351f1 V |
530 | int (*spi_flash_read)(struct spi_device *spi, |
531 | struct spi_flash_read_message *msg); | |
49834de2 | 532 | |
b158935f MB |
533 | /* |
534 | * These hooks are for drivers that use a generic implementation | |
535 | * of transfer_one_message() provied by the core. | |
536 | */ | |
537 | void (*set_cs)(struct spi_device *spi, bool enable); | |
538 | int (*transfer_one)(struct spi_master *master, struct spi_device *spi, | |
539 | struct spi_transfer *transfer); | |
b716c4ff AS |
540 | void (*handle_err)(struct spi_master *master, |
541 | struct spi_message *message); | |
b158935f | 542 | |
74317984 JCPV |
543 | /* gpio chip select */ |
544 | int *cs_gpios; | |
99adef31 | 545 | |
eca2ebc7 MS |
546 | /* statistics */ |
547 | struct spi_statistics statistics; | |
548 | ||
99adef31 MB |
549 | /* DMA channels for use with core dmaengine helpers */ |
550 | struct dma_chan *dma_tx; | |
551 | struct dma_chan *dma_rx; | |
3a2eba9b MB |
552 | |
553 | /* dummy data for full duplex devices */ | |
554 | void *dummy_rx; | |
555 | void *dummy_tx; | |
a0a90718 MW |
556 | |
557 | int (*fw_translate_cs)(struct spi_master *master, unsigned cs); | |
8ae12a0d DB |
558 | }; |
559 | ||
0c868461 DB |
560 | static inline void *spi_master_get_devdata(struct spi_master *master) |
561 | { | |
49dce689 | 562 | return dev_get_drvdata(&master->dev); |
0c868461 DB |
563 | } |
564 | ||
565 | static inline void spi_master_set_devdata(struct spi_master *master, void *data) | |
566 | { | |
49dce689 | 567 | dev_set_drvdata(&master->dev, data); |
0c868461 DB |
568 | } |
569 | ||
570 | static inline struct spi_master *spi_master_get(struct spi_master *master) | |
571 | { | |
49dce689 | 572 | if (!master || !get_device(&master->dev)) |
0c868461 DB |
573 | return NULL; |
574 | return master; | |
575 | } | |
576 | ||
577 | static inline void spi_master_put(struct spi_master *master) | |
578 | { | |
579 | if (master) | |
49dce689 | 580 | put_device(&master->dev); |
0c868461 DB |
581 | } |
582 | ||
ffbbdd21 LW |
583 | /* PM calls that need to be issued by the driver */ |
584 | extern int spi_master_suspend(struct spi_master *master); | |
585 | extern int spi_master_resume(struct spi_master *master); | |
586 | ||
587 | /* Calls the driver make to interact with the message queue */ | |
588 | extern struct spi_message *spi_get_next_queued_message(struct spi_master *master); | |
589 | extern void spi_finalize_current_message(struct spi_master *master); | |
b158935f | 590 | extern void spi_finalize_current_transfer(struct spi_master *master); |
0c868461 | 591 | |
8ae12a0d DB |
592 | /* the spi driver core manages memory for the spi_master classdev */ |
593 | extern struct spi_master * | |
594 | spi_alloc_master(struct device *host, unsigned size); | |
595 | ||
596 | extern int spi_register_master(struct spi_master *master); | |
666d5b4c MB |
597 | extern int devm_spi_register_master(struct device *dev, |
598 | struct spi_master *master); | |
8ae12a0d DB |
599 | extern void spi_unregister_master(struct spi_master *master); |
600 | ||
601 | extern struct spi_master *spi_busnum_to_master(u16 busnum); | |
602 | ||
d780c371 MS |
603 | /* |
604 | * SPI resource management while processing a SPI message | |
605 | */ | |
606 | ||
d6497816 MS |
607 | typedef void (*spi_res_release_t)(struct spi_master *master, |
608 | struct spi_message *msg, | |
609 | void *res); | |
610 | ||
d780c371 MS |
611 | /** |
612 | * struct spi_res - spi resource management structure | |
613 | * @entry: list entry | |
614 | * @release: release code called prior to freeing this resource | |
615 | * @data: extra data allocated for the specific use-case | |
616 | * | |
617 | * this is based on ideas from devres, but focused on life-cycle | |
618 | * management during spi_message processing | |
619 | */ | |
d780c371 MS |
620 | struct spi_res { |
621 | struct list_head entry; | |
622 | spi_res_release_t release; | |
623 | unsigned long long data[]; /* guarantee ull alignment */ | |
624 | }; | |
625 | ||
626 | extern void *spi_res_alloc(struct spi_device *spi, | |
627 | spi_res_release_t release, | |
628 | size_t size, gfp_t gfp); | |
629 | extern void spi_res_add(struct spi_message *message, void *res); | |
630 | extern void spi_res_free(void *res); | |
631 | ||
632 | extern void spi_res_release(struct spi_master *master, | |
633 | struct spi_message *message); | |
634 | ||
8ae12a0d DB |
635 | /*---------------------------------------------------------------------------*/ |
636 | ||
637 | /* | |
638 | * I/O INTERFACE between SPI controller and protocol drivers | |
639 | * | |
640 | * Protocol drivers use a queue of spi_messages, each transferring data | |
641 | * between the controller and memory buffers. | |
642 | * | |
643 | * The spi_messages themselves consist of a series of read+write transfer | |
644 | * segments. Those segments always read the same number of bits as they | |
645 | * write; but one or the other is easily ignored by passing a null buffer | |
646 | * pointer. (This is unlike most types of I/O API, because SPI hardware | |
647 | * is full duplex.) | |
648 | * | |
649 | * NOTE: Allocation of spi_transfer and spi_message memory is entirely | |
650 | * up to the protocol driver, which guarantees the integrity of both (as | |
651 | * well as the data buffers) for as long as the message is queued. | |
652 | */ | |
653 | ||
654 | /** | |
655 | * struct spi_transfer - a read/write buffer pair | |
8275c642 VW |
656 | * @tx_buf: data to be written (dma-safe memory), or NULL |
657 | * @rx_buf: data to be read (dma-safe memory), or NULL | |
33e34dc6 DB |
658 | * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped |
659 | * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped | |
e227867f | 660 | * @tx_nbits: number of bits used for writing. If 0 the default |
f477b7fb | 661 | * (SPI_NBITS_SINGLE) is used. |
662 | * @rx_nbits: number of bits used for reading. If 0 the default | |
663 | * (SPI_NBITS_SINGLE) is used. | |
8ae12a0d | 664 | * @len: size of rx and tx buffers (in bytes) |
025dfdaf | 665 | * @speed_hz: Select a speed other than the device default for this |
33e34dc6 | 666 | * transfer. If 0 the default (from @spi_device) is used. |
025dfdaf | 667 | * @bits_per_word: select a bits_per_word other than the device default |
33e34dc6 | 668 | * for this transfer. If 0 the default (from @spi_device) is used. |
8ae12a0d DB |
669 | * @cs_change: affects chipselect after this transfer completes |
670 | * @delay_usecs: microseconds to delay after this transfer before | |
747d844e | 671 | * (optionally) changing the chipselect status, then starting |
33e34dc6 DB |
672 | * the next transfer or completing this @spi_message. |
673 | * @transfer_list: transfers are sequenced through @spi_message.transfers | |
6ad45a27 MB |
674 | * @tx_sg: Scatterlist for transmit, currently not for client use |
675 | * @rx_sg: Scatterlist for receive, currently not for client use | |
8ae12a0d DB |
676 | * |
677 | * SPI transfers always write the same number of bytes as they read. | |
33e34dc6 | 678 | * Protocol drivers should always provide @rx_buf and/or @tx_buf. |
8ae12a0d DB |
679 | * In some cases, they may also want to provide DMA addresses for |
680 | * the data being transferred; that may reduce overhead, when the | |
681 | * underlying driver uses dma. | |
682 | * | |
4b1badf5 | 683 | * If the transmit buffer is null, zeroes will be shifted out |
33e34dc6 | 684 | * while filling @rx_buf. If the receive buffer is null, the data |
8275c642 VW |
685 | * shifted in will be discarded. Only "len" bytes shift out (or in). |
686 | * It's an error to try to shift out a partial word. (For example, by | |
687 | * shifting out three bytes with word size of sixteen or twenty bits; | |
688 | * the former uses two bytes per word, the latter uses four bytes.) | |
689 | * | |
80224561 DB |
690 | * In-memory data values are always in native CPU byte order, translated |
691 | * from the wire byte order (big-endian except with SPI_LSB_FIRST). So | |
692 | * for example when bits_per_word is sixteen, buffers are 2N bytes long | |
33e34dc6 | 693 | * (@len = 2N) and hold N sixteen bit words in CPU byte order. |
80224561 DB |
694 | * |
695 | * When the word size of the SPI transfer is not a power-of-two multiple | |
696 | * of eight bits, those in-memory words include extra bits. In-memory | |
697 | * words are always seen by protocol drivers as right-justified, so the | |
698 | * undefined (rx) or unused (tx) bits are always the most significant bits. | |
699 | * | |
8275c642 VW |
700 | * All SPI transfers start with the relevant chipselect active. Normally |
701 | * it stays selected until after the last transfer in a message. Drivers | |
33e34dc6 | 702 | * can affect the chipselect signal using cs_change. |
8ae12a0d DB |
703 | * |
704 | * (i) If the transfer isn't the last one in the message, this flag is | |
705 | * used to make the chipselect briefly go inactive in the middle of the | |
706 | * message. Toggling chipselect in this way may be needed to terminate | |
707 | * a chip command, letting a single spi_message perform all of group of | |
708 | * chip transactions together. | |
709 | * | |
710 | * (ii) When the transfer is the last one in the message, the chip may | |
f5a9c77d DB |
711 | * stay selected until the next transfer. On multi-device SPI busses |
712 | * with nothing blocking messages going to other devices, this is just | |
713 | * a performance hint; starting a message to another device deselects | |
714 | * this one. But in other cases, this can be used to ensure correctness. | |
715 | * Some devices need protocol transactions to be built from a series of | |
716 | * spi_message submissions, where the content of one message is determined | |
717 | * by the results of previous messages and where the whole transaction | |
718 | * ends when the chipselect goes intactive. | |
0c868461 | 719 | * |
e227867f | 720 | * When SPI can transfer in 1x,2x or 4x. It can get this transfer information |
f477b7fb | 721 | * from device through @tx_nbits and @rx_nbits. In Bi-direction, these |
722 | * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x) | |
723 | * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer. | |
724 | * | |
0c868461 DB |
725 | * The code that submits an spi_message (and its spi_transfers) |
726 | * to the lower layers is responsible for managing its memory. | |
727 | * Zero-initialize every field you don't set up explicitly, to | |
8275c642 VW |
728 | * insulate against future API updates. After you submit a message |
729 | * and its transfers, ignore them until its completion callback. | |
8ae12a0d DB |
730 | */ |
731 | struct spi_transfer { | |
732 | /* it's ok if tx_buf == rx_buf (right?) | |
733 | * for MicroWire, one buffer must be null | |
0c868461 DB |
734 | * buffers must work with dma_*map_single() calls, unless |
735 | * spi_message.is_dma_mapped reports a pre-existing mapping | |
8ae12a0d DB |
736 | */ |
737 | const void *tx_buf; | |
738 | void *rx_buf; | |
739 | unsigned len; | |
740 | ||
741 | dma_addr_t tx_dma; | |
742 | dma_addr_t rx_dma; | |
6ad45a27 MB |
743 | struct sg_table tx_sg; |
744 | struct sg_table rx_sg; | |
8ae12a0d DB |
745 | |
746 | unsigned cs_change:1; | |
d3fbd457 MB |
747 | unsigned tx_nbits:3; |
748 | unsigned rx_nbits:3; | |
f477b7fb | 749 | #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */ |
750 | #define SPI_NBITS_DUAL 0x02 /* 2bits transfer */ | |
751 | #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */ | |
4cff33f9 | 752 | u8 bits_per_word; |
8ae12a0d | 753 | u16 delay_usecs; |
4cff33f9 | 754 | u32 speed_hz; |
8275c642 VW |
755 | |
756 | struct list_head transfer_list; | |
8ae12a0d DB |
757 | }; |
758 | ||
759 | /** | |
760 | * struct spi_message - one multi-segment SPI transaction | |
8275c642 | 761 | * @transfers: list of transfer segments in this transaction |
8ae12a0d DB |
762 | * @spi: SPI device to which the transaction is queued |
763 | * @is_dma_mapped: if true, the caller provided both dma and cpu virtual | |
764 | * addresses for each transfer buffer | |
765 | * @complete: called to report transaction completions | |
766 | * @context: the argument to complete() when it's called | |
2c675689 | 767 | * @frame_length: the total number of bytes in the message |
b885244e DB |
768 | * @actual_length: the total number of bytes that were transferred in all |
769 | * successful segments | |
8ae12a0d DB |
770 | * @status: zero for success, else negative errno |
771 | * @queue: for use by whichever driver currently owns the message | |
772 | * @state: for use by whichever driver currently owns the message | |
d780c371 | 773 | * @resources: for resource management when the spi message is processed |
0c868461 | 774 | * |
33e34dc6 | 775 | * A @spi_message is used to execute an atomic sequence of data transfers, |
8275c642 VW |
776 | * each represented by a struct spi_transfer. The sequence is "atomic" |
777 | * in the sense that no other spi_message may use that SPI bus until that | |
778 | * sequence completes. On some systems, many such sequences can execute as | |
779 | * as single programmed DMA transfer. On all systems, these messages are | |
780 | * queued, and might complete after transactions to other devices. Messages | |
c6331ba3 | 781 | * sent to a given spi_device are always executed in FIFO order. |
8275c642 | 782 | * |
0c868461 DB |
783 | * The code that submits an spi_message (and its spi_transfers) |
784 | * to the lower layers is responsible for managing its memory. | |
785 | * Zero-initialize every field you don't set up explicitly, to | |
8275c642 VW |
786 | * insulate against future API updates. After you submit a message |
787 | * and its transfers, ignore them until its completion callback. | |
8ae12a0d DB |
788 | */ |
789 | struct spi_message { | |
747d844e | 790 | struct list_head transfers; |
8ae12a0d DB |
791 | |
792 | struct spi_device *spi; | |
793 | ||
794 | unsigned is_dma_mapped:1; | |
795 | ||
796 | /* REVISIT: we might want a flag affecting the behavior of the | |
797 | * last transfer ... allowing things like "read 16 bit length L" | |
798 | * immediately followed by "read L bytes". Basically imposing | |
799 | * a specific message scheduling algorithm. | |
800 | * | |
801 | * Some controller drivers (message-at-a-time queue processing) | |
802 | * could provide that as their default scheduling algorithm. But | |
b885244e | 803 | * others (with multi-message pipelines) could need a flag to |
8ae12a0d DB |
804 | * tell them about such special cases. |
805 | */ | |
806 | ||
807 | /* completion is reported through a callback */ | |
747d844e | 808 | void (*complete)(void *context); |
8ae12a0d | 809 | void *context; |
078726ce | 810 | unsigned frame_length; |
8ae12a0d DB |
811 | unsigned actual_length; |
812 | int status; | |
813 | ||
814 | /* for optional use by whatever driver currently owns the | |
815 | * spi_message ... between calls to spi_async and then later | |
816 | * complete(), that's the spi_master controller driver. | |
817 | */ | |
818 | struct list_head queue; | |
819 | void *state; | |
d780c371 MS |
820 | |
821 | /* list of spi_res reources when the spi message is processed */ | |
822 | struct list_head resources; | |
8ae12a0d DB |
823 | }; |
824 | ||
49ddedf3 MS |
825 | static inline void spi_message_init_no_memset(struct spi_message *m) |
826 | { | |
827 | INIT_LIST_HEAD(&m->transfers); | |
d780c371 | 828 | INIT_LIST_HEAD(&m->resources); |
49ddedf3 MS |
829 | } |
830 | ||
8275c642 VW |
831 | static inline void spi_message_init(struct spi_message *m) |
832 | { | |
833 | memset(m, 0, sizeof *m); | |
49ddedf3 | 834 | spi_message_init_no_memset(m); |
8275c642 VW |
835 | } |
836 | ||
837 | static inline void | |
838 | spi_message_add_tail(struct spi_transfer *t, struct spi_message *m) | |
839 | { | |
840 | list_add_tail(&t->transfer_list, &m->transfers); | |
841 | } | |
842 | ||
843 | static inline void | |
844 | spi_transfer_del(struct spi_transfer *t) | |
845 | { | |
846 | list_del(&t->transfer_list); | |
847 | } | |
848 | ||
6d9eecd4 LPC |
849 | /** |
850 | * spi_message_init_with_transfers - Initialize spi_message and append transfers | |
851 | * @m: spi_message to be initialized | |
852 | * @xfers: An array of spi transfers | |
853 | * @num_xfers: Number of items in the xfer array | |
854 | * | |
855 | * This function initializes the given spi_message and adds each spi_transfer in | |
856 | * the given array to the message. | |
857 | */ | |
858 | static inline void | |
859 | spi_message_init_with_transfers(struct spi_message *m, | |
860 | struct spi_transfer *xfers, unsigned int num_xfers) | |
861 | { | |
862 | unsigned int i; | |
863 | ||
864 | spi_message_init(m); | |
865 | for (i = 0; i < num_xfers; ++i) | |
866 | spi_message_add_tail(&xfers[i], m); | |
867 | } | |
868 | ||
0c868461 DB |
869 | /* It's fine to embed message and transaction structures in other data |
870 | * structures so long as you don't free them while they're in use. | |
871 | */ | |
872 | ||
873 | static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags) | |
874 | { | |
875 | struct spi_message *m; | |
876 | ||
877 | m = kzalloc(sizeof(struct spi_message) | |
878 | + ntrans * sizeof(struct spi_transfer), | |
879 | flags); | |
880 | if (m) { | |
8f53602b | 881 | unsigned i; |
8275c642 VW |
882 | struct spi_transfer *t = (struct spi_transfer *)(m + 1); |
883 | ||
884 | INIT_LIST_HEAD(&m->transfers); | |
885 | for (i = 0; i < ntrans; i++, t++) | |
886 | spi_message_add_tail(t, m); | |
0c868461 DB |
887 | } |
888 | return m; | |
889 | } | |
890 | ||
891 | static inline void spi_message_free(struct spi_message *m) | |
892 | { | |
893 | kfree(m); | |
894 | } | |
895 | ||
7d077197 | 896 | extern int spi_setup(struct spi_device *spi); |
568d0697 | 897 | extern int spi_async(struct spi_device *spi, struct spi_message *message); |
cf32b71e ES |
898 | extern int spi_async_locked(struct spi_device *spi, |
899 | struct spi_message *message); | |
8ae12a0d | 900 | |
4acad4aa MS |
901 | static inline size_t |
902 | spi_max_transfer_size(struct spi_device *spi) | |
903 | { | |
904 | struct spi_master *master = spi->master; | |
905 | if (!master->max_transfer_size) | |
906 | return SIZE_MAX; | |
907 | return master->max_transfer_size(spi); | |
908 | } | |
909 | ||
8ae12a0d DB |
910 | /*---------------------------------------------------------------------------*/ |
911 | ||
523baf5a MS |
912 | /* SPI transfer replacement methods which make use of spi_res */ |
913 | ||
c76d9ae4 JMC |
914 | struct spi_replaced_transfers; |
915 | typedef void (*spi_replaced_release_t)(struct spi_master *master, | |
916 | struct spi_message *msg, | |
917 | struct spi_replaced_transfers *res); | |
523baf5a MS |
918 | /** |
919 | * struct spi_replaced_transfers - structure describing the spi_transfer | |
920 | * replacements that have occurred | |
921 | * so that they can get reverted | |
922 | * @release: some extra release code to get executed prior to | |
923 | * relasing this structure | |
924 | * @extradata: pointer to some extra data if requested or NULL | |
925 | * @replaced_transfers: transfers that have been replaced and which need | |
926 | * to get restored | |
927 | * @replaced_after: the transfer after which the @replaced_transfers | |
928 | * are to get re-inserted | |
929 | * @inserted: number of transfers inserted | |
930 | * @inserted_transfers: array of spi_transfers of array-size @inserted, | |
931 | * that have been replacing replaced_transfers | |
932 | * | |
933 | * note: that @extradata will point to @inserted_transfers[@inserted] | |
934 | * if some extra allocation is requested, so alignment will be the same | |
935 | * as for spi_transfers | |
936 | */ | |
523baf5a MS |
937 | struct spi_replaced_transfers { |
938 | spi_replaced_release_t release; | |
939 | void *extradata; | |
940 | struct list_head replaced_transfers; | |
941 | struct list_head *replaced_after; | |
942 | size_t inserted; | |
943 | struct spi_transfer inserted_transfers[]; | |
944 | }; | |
945 | ||
946 | extern struct spi_replaced_transfers *spi_replace_transfers( | |
947 | struct spi_message *msg, | |
948 | struct spi_transfer *xfer_first, | |
949 | size_t remove, | |
950 | size_t insert, | |
951 | spi_replaced_release_t release, | |
952 | size_t extradatasize, | |
953 | gfp_t gfp); | |
954 | ||
955 | /*---------------------------------------------------------------------------*/ | |
956 | ||
d9f12122 MS |
957 | /* SPI transfer transformation methods */ |
958 | ||
959 | extern int spi_split_transfers_maxsize(struct spi_master *master, | |
960 | struct spi_message *msg, | |
961 | size_t maxsize, | |
962 | gfp_t gfp); | |
963 | ||
964 | /*---------------------------------------------------------------------------*/ | |
965 | ||
8ae12a0d DB |
966 | /* All these synchronous SPI transfer routines are utilities layered |
967 | * over the core async transfer primitive. Here, "synchronous" means | |
968 | * they will sleep uninterruptibly until the async transfer completes. | |
969 | */ | |
970 | ||
971 | extern int spi_sync(struct spi_device *spi, struct spi_message *message); | |
cf32b71e ES |
972 | extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message); |
973 | extern int spi_bus_lock(struct spi_master *master); | |
974 | extern int spi_bus_unlock(struct spi_master *master); | |
8ae12a0d DB |
975 | |
976 | /** | |
977 | * spi_write - SPI synchronous write | |
978 | * @spi: device to which data will be written | |
979 | * @buf: data buffer | |
980 | * @len: data buffer size | |
33e34dc6 | 981 | * Context: can sleep |
8ae12a0d | 982 | * |
a1fdeaa7 | 983 | * This function writes the buffer @buf. |
8ae12a0d | 984 | * Callable only from contexts that can sleep. |
a1fdeaa7 JMC |
985 | * |
986 | * Return: zero on success, else a negative error code. | |
8ae12a0d DB |
987 | */ |
988 | static inline int | |
0c4a1590 | 989 | spi_write(struct spi_device *spi, const void *buf, size_t len) |
8ae12a0d DB |
990 | { |
991 | struct spi_transfer t = { | |
992 | .tx_buf = buf, | |
8ae12a0d | 993 | .len = len, |
8ae12a0d | 994 | }; |
8275c642 | 995 | struct spi_message m; |
8ae12a0d | 996 | |
8275c642 VW |
997 | spi_message_init(&m); |
998 | spi_message_add_tail(&t, &m); | |
8ae12a0d DB |
999 | return spi_sync(spi, &m); |
1000 | } | |
1001 | ||
1002 | /** | |
1003 | * spi_read - SPI synchronous read | |
1004 | * @spi: device from which data will be read | |
1005 | * @buf: data buffer | |
1006 | * @len: data buffer size | |
33e34dc6 | 1007 | * Context: can sleep |
8ae12a0d | 1008 | * |
a1fdeaa7 | 1009 | * This function reads the buffer @buf. |
8ae12a0d | 1010 | * Callable only from contexts that can sleep. |
a1fdeaa7 JMC |
1011 | * |
1012 | * Return: zero on success, else a negative error code. | |
8ae12a0d DB |
1013 | */ |
1014 | static inline int | |
0c4a1590 | 1015 | spi_read(struct spi_device *spi, void *buf, size_t len) |
8ae12a0d DB |
1016 | { |
1017 | struct spi_transfer t = { | |
8ae12a0d DB |
1018 | .rx_buf = buf, |
1019 | .len = len, | |
8ae12a0d | 1020 | }; |
8275c642 | 1021 | struct spi_message m; |
8ae12a0d | 1022 | |
8275c642 VW |
1023 | spi_message_init(&m); |
1024 | spi_message_add_tail(&t, &m); | |
8ae12a0d DB |
1025 | return spi_sync(spi, &m); |
1026 | } | |
1027 | ||
6d9eecd4 LPC |
1028 | /** |
1029 | * spi_sync_transfer - synchronous SPI data transfer | |
1030 | * @spi: device with which data will be exchanged | |
1031 | * @xfers: An array of spi_transfers | |
1032 | * @num_xfers: Number of items in the xfer array | |
1033 | * Context: can sleep | |
1034 | * | |
1035 | * Does a synchronous SPI data transfer of the given spi_transfer array. | |
1036 | * | |
1037 | * For more specific semantics see spi_sync(). | |
1038 | * | |
a1fdeaa7 | 1039 | * Return: Return: zero on success, else a negative error code. |
6d9eecd4 LPC |
1040 | */ |
1041 | static inline int | |
1042 | spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers, | |
1043 | unsigned int num_xfers) | |
1044 | { | |
1045 | struct spi_message msg; | |
1046 | ||
1047 | spi_message_init_with_transfers(&msg, xfers, num_xfers); | |
1048 | ||
1049 | return spi_sync(spi, &msg); | |
1050 | } | |
1051 | ||
0c868461 | 1052 | /* this copies txbuf and rxbuf data; for small transfers only! */ |
8ae12a0d | 1053 | extern int spi_write_then_read(struct spi_device *spi, |
0c4a1590 MB |
1054 | const void *txbuf, unsigned n_tx, |
1055 | void *rxbuf, unsigned n_rx); | |
8ae12a0d DB |
1056 | |
1057 | /** | |
1058 | * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read | |
1059 | * @spi: device with which data will be exchanged | |
1060 | * @cmd: command to be written before data is read back | |
33e34dc6 | 1061 | * Context: can sleep |
8ae12a0d | 1062 | * |
a1fdeaa7 JMC |
1063 | * Callable only from contexts that can sleep. |
1064 | * | |
1065 | * Return: the (unsigned) eight bit number returned by the | |
1066 | * device, or else a negative error code. | |
8ae12a0d DB |
1067 | */ |
1068 | static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd) | |
1069 | { | |
1070 | ssize_t status; | |
1071 | u8 result; | |
1072 | ||
1073 | status = spi_write_then_read(spi, &cmd, 1, &result, 1); | |
1074 | ||
1075 | /* return negative errno or unsigned value */ | |
1076 | return (status < 0) ? status : result; | |
1077 | } | |
1078 | ||
1079 | /** | |
1080 | * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read | |
1081 | * @spi: device with which data will be exchanged | |
1082 | * @cmd: command to be written before data is read back | |
33e34dc6 | 1083 | * Context: can sleep |
8ae12a0d | 1084 | * |
8ae12a0d DB |
1085 | * The number is returned in wire-order, which is at least sometimes |
1086 | * big-endian. | |
a1fdeaa7 JMC |
1087 | * |
1088 | * Callable only from contexts that can sleep. | |
1089 | * | |
1090 | * Return: the (unsigned) sixteen bit number returned by the | |
1091 | * device, or else a negative error code. | |
8ae12a0d DB |
1092 | */ |
1093 | static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd) | |
1094 | { | |
1095 | ssize_t status; | |
1096 | u16 result; | |
1097 | ||
269ccca8 | 1098 | status = spi_write_then_read(spi, &cmd, 1, &result, 2); |
8ae12a0d DB |
1099 | |
1100 | /* return negative errno or unsigned value */ | |
1101 | return (status < 0) ? status : result; | |
1102 | } | |
1103 | ||
05071aa8 LPC |
1104 | /** |
1105 | * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read | |
1106 | * @spi: device with which data will be exchanged | |
1107 | * @cmd: command to be written before data is read back | |
1108 | * Context: can sleep | |
1109 | * | |
05071aa8 LPC |
1110 | * This function is similar to spi_w8r16, with the exception that it will |
1111 | * convert the read 16 bit data word from big-endian to native endianness. | |
1112 | * | |
a1fdeaa7 JMC |
1113 | * Callable only from contexts that can sleep. |
1114 | * | |
1115 | * Return: the (unsigned) sixteen bit number returned by the device in cpu | |
1116 | * endianness, or else a negative error code. | |
05071aa8 LPC |
1117 | */ |
1118 | static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd) | |
1119 | ||
1120 | { | |
1121 | ssize_t status; | |
1122 | __be16 result; | |
1123 | ||
1124 | status = spi_write_then_read(spi, &cmd, 1, &result, 2); | |
1125 | if (status < 0) | |
1126 | return status; | |
1127 | ||
1128 | return be16_to_cpu(result); | |
1129 | } | |
1130 | ||
556351f1 V |
1131 | /** |
1132 | * struct spi_flash_read_message - flash specific information for | |
1133 | * spi-masters that provide accelerated flash read interfaces | |
1134 | * @buf: buffer to read data | |
1135 | * @from: offset within the flash from where data is to be read | |
1136 | * @len: length of data to be read | |
1137 | * @retlen: actual length of data read | |
1138 | * @read_opcode: read_opcode to be used to communicate with flash | |
1139 | * @addr_width: number of address bytes | |
1140 | * @dummy_bytes: number of dummy bytes | |
1141 | * @opcode_nbits: number of lines to send opcode | |
1142 | * @addr_nbits: number of lines to send address | |
1143 | * @data_nbits: number of lines for data | |
1144 | */ | |
1145 | struct spi_flash_read_message { | |
1146 | void *buf; | |
1147 | loff_t from; | |
1148 | size_t len; | |
1149 | size_t retlen; | |
1150 | u8 read_opcode; | |
1151 | u8 addr_width; | |
1152 | u8 dummy_bytes; | |
1153 | u8 opcode_nbits; | |
1154 | u8 addr_nbits; | |
1155 | u8 data_nbits; | |
1156 | }; | |
1157 | ||
1158 | /* SPI core interface for flash read support */ | |
1159 | static inline bool spi_flash_read_supported(struct spi_device *spi) | |
1160 | { | |
1161 | return spi->master->spi_flash_read ? true : false; | |
1162 | } | |
1163 | ||
1164 | int spi_flash_read(struct spi_device *spi, | |
1165 | struct spi_flash_read_message *msg); | |
1166 | ||
8ae12a0d DB |
1167 | /*---------------------------------------------------------------------------*/ |
1168 | ||
1169 | /* | |
1170 | * INTERFACE between board init code and SPI infrastructure. | |
1171 | * | |
1172 | * No SPI driver ever sees these SPI device table segments, but | |
1173 | * it's how the SPI core (or adapters that get hotplugged) grows | |
1174 | * the driver model tree. | |
1175 | * | |
1176 | * As a rule, SPI devices can't be probed. Instead, board init code | |
1177 | * provides a table listing the devices which are present, with enough | |
1178 | * information to bind and set up the device's driver. There's basic | |
1179 | * support for nonstatic configurations too; enough to handle adding | |
1180 | * parport adapters, or microcontrollers acting as USB-to-SPI bridges. | |
1181 | */ | |
1182 | ||
2604288f DB |
1183 | /** |
1184 | * struct spi_board_info - board-specific template for a SPI device | |
1185 | * @modalias: Initializes spi_device.modalias; identifies the driver. | |
1186 | * @platform_data: Initializes spi_device.platform_data; the particular | |
1187 | * data stored there is driver-specific. | |
1188 | * @controller_data: Initializes spi_device.controller_data; some | |
1189 | * controllers need hints about hardware setup, e.g. for DMA. | |
1190 | * @irq: Initializes spi_device.irq; depends on how the board is wired. | |
1191 | * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits | |
1192 | * from the chip datasheet and board-specific signal quality issues. | |
1193 | * @bus_num: Identifies which spi_master parents the spi_device; unused | |
1194 | * by spi_new_device(), and otherwise depends on board wiring. | |
1195 | * @chip_select: Initializes spi_device.chip_select; depends on how | |
1196 | * the board is wired. | |
1197 | * @mode: Initializes spi_device.mode; based on the chip datasheet, board | |
1198 | * wiring (some devices support both 3WIRE and standard modes), and | |
1199 | * possibly presence of an inverter in the chipselect path. | |
1200 | * | |
1201 | * When adding new SPI devices to the device tree, these structures serve | |
1202 | * as a partial device template. They hold information which can't always | |
1203 | * be determined by drivers. Information that probe() can establish (such | |
1204 | * as the default transfer wordsize) is not included here. | |
1205 | * | |
1206 | * These structures are used in two places. Their primary role is to | |
1207 | * be stored in tables of board-specific device descriptors, which are | |
1208 | * declared early in board initialization and then used (much later) to | |
1209 | * populate a controller's device tree after the that controller's driver | |
1210 | * initializes. A secondary (and atypical) role is as a parameter to | |
1211 | * spi_new_device() call, which happens after those controller drivers | |
1212 | * are active in some dynamic board configuration models. | |
1213 | */ | |
8ae12a0d DB |
1214 | struct spi_board_info { |
1215 | /* the device name and module name are coupled, like platform_bus; | |
1216 | * "modalias" is normally the driver name. | |
1217 | * | |
1218 | * platform_data goes to spi_device.dev.platform_data, | |
b885244e | 1219 | * controller_data goes to spi_device.controller_data, |
8ae12a0d DB |
1220 | * irq is copied too |
1221 | */ | |
75368bf6 | 1222 | char modalias[SPI_NAME_SIZE]; |
8ae12a0d | 1223 | const void *platform_data; |
b885244e | 1224 | void *controller_data; |
8ae12a0d DB |
1225 | int irq; |
1226 | ||
1227 | /* slower signaling on noisy or low voltage boards */ | |
1228 | u32 max_speed_hz; | |
1229 | ||
1230 | ||
1231 | /* bus_num is board specific and matches the bus_num of some | |
1232 | * spi_master that will probably be registered later. | |
1233 | * | |
1234 | * chip_select reflects how this chip is wired to that master; | |
1235 | * it's less than num_chipselect. | |
1236 | */ | |
1237 | u16 bus_num; | |
1238 | u16 chip_select; | |
1239 | ||
980a01c9 DB |
1240 | /* mode becomes spi_device.mode, and is essential for chips |
1241 | * where the default of SPI_CS_HIGH = 0 is wrong. | |
1242 | */ | |
f477b7fb | 1243 | u16 mode; |
980a01c9 | 1244 | |
8ae12a0d DB |
1245 | /* ... may need additional spi_device chip config data here. |
1246 | * avoid stuff protocol drivers can set; but include stuff | |
1247 | * needed to behave without being bound to a driver: | |
8ae12a0d DB |
1248 | * - quirks like clock rate mattering when not selected |
1249 | */ | |
1250 | }; | |
1251 | ||
1252 | #ifdef CONFIG_SPI | |
1253 | extern int | |
1254 | spi_register_board_info(struct spi_board_info const *info, unsigned n); | |
1255 | #else | |
1256 | /* board init code may ignore whether SPI is configured or not */ | |
1257 | static inline int | |
1258 | spi_register_board_info(struct spi_board_info const *info, unsigned n) | |
1259 | { return 0; } | |
1260 | #endif | |
1261 | ||
1262 | ||
1263 | /* If you're hotplugging an adapter with devices (parport, usb, etc) | |
0c868461 DB |
1264 | * use spi_new_device() to describe each device. You can also call |
1265 | * spi_unregister_device() to start making that device vanish, but | |
1266 | * normally that would be handled by spi_unregister_master(). | |
dc87c98e GL |
1267 | * |
1268 | * You can also use spi_alloc_device() and spi_add_device() to use a two | |
1269 | * stage registration sequence for each spi_device. This gives the caller | |
1270 | * some more control over the spi_device structure before it is registered, | |
1271 | * but requires that caller to initialize fields that would otherwise | |
1272 | * be defined using the board info. | |
8ae12a0d | 1273 | */ |
dc87c98e GL |
1274 | extern struct spi_device * |
1275 | spi_alloc_device(struct spi_master *master); | |
1276 | ||
1277 | extern int | |
1278 | spi_add_device(struct spi_device *spi); | |
1279 | ||
8ae12a0d DB |
1280 | extern struct spi_device * |
1281 | spi_new_device(struct spi_master *, struct spi_board_info *); | |
1282 | ||
3b1884c2 | 1283 | extern void spi_unregister_device(struct spi_device *spi); |
8ae12a0d | 1284 | |
75368bf6 AV |
1285 | extern const struct spi_device_id * |
1286 | spi_get_device_id(const struct spi_device *sdev); | |
1287 | ||
b671358a BG |
1288 | static inline bool |
1289 | spi_transfer_is_last(struct spi_master *master, struct spi_transfer *xfer) | |
1290 | { | |
1291 | return list_is_last(&xfer->transfer_list, &master->cur_msg->transfers); | |
1292 | } | |
1293 | ||
8ae12a0d | 1294 | #endif /* __LINUX_SPI_H */ |