[deliverable/linux.git] / include / linux / usb / tegra_usb_phy.h

/*
 * Copyright (C) 2010 Google, Inc.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#ifndef __TEGRA_USB_PHY_H
#define __TEGRA_USB_PHY_H

#include <linux/clk.h>
#include <linux/usb/otg.h>

/*
 * utmi_pll_config_in_car_module: true if the UTMI PLL configuration registers
 *     should be set up by clk-tegra, false if by the PHY code
 * has_hostpc: true if the USB controller has the HOSTPC extension, which
 *     changes the location of the PHCD and PTS fields
 * requires_usbmode_setup: true if the USBMODE register needs to be set to
 *      enter host mode
 * requires_extra_tuning_parameters: true if xcvr_hsslew, hssquelch_level
 *      and hsdiscon_level should be set for adequate signal quality
 */

struct tegra_phy_soc_config {
	bool utmi_pll_config_in_car_module;
	bool has_hostpc;
	bool requires_usbmode_setup;
	bool requires_extra_tuning_parameters;
};

struct tegra_utmip_config {
	u8 hssync_start_delay;
	u8 elastic_limit;
	u8 idle_wait_delay;
	u8 term_range_adj;
	bool xcvr_setup_use_fuses;
	u8 xcvr_setup;
	u8 xcvr_lsfslew;
	u8 xcvr_lsrslew;
	u8 xcvr_hsslew;
	u8 hssquelch_level;
	u8 hsdiscon_level;
};

enum tegra_usb_phy_port_speed {
	TEGRA_USB_PHY_PORT_SPEED_FULL = 0,
	TEGRA_USB_PHY_PORT_SPEED_LOW,
	TEGRA_USB_PHY_PORT_SPEED_HIGH,
};

struct tegra_xtal_freq;

struct tegra_usb_phy {
	int instance;
	const struct tegra_xtal_freq *freq;
	void __iomem *regs;
	void __iomem *pad_regs;
	struct clk *clk;
	struct clk *pll_u;
	struct clk *pad_clk;
	struct regulator *vbus;
	enum usb_dr_mode mode;
	void *config;
	const struct tegra_phy_soc_config *soc_config;
	struct usb_phy *ulpi;
	struct usb_phy u_phy;
	bool is_legacy_phy;
	bool is_ulpi_phy;
	int reset_gpio;
};

void tegra_usb_phy_preresume(struct usb_phy *phy);

void tegra_usb_phy_postresume(struct usb_phy *phy);

void tegra_ehci_phy_restore_start(struct usb_phy *phy,
				 enum tegra_usb_phy_port_speed port_speed);

void tegra_ehci_phy_restore_end(struct usb_phy *phy);

#endif /* __TEGRA_USB_PHY_H */
Commit	Line	Data
91525d08	1	/*
91525d08 BG	2	* Copyright (C) 2010 Google, Inc.
	3	*
	4	* This software is licensed under the terms of the GNU General Public
	5	* License version 2, as published by the Free Software Foundation, and
	6	* may be copied, distributed, and modified under those terms.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	*/
	14
1ba8216f VB	15	#ifndef __TEGRA_USB_PHY_H
1ba8216f VB	16	#define __TEGRA_USB_PHY_H
91525d08 BG	17
	18	#include <linux/clk.h>
	19	#include <linux/usb/otg.h>
	20
3e635202 TT	21	/*
	22	* utmi_pll_config_in_car_module: true if the UTMI PLL configuration registers
	23	* should be set up by clk-tegra, false if by the PHY code
	24	* has_hostpc: true if the USB controller has the HOSTPC extension, which
	25	* changes the location of the PHCD and PTS fields
	26	* requires_usbmode_setup: true if the USBMODE register needs to be set to
	27	* enter host mode
	28	* requires_extra_tuning_parameters: true if xcvr_hsslew, hssquelch_level
	29	* and hsdiscon_level should be set for adequate signal quality
	30	*/
	31
	32	struct tegra_phy_soc_config {
	33	bool utmi_pll_config_in_car_module;
	34	bool has_hostpc;
	35	bool requires_usbmode_setup;
	36	bool requires_extra_tuning_parameters;
	37	};
	38
91525d08 BG	39	struct tegra_utmip_config {
	40	u8 hssync_start_delay;
	41	u8 elastic_limit;
	42	u8 idle_wait_delay;
	43	u8 term_range_adj;
e497a24d	44	bool xcvr_setup_use_fuses;
91525d08 BG	45	u8 xcvr_setup;
	46	u8 xcvr_lsfslew;
	47	u8 xcvr_lsrslew;
e497a24d TT	48	u8 xcvr_hsslew;
	49	u8 hssquelch_level;
	50	u8 hsdiscon_level;
91525d08 BG	51	};
91525d08 BG	52
91525d08 BG	53	enum tegra_usb_phy_port_speed {
	54	TEGRA_USB_PHY_PORT_SPEED_FULL = 0,
	55	TEGRA_USB_PHY_PORT_SPEED_LOW,
	56	TEGRA_USB_PHY_PORT_SPEED_HIGH,
	57	};
	58
91525d08 BG	59	struct tegra_xtal_freq;
	60
	61	struct tegra_usb_phy {
	62	int instance;
	63	const struct tegra_xtal_freq *freq;
	64	void __iomem *regs;
	65	void __iomem *pad_regs;
	66	struct clk *clk;
	67	struct clk *pll_u;
	68	struct clk *pad_clk;
f5b8c8b6	69	struct regulator *vbus;
6558d7ed	70	enum usb_dr_mode mode;
91525d08	71	void *config;
3e635202	72	const struct tegra_phy_soc_config *soc_config;
86753811	73	struct usb_phy *ulpi;
1ba8216f	74	struct usb_phy u_phy;
3a55c6a8	75	bool is_legacy_phy;
3f9db1a1	76	bool is_ulpi_phy;
12ea18e4	77	int reset_gpio;
91525d08 BG	78	};
91525d08 BG	79
ab137d04	80	void tegra_usb_phy_preresume(struct usb_phy *phy);
91525d08	81
ab137d04	82	void tegra_usb_phy_postresume(struct usb_phy *phy);
91525d08	83
ab137d04	84	void tegra_ehci_phy_restore_start(struct usb_phy *phy,
91525d08 BG	85	enum tegra_usb_phy_port_speed port_speed);
91525d08 BG	86
ab137d04	87	void tegra_ehci_phy_restore_end(struct usb_phy *phy);
91525d08	88
1ba8216f	89	#endif /* __TEGRA_USB_PHY_H */