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[AArch64][PATCH 10/14] Rework code mapping vector types to operand qualifiers.
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
1e6f4800
MW		 12015-12-11 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB.
4 * aarch64-asm-2.c: Regenerate.
5 * aarch64-dis-2.c: Regenerate.
6 * aarch64-opc-2.c: Regenerate.
7 * aarch64-opc.c (aarch64_hint_options): Add "csync".
8 (aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB.
9 * aarch64-tbl.h (aarch64_feature_stat_profile): New.
10 (STAT_PROFILE): New.
11 (aarch64_opcode_table): Add "psb".
12 (AARCH64_OPERANDS): Add "BARRIER_PSB".
13
9ed608f9
MW		 142015-12-11 Matthew Wahab <matthew.wahab@arm.com>
15
16 * aarch64.h (aarch64_hint_options): Declare.
17 (aarch64_opnd_info): Add field hint_option.
18
73af8ed6
MW		 192015-12-11 Matthew Wahab <matthew.wahab@arm.com>
20
21 * aarch64.h (AARCH64_FEATURE_PROFILE): New.
22
d6bf7ce6
MW		 232015-12-10 Matthew Wahab <matthew.wahab@arm.com>
24
25 * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
26
ea2deeec
MW		 272015-12-10 Matthew Wahab <matthew.wahab@arm.com>
28
29 * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
30 (aarch64_sys_ins_reg_has_xt): Declare.
31
c8a6db6f
MW		 322015-12-10 Matthew Wahab <matthew.wahab@arm.com>
33
34 * aarch64.h (AARCH64_FEATURE_RAS): New.
35 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.
36
af117b3c
MW		 372015-12-10 Matthew Wahab <matthew.wahab@arm.com>
38
39 * aarch64.h (AARCH64_FEATURE_F16): Fix clash with
40 AARCH64_FEATURE_V8_1.
41 (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
42 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
43 AARCH64_FEATURE_V8_1.
44
24b368f8
CZ		 452015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
46
47 * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].
48
d685192a
MW		 492015-11-27 Matthew Wahab <matthew.wahab@arm.com>
50
51 * aarch64.h (aarch64_op): Add OP_BFC.
52
87018195
MW		 532015-11-27 Matthew Wahab <matthew.wahab@arm.com>
54
55 * aarch64.h (AARCH64_FEATURE_F16): New.
56 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
57 features.
58
250aafa4
MW		 592015-11-20 Matthew Wahab <matthew.wahab@arm.com>
60
61 * aarch64.h (AARCH64_FEATURE_V8_1): New.
62 (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
63
56a1b672
MW		 642015-11-19 Matthew Wahab <matthew.wahab@arm.com>
65
66 * arm.h (ARM_EXT2_V8_2A): New.
67 (ARM_ARCH_V8_2A): New.
68
acb787b0
MW		 692015-11-19 Matthew Wahab <matthew.wahab@arm.com>
70
71 * aarch64.h (AARCH64_FEATURE_V8_2): New.
72 (AARCH64_ARCH_V8_2): New.
73
a680de9a
PB		 742015-11-11 Alan Modra <amodra@gmail.com>
75 Peter Bergner <bergner@vnet.ibm.com>
76
77 * ppc.h (PPC_OPCODE_POWER9): New define.
78 (PPC_OPCODE_VSX3): Likewise.
79
854eb72b
NC		 802015-11-02 Nick Clifton <nickc@redhat.com>
81
82 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
83
e292aa7a
NC		 842015-11-02 Nick Clifton <nickc@redhat.com>
85
86 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
87
43cdf5ae
YQ		 882015-10-28 Yao Qi <yao.qi@linaro.org>
89
90 * aarch64.h (aarch64_decode_insn): Update declaration.
91
875880c6
YQ		 922015-10-07 Yao Qi <yao.qi@linaro.org>
93
94 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
95 <name>: New field.
96
d3e12b29
YQ		 972015-10-07 Yao Qi <yao.qi@linaro.org>
98
99 * aarch64.h [__cplusplus]: Wrap in extern "C".
100
886a2506
NC		 1012015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
102 Cupertino Miranda <cmiranda@synopsys.com>
103
104 * arc-func.h: New file.
105 * arc.h: Likewise.
106
e141d84e
YQ		 1072015-10-02 Yao Qi <yao.qi@linaro.org>
108
109 * aarch64.h (aarch64_zero_register_p): Move the declaration
110 to column one.
111
36f4aab1
YQ		 1122015-10-02 Yao Qi <yao.qi@linaro.org>
113
114 * aarch64.h (aarch64_decode_insn): Declare it.
115
7ecc513a
DV		 1162015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
117
118 * s390.h (S390_INSTR_FLAG_HTM): New flag.
119 (S390_INSTR_FLAG_VX): New flag.
120 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
121
b6518b38
NC		 1222015-09-23 Nick Clifton <nickc@redhat.com>
123
124 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
125 shifting.
126
f04265ec
NC		 1272015-09-22 Nick Clifton <nickc@redhat.com>
128
129 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
130
7bdf96ef
NC		 1312015-09-09 Daniel Santos <daniel.santos@pobox.com>
132
133 * visium.h (gen_reg_table): Make static.
134 (fp_reg_table): Likewise.
135 (cc_table): Likewise.
136
f33026a9
MW		 1372015-07-20 Matthew Wahab <matthew.wahab@arm.com>
138
139 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
140 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
141 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
142 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
143
ef5a96d5
AM		 1442015-07-03 Alan Modra <amodra@gmail.com>
145
146 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
147
c8c8175b
SL		 1482015-07-01 Sandra Loosemore <sandra@codesourcery.com>
149 Cesar Philippidis <cesar@codesourcery.com>
150
151 * nios2.h (enum iw_format_type): Add R2 formats.
152 (enum overflow_type): Add signed_immed12_overflow and
153 enumeration_overflow for R2.
154 (struct nios2_opcode): Document new argument letters for R2.
155 (REG_3BIT, REG_LDWM, REG_POP): Define.
156 (includes): Include nios2r2.h.
157 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
158 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
159 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
160 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
161 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
162 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
163 Declare.
164 * nios2r2.h: New file.
165
11a0cf2e
PB		 1662015-06-19 Peter Bergner <bergner@vnet.ibm.com>
167
168 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
169 (ppc_optional_operand_value): New inline function.
170
88f0ea34
MW		 1712015-06-04 Matthew Wahab <matthew.wahab@arm.com>
172
173 * aarch64.h (AARCH64_V8_1): New.
174
a5932920
MW		 1752015-06-03 Matthew Wahab <matthew.wahab@arm.com>
176
177 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
178 (ARM_ARCH_V8_1A): New.
179 (ARM_ARCH_V8_1A_FP): New.
180 (ARM_ARCH_V8_1A_SIMD): New.
181 (ARM_ARCH_V8_1A_CRYPTOV1): New.
182 (ARM_FEATURE_CORE): New.
183
ddfded2f
MW		 1842015-06-02 Matthew Wahab <matthew.wahab@arm.com>
185
186 * arm.h (ARM_EXT2_PAN): New.
187 (ARM_FEATURE_CORE_HIGH): New.
188
1af1dd51
MW		 1892015-06-02 Matthew Wahab <matthew.wahab@arm.com>
190
191 * arm.h (ARM_FEATURE_ALL): New.
192
9e1f0fa7
MW		 1932015-06-02 Matthew Wahab <matthew.wahab@arm.com>
194
195 * aarch64.h (AARCH64_FEATURE_RDMA): New.
196
290806fd
MW		 1972015-06-02 Matthew Wahab <matthew.wahab@arm.com>
198
199 * aarch64.h (AARCH64_FEATURE_LOR): New.
200
f21cce2c
MW		 2012015-06-01 Matthew Wahab <matthew.wahab@arm.com>
202
203 * aarch64.h (AARCH64_FEATURE_PAN): New.
204 (aarch64_sys_reg_supported_p): Declare.
205 (aarch64_pstatefield_supported_p): Declare.
206
0952813b
DD		 2072015-04-30 DJ Delorie <dj@redhat.com>
208
209 * rl78.h (RL78_Dis_Isa): New.
210 (rl78_decode_opcode): Add ISA parameter.
211
823d2571
TG		 2122015-03-24 Terry Guo <terry.guo@arm.com>
213
214 * arm.h (arm_feature_set): Extended to provide more available bits.
215 (ARM_ANY): Updated to follow above new definition.
216 (ARM_CPU_HAS_FEATURE): Likewise.
217 (ARM_CPU_IS_ANY): Likewise.
218 (ARM_MERGE_FEATURE_SETS): Likewise.
219 (ARM_CLEAR_FEATURE): Likewise.
220 (ARM_FEATURE): Likewise.
221 (ARM_FEATURE_COPY): New macro.
222 (ARM_FEATURE_EQUAL): Likewise.
223 (ARM_FEATURE_ZERO): Likewise.
224 (ARM_FEATURE_CORE_EQUAL): Likewise.
225 (ARM_FEATURE_LOW): Likewise.
226 (ARM_FEATURE_CORE_LOW): Likewise.
227 (ARM_FEATURE_CORE_COPROC): Likewise.
228
f63c1776
PA		 2292015-02-19 Pedro Alves <palves@redhat.com>
230
231 * cgen.h [__cplusplus]: Wrap in extern "C".
232 * msp430-decode.h [__cplusplus]: Likewise.
233 * nios2.h [__cplusplus]: Likewise.
234 * rl78.h [__cplusplus]: Likewise.
235 * rx.h [__cplusplus]: Likewise.
236 * tilegx.h [__cplusplus]: Likewise.
237
3f8107ab
AM		 2382015-01-28 James Bowman <james.bowman@ftdichip.com>
239
240 * ft32.h: New file.
241
1e2e8c52
AK		 2422015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
243
244 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
245
b90efa5b
AM		 2462015-01-01 Alan Modra <amodra@gmail.com>
247
248 Update year range in copyright notice of all files.
249
bffb6004
AG		 2502014-12-27 Anthony Green <green@moxielogic.com>
251
252 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
253 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
254
1945cfa5
EB		 2552014-12-06 Eric Botcazou <ebotcazou@adacore.com>
256
257 * visium.h: New file.
258
d306ce58
SL		 2592014-11-28 Sandra Loosemore <sandra@codesourcery.com>
260
261 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
262 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
263 (NIOS2_INSN_OPTARG): Renumber.
264
b4714c7c
SL		 2652014-11-06 Sandra Loosemore <sandra@codesourcery.com>
266
267 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
268 declaration. Fix obsolete comment.
269
96ba4233
SL		 2702014-10-23 Sandra Loosemore <sandra@codesourcery.com>
271
272 * nios2.h (enum iw_format_type): New.
273 (struct nios2_opcode): Update comments. Add size and format fields.
274 (NIOS2_INSN_OPTARG): New.
275 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
276 (struct nios2_reg): Add regtype field.
277 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
278 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
279 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
280 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
281 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
282 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
283 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
284 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
285 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
286 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
287 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
288 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
289 (OP_MASK_OP, OP_SH_OP): Delete.
290 (OP_MASK_IOP, OP_SH_IOP): Delete.
291 (OP_MASK_IRD, OP_SH_IRD): Delete.
292 (OP_MASK_IRT, OP_SH_IRT): Delete.
293 (OP_MASK_IRS, OP_SH_IRS): Delete.
294 (OP_MASK_ROP, OP_SH_ROP): Delete.
295 (OP_MASK_RRD, OP_SH_RRD): Delete.
296 (OP_MASK_RRT, OP_SH_RRT): Delete.
297 (OP_MASK_RRS, OP_SH_RRS): Delete.
298 (OP_MASK_JOP, OP_SH_JOP): Delete.
299 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
300 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
301 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
302 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
303 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
304 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
305 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
306 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
307 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
308 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
309 (OP_MASK_<insn>, OP_MASK): Delete.
310 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
311 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
312 Include nios2r1.h to define new instruction opcode constants
313 and accessors.
314 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
315 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
316 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
317 (NUMOPCODES, NUMREGISTERS): Delete.
318 * nios2r1.h: New file.
319
0b6be415
JM		 3202014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
321
322 * sparc.h (HWCAP2_VIS3B): Documentation improved.
323
3d68f91c
JM		 3242014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
325
326 * sparc.h (sparc_opcode): new field `hwcaps2'.
327 (HWCAP2_FJATHPLUS): New define.
328 (HWCAP2_VIS3B): Likewise.
329 (HWCAP2_ADP): Likewise.
330 (HWCAP2_SPARC5): Likewise.
331 (HWCAP2_MWAIT): Likewise.
332 (HWCAP2_XMPMUL): Likewise.
333 (HWCAP2_XMONT): Likewise.
334 (HWCAP2_NSEC): Likewise.
335 (HWCAP2_FJATHHPC): Likewise.
336 (HWCAP2_FJDES): Likewise.
337 (HWCAP2_FJAES): Likewise.
338 Document the new operand kind `{', corresponding to the mcdper
339 ancillary state register.
340 Document the new operand kind }, which represents frsd floating
341 point registers (double precision) which must be the same than
342 frs1 in its containing instruction.
343
40c7a7cb
KLC		 3442014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
345
72f4393d 346 * nds32.h: Add new opcode declaration.
40c7a7cb 347
7361da2c
AB		 3482014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
349 Matthew Fortune <matthew.fortune@imgtec.com>
350
351 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
352 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
353 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
354 +I, +O, +R, +:, +\, +", +;
355 (mips_check_prev_operand): New struct.
356 (INSN2_FORBIDDEN_SLOT): New define.
357 (INSN_ISA32R6): New define.
358 (INSN_ISA64R6): New define.
359 (INSN_UPTO32R6): New define.
360 (INSN_UPTO64R6): New define.
361 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
362 (ISA_MIPS32R6): New define.
363 (ISA_MIPS64R6): New define.
364 (CPU_MIPS32R6): New define.
365 (CPU_MIPS64R6): New define.
366 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
367
ee804238
JW		 3682014-09-03 Jiong Wang <jiong.wang@arm.com>
369
370 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
371 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
372 (aarch64_insn_class): Add lse_atomic.
373 (F_LSE_SZ): New field added.
374 (opcode_has_special_coder): Recognize F_LSE_SZ.
375
5575639b
MR		 3762014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
377
378 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
379 over to `+J'.
380
43885403
MF		 3812014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
382
383 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
384 (INSN_LOAD_COPROC): New define.
385 (INSN_COPROC_MOVE_DELAY): Rename to...
386 (INSN_COPROC_MOVE): New define.
387
f36e8886 3882014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
72f4393d
L		 389 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
390 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
391 Soundararajan <Sounderarajan.D@atmel.com>
f36e8886
BS		 392
393 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
394 (AVR_ISA_2xxxa): Define ISA without LPM.
395 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
396 Add doc for contraint used in 16 bit lds/sts.
397 Adjust ISA group for icall, ijmp, pop and push.
398 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
399
00b32ff2
NC		 4002014-05-19 Nick Clifton <nickc@redhat.com>
401
402 * msp430.h (struct msp430_operand_s): Add vshift field.
403
ae52f483
AB		 4042014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
405
406 * mips.h (INSN_ISA_MASK): Updated.
407 (INSN_ISA32R3): New define.
408 (INSN_ISA32R5): New define.
409 (INSN_ISA64R3): New define.
410 (INSN_ISA64R5): New define.
411 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
412 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
413 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
414 mips64r5.
415 (INSN_UPTO32R3): New define.
416 (INSN_UPTO32R5): New define.
417 (INSN_UPTO64R3): New define.
418 (INSN_UPTO64R5): New define.
419 (ISA_MIPS32R3): New define.
420 (ISA_MIPS32R5): New define.
421 (ISA_MIPS64R3): New define.
422 (ISA_MIPS64R5): New define.
423 (CPU_MIPS32R3): New define.
424 (CPU_MIPS32R5): New define.
425 (CPU_MIPS64R3): New define.
426 (CPU_MIPS64R5): New define.
427
3efe9ec5
RS		 4282014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
429
430 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
431
73589c9d
CS		 4322014-04-22 Christian Svensson <blue@cmd.nu>
433
434 * or32.h: Delete.
435
4b95cf5c
AM		 4362014-03-05 Alan Modra <amodra@gmail.com>
437
438 Update copyright years.
439
e269fea7
AB		 4402013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
441
442 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
443 microMIPS.
444
35c08157
KLC		 4452013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
446 Wei-Cheng Wang <cole945@gmail.com>
447
448 * nds32.h: New file for Andes NDS32.
449
594d8fa8
MF		 4502013-12-07 Mike Frysinger <vapier@gentoo.org>
451
452 * bfin.h: Remove +x file mode.
453
87b8eed7
YZ		 4542013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
455
456 * aarch64.h (aarch64_pstatefields): Change element type to
457 aarch64_sys_reg.
458
c9fb6e58
YZ		 4592013-11-18 Renlin Li <Renlin.Li@arm.com>
460
461 * arm.h (ARM_AEXT_V7VE): New define.
462 (ARM_ARCH_V7VE): New define.
463 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
464
a203d9b7
YZ		 4652013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
466
467 Revert
468
469 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
470
471 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
472 (aarch64_sys_reg_writeonly_p): Ditto.
473
75468c93
YZ		 4742013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
475
476 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
477 (aarch64_sys_reg_writeonly_p): Ditto.
478
49eec193
YZ		 4792013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
480
481 * aarch64.h (aarch64_sys_reg): New typedef.
482 (aarch64_sys_regs): Change to define with the new type.
483 (aarch64_sys_reg_deprecated_p): Declare.
484
68a64283
YZ		 4852013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
486
487 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
488 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
489
387a82f1
CF		 4902013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
491
492 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
493 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
494 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
495 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
496 For MIPS, update extension character sequences after +.
497 (ASE_MSA): New define.
498 (ASE_MSA64): New define.
499 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
500 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
501 For microMIPS, update extension character sequences after +.
502
9aff4b7a
NC		 5032013-08-23 Yuri Chornoivan <yurchor@ukr.net>
504
505 PR binutils/15834
506 * i960.h: Fix typos.
507
e423441d
RS		 5082013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
509
510 * mips.h: Remove references to "+I" and imm2_expr.
511
5e0dc5ba
RS		 5122013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
513
514 * mips.h (M_DEXT, M_DINS): Delete.
515
0f35dbc4
RS		 5162013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
517
518 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
519 (mips_optional_operand_p): New function.
520
14daeee3
RS		 5212013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
522 Richard Sandiford <rdsandiford@googlemail.com>
523
524 * mips.h: Document new VU0 operand characters.
525 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
526 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
527 (OP_REG_R5900_ACC): New mips_reg_operand_types.
528 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
529 (mips_vu0_channel_mask): Declare.
530
3ccad066
RS		 5312013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
532
533 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
534 (mips_int_operand_min, mips_int_operand_max): New functions.
535 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
536
fc76e730
RS		 5372013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
538
539 * mips.h (mips_decode_reg_operand): New function.
540 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
541 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
542 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
543 New macros.
544 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
545 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
546 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
547 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
548 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
549 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
550 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
551 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
552 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
553 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
554 macros to cover the gaps.
555 (INSN2_MOD_SP): Replace with...
556 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
557 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
558 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
559 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
560 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
561 Delete.
562
26545944
RS		 5632013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
564
565 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
566 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
567 (MIPS16_INSN_COND_BRANCH): Delete.
568
7e8b059b
L		 5692013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
570 Kirill Yukhin <kirill.yukhin@intel.com>
571 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
572
573 * i386.h (BND_PREFIX_OPCODE): New.
574
c3c07478
RS		 5752013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
576
577 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
578 OP_SAVE_RESTORE_LIST.
579 (decode_mips16_operand): Declare.
580
ab902481
RS		 5812013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
582
583 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
584 (mips_operand, mips_int_operand, mips_mapped_int_operand)
585 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
586 (mips_pcrel_operand): New structures.
587 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
588 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
589 (decode_mips_operand, decode_micromips_operand): Declare.
590
cc537e56
RS		 5912013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
592
593 * mips.h: Document MIPS16 "I" opcode.
594
f2ae14a1
RS		 5952013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
596
597 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
598 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
599 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
600 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
601 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
602 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
603 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
604 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
605 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
606 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
607 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
608 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
609 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
610 Rename to...
611 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
612 (M_USD_AB): ...these.
613
5c324c16
RS		 6142013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
615
616 * mips.h: Remove documentation of "[" and "]". Update documentation
617 of "k" and the MDMX formats.
618
23e69e47
RS		 6192013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
620
621 * mips.h: Update documentation of "+s" and "+S".
622
27c5c572
RS		 6232013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
624
625 * mips.h: Document "+i".
626
e76ff5ab
RS		 6272013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
628
629 * mips.h: Remove "mi" documentation. Update "mh" documentation.
630 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
631 Delete.
632 (INSN2_WRITE_GPR_MHI): Rename to...
633 (INSN2_WRITE_GPR_MH): ...this.
634
fa7616a4
RS		 6352013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
636
637 * mips.h: Remove documentation of "+D" and "+T".
638
18870af7
RS		 6392013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
640
641 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
642 Use "source" rather than "destination" for microMIPS "G".
643
833794fc
MR		 6442013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
645
646 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
647 values.
648
c3678916
RS		 6492013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
650
651 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
652
7f3c4072
CM		 6532013-06-17 Catherine Moore <clm@codesourcery.com>
654 Maciej W. Rozycki <macro@codesourcery.com>
655 Chao-Ying Fu <fu@mips.com>
656
657 * mips.h (OP_SH_EVAOFFSET): Define.
658 (OP_MASK_EVAOFFSET): Define.
659 (INSN_ASE_MASK): Delete.
660 (ASE_EVA): Define.
661 (M_CACHEE_AB, M_CACHEE_OB): New.
662 (M_LBE_OB, M_LBE_AB): New.
663 (M_LBUE_OB, M_LBUE_AB): New.
664 (M_LHE_OB, M_LHE_AB): New.
665 (M_LHUE_OB, M_LHUE_AB): New.
666 (M_LLE_AB, M_LLE_OB): New.
667 (M_LWE_OB, M_LWE_AB): New.
668 (M_LWLE_AB, M_LWLE_OB): New.
669 (M_LWRE_AB, M_LWRE_OB): New.
670 (M_PREFE_AB, M_PREFE_OB): New.
671 (M_SCE_AB, M_SCE_OB): New.
672 (M_SBE_OB, M_SBE_AB): New.
673 (M_SHE_OB, M_SHE_AB): New.
674 (M_SWE_OB, M_SWE_AB): New.
675 (M_SWLE_AB, M_SWLE_OB): New.
676 (M_SWRE_AB, M_SWRE_OB): New.
677 (MICROMIPSOP_SH_EVAOFFSET): Define.
678 (MICROMIPSOP_MASK_EVAOFFSET): Define.
679
0c8fe7cf
SL		 6802013-06-12 Sandra Loosemore <sandra@codesourcery.com>
681
682 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
683
c77c0862
RS		 6842013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
685
686 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
687
b015e599
AP		 6882013-05-09 Andrew Pinski <apinski@cavium.com>
689
690 * mips.h (OP_MASK_CODE10): Correct definition.
691 (OP_SH_CODE10): Likewise.
692 Add a comment that "+J" is used now for OP_*CODE10.
693 (INSN_ASE_MASK): Update.
694 (INSN_VIRT): New macro.
695 (INSN_VIRT64): New macro
696
13761a11
NC		 6972013-05-02 Nick Clifton <nickc@redhat.com>
698
699 * msp430.h: Add patterns for MSP430X instructions.
700
0afd1215
DM		 7012013-04-06 David S. Miller <davem@davemloft.net>
702
703 * sparc.h (F_PREFERRED): Define.
704 (F_PREF_ALIAS): Define.
705
41702d50
NC		 7062013-04-03 Nick Clifton <nickc@redhat.com>
707
708 * v850.h (V850_INVERSE_PCREL): Define.
709
e21e1a51
NC		 7102013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
711
712 PR binutils/15068
713 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
714
51dcdd4d
NC		 7152013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
716
717 PR binutils/15068
718 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
719 Add 16-bit opcodes.
720 * tic6xc-opcode-table.h: Add 16-bit insns.
721 * tic6x.h: Add support for 16-bit insns.
722
81f5558e
NC		 7232013-03-21 Michael Schewe <michael.schewe@gmx.net>
724
725 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
726 and mov.b/w/l Rs,@(d:32,ERd).
727
165546ad
NC		 7282013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
729
730 PR gas/15082
731 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
732 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
733 tic6x_operand_xregpair operand coding type.
734 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
735 opcode field, usu ORXREGD1324 for the src2 operand and remove the
736 TIC6X_FLAG_NO_CROSS.
737
795b8e6b
NC		 7382013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
739
740 PR gas/15095
741 * tic6x.h (enum tic6x_coding_method): Add
742 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
743 separately the msb and lsb of a register pair. This is needed to
744 encode the opcodes in the same way as TI assembler does.
745 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
746 and rsqrdp opcodes to use the new field coding types.
747
dd5181d5
KT		 7482013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
749
750 * arm.h (CRC_EXT_ARMV8): New constant.
751 (ARCH_CRC_ARMV8): New macro.
752
e60bb1dd
YZ		 7532013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
754
755 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
756
36591ba1 7572013-02-06 Sandra Loosemore <sandra@codesourcery.com>
72f4393d 758 Andrew Jenner <andrew@codesourcery.com>
36591ba1
SL		 759
760 Based on patches from Altera Corporation.
761
762 * nios2.h: New file.
763
e30181a5
YZ		 7642013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
765
766 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
767
0c9573f4
NC		 7682013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
769
770 PR gas/15069
771 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
772
981dc7f1
NC		 7732013-01-24 Nick Clifton <nickc@redhat.com>
774
775 * v850.h: Add e3v5 support.
776
f5555712
YZ		 7772013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
778
779 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
780
5817ffd1
PB		 7812013-01-10 Peter Bergner <bergner@vnet.ibm.com>
782
783 * ppc.h (PPC_OPCODE_POWER8): New define.
784 (PPC_OPCODE_HTM): Likewise.
785
a3c62988
NC		 7862013-01-10 Will Newton <will.newton@imgtec.com>
787
788 * metag.h: New file.
789
73335eae
NC		 7902013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
791
792 * cr16.h (make_instruction): Rename to cr16_make_instruction.
793 (match_opcode): Rename to cr16_match_opcode.
794
e407c74b
NC		 7952013-01-04 Juergen Urban <JuergenUrban@gmx.de>
796
797 * mips.h: Add support for r5900 instructions including lq and sq.
798
bab4becb
NC		 7992013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
800
801 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
802 (make_instruction,match_opcode): Added function prototypes.
803 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
804
776fc418
AM		 8052012-11-23 Alan Modra <amodra@gmail.com>
806
807 * ppc.h (ppc_parse_cpu): Update prototype.
808
f05682d4
DA		 8092012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
810
811 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
812 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
813
cfc72779
AK		 8142012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
815
816 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
817
b3e14eda
L		 8182012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
819
820 * ia64.h (ia64_opnd): Add new operand types.
821
2c63854f
DM		 8222012-08-21 David S. Miller <davem@davemloft.net>
823
824 * sparc.h (F3F4): New macro.
825
a06ea964 8262012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 827 Laurent Desnogues <laurent.desnogues@arm.com>
828 Jim MacArthur <jim.macarthur@arm.com>
829 Marcus Shawcroft <marcus.shawcroft@arm.com>
830 Nigel Stephens <nigel.stephens@arm.com>
831 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
832 Richard Earnshaw <rearnsha@arm.com>
833 Sofiane Naci <sofiane.naci@arm.com>
834 Tejas Belagod <tejas.belagod@arm.com>
835 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 836
837 * aarch64.h: New file.
838
35d0a169 8392012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 840 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 841
842 * mips.h (mips_opcode): Add the exclusions field.
843 (OPCODE_IS_MEMBER): Remove macro.
844 (cpu_is_member): New inline function.
845 (opcode_is_member): Likewise.
846
03f66e8a 8472012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 848 Catherine Moore <clm@codesourcery.com>
849 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 850
851 * mips.h: Document microMIPS DSP ASE usage.
852 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
853 microMIPS DSP ASE support.
854 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
855 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
856 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
857 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
858 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
859 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
860 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
861
9d7b4c23
MR		 8622012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
863
864 * mips.h: Fix a typo in description.
865
76e879f8
NC		 8662012-06-07 Georg-Johann Lay <avr@gjlay.de>
867
868 * avr.h: (AVR_ISA_XCH): New define.
869 (AVR_ISA_XMEGA): Use it.
870 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
871
6927f982
NC		 8722012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
873
874 * m68hc11.h: Add XGate definitions.
875 (struct m68hc11_opcode): Add xg_mask field.
876
b9c361e0
JL		 8772012-05-14 Catherine Moore <clm@codesourcery.com>
878 Maciej W. Rozycki <macro@codesourcery.com>
879 Rhonda Wittels <rhonda@codesourcery.com>
880
6927f982 881 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 882 (PPC_OP_SA): New macro.
883 (PPC_OP_SE_VLE): New macro.
884 (PPC_OP): Use a variable shift amount.
885 (powerpc_operand): Update comments.
886 (PPC_OPSHIFT_INV): New macro.
887 (PPC_OPERAND_CR): Replace with...
888 (PPC_OPERAND_CR_BIT): ...this and
889 (PPC_OPERAND_CR_REG): ...this.
890
891
f6c1a2d5
NC		 8922012-05-03 Sean Keys <skeys@ipdatasys.com>
893
894 * xgate.h: Header file for XGATE assembler.
895
ec668d69
DM		 8962012-04-27 David S. Miller <davem@davemloft.net>
897
6cda1326
DM		 898 * sparc.h: Document new arg code' )' for crypto RS3
899 immediates.
900
ec668d69
DM		 901 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
902 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
903 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
904 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
905 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
906 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
907 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
908 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
909 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
910 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
911 HWCAP_CBCOND, HWCAP_CRC32): New defines.
912
aea77599
AM		 9132012-03-10 Edmar Wienskoski <edmar@freescale.com>
914
915 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
916
1f42f8b3
AM		 9172012-02-27 Alan Modra <amodra@gmail.com>
918
919 * crx.h (cst4_map): Update declaration.
920
6f7be959
WL		 9212012-02-25 Walter Lee <walt@tilera.com>
922
923 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
924 TILEGX_OPC_LD_TLS.
925 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
926 TILEPRO_OPC_LW_TLS_SN.
927
42164a71
L		 9282012-02-08 H.J. Lu <hongjiu.lu@intel.com>
929
930 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
931 (XRELEASE_PREFIX_OPCODE): Likewise.
932
432233b3 9332011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 934 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 935
936 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
937 (INSN_OCTEON2): New macro.
938 (CPU_OCTEON2): New macro.
939 (OPCODE_IS_MEMBER): Add Octeon2.
940
dd6a37e7
AP		 9412011-11-29 Andrew Pinski <apinski@cavium.com>
942
943 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
944 (INSN_OCTEONP): New macro.
945 (CPU_OCTEONP): New macro.
946 (OPCODE_IS_MEMBER): Add Octeon+.
947 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
948
99c513f6
DD		 9492011-11-01 DJ Delorie <dj@redhat.com>
950
951 * rl78.h: New file.
952
26f85d7a
MR		 9532011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
954
955 * mips.h: Fix a typo in description.
956
9e8c70f9
DM		 9572011-09-21 David S. Miller <davem@davemloft.net>
958
959 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
960 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
961 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
962 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
963
dec0624d 9642011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 965 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 966
967 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
968 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
969 (INSN_ASE_MASK): Add the MCU bit.
970 (INSN_MCU): New macro.
971 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
972 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
973
2b0c8b40
MR		 9742011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
975
976 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
977 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
978 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
979 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
980 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
981 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
982 (INSN2_READ_GPR_MMN): Likewise.
983 (INSN2_READ_FPR_D): Change the bit used.
984 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
985 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
986 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
987 (INSN2_COND_BRANCH): Likewise.
988 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
989 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
990 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
991 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
992 (INSN2_MOD_GPR_MN): Likewise.
993
ea783ef3
DM		 9942011-08-05 David S. Miller <davem@davemloft.net>
995
996 * sparc.h: Document new format codes '4', '5', and '('.
997 (OPF_LOW4, RS3): New macros.
998
7c176fa8
MR		 9992011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
1000
1001 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
1002 order of flags documented.
1003
2309ddf2
MR		 10042011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
1005
1006 * mips.h: Clarify the description of microMIPS instruction
1007 manipulation macros.
1008 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
1009
df58fc94 10102011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 1011 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 1012
1013 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
1014 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
1015 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
1016 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
1017 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
1018 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
1019 (OP_MASK_RS3, OP_SH_RS3): Likewise.
1020 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
1021 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
1022 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
1023 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
1024 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
1025 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
1026 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
1027 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
1028 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
1029 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
1030 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
1031 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
1032 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
1033 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
1034 (INSN_WRITE_GPR_S): New macro.
1035 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
1036 (INSN2_READ_FPR_D): Likewise.
1037 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
1038 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
1039 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
1040 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
1041 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
1042 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
1043 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
1044 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
1045 (CPU_MICROMIPS): New macro.
1046 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
1047 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
1048 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
1049 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
1050 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
1051 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
1052 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
1053 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
1054 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
1055 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
1056 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
1057 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
1058 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
1059 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
1060 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
1061 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
1062 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
1063 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
1064 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
1065 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
1066 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
1067 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
1068 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
1069 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1070 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1071 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1072 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1073 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1074 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1075 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1076 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1077 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1078 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1079 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1080 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1081 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1082 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1083 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1084 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1085 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1086 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1087 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1088 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1089 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1090 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1091 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1092 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1093 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1094 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1095 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1096 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1097 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1098 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1099 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1100 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1101 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1102 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1103 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1104 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1105 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1106 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1107 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1108 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1109 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1110 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1111 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1112 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1113 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1114 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1115 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1116 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1117 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1118 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1119 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1120 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1121 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1122 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1123 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1124 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1125 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1126 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1127 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1128 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1129 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1130 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1131 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1132 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1133 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1134 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1135 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1136 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1137 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1138 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1139 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1140 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1141 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1142 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1143 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1144 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1145 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1146 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1147 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1148 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1149 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1150 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1151 (micromips_opcodes): New declaration.
1152 (bfd_micromips_num_opcodes): Likewise.
1153
bcd530a7
RS		 11542011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1155
1156 * mips.h (INSN_TRAP): Rename to...
1157 (INSN_NO_DELAY_SLOT): ... this.
1158 (INSN_SYNC): Remove macro.
1159
2dad5a91
EW		 11602011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1161
1162 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1163 a duplicate of AVR_ISA_SPM.
1164
5d73b1f1
NC		 11652011-07-01 Nick Clifton <nickc@redhat.com>
1166
1167 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1168
ef26d60e
MF		 11692011-06-18 Robin Getz <robin.getz@analog.com>
1170
1171 * bfin.h (is_macmod_signed): New func
1172
8fb8dca7
MF		 11732011-06-18 Mike Frysinger <vapier@gentoo.org>
1174
1175 * bfin.h (is_macmod_pmove): Add missing space before func args.
1176 (is_macmod_hmove): Likewise.
1177
aa137e4d
NC		 11782011-06-13 Walter Lee <walt@tilera.com>
1179
1180 * tilegx.h: New file.
1181 * tilepro.h: New file.
1182
3b2f0793
PB		 11832011-05-31 Paul Brook <paul@codesourcery.com>
1184
aa137e4d
NC		 1185 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1186
11872011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1188
1189 * s390.h: Replace S390_OPERAND_REG_EVEN with
1190 S390_OPERAND_REG_PAIR.
1191
11922011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1193
1194 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1195
ac7f631b
NC		 11962011-04-18 Julian Brown <julian@codesourcery.com>
1197
1198 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1199
84701018
NC		 12002011-04-11 Dan McDonald <dan@wellkeeper.com>
1201
1202 PR gas/12296
1203 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1204
8cc66334
EW		 12052011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1206
1207 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1208 New instruction set flags.
1209 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1210
3eebd5eb
MR		 12112011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1212
1213 * mips.h (M_PREF_AB): New enum value.
1214
26bb3ddd
MF		 12152011-02-12 Mike Frysinger <vapier@gentoo.org>
1216
89c0d58c
MR		 1217 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1218 M_IU): Define.
1219 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1220
dd76fcb8
MF		 12212011-02-11 Mike Frysinger <vapier@gentoo.org>
1222
1223 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1224
98d23bef
BS		 12252011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1226
1227 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1228 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1229
3c853d93
DA		 12302010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1231
1232 PR gas/11395
1233 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1234 "bb" entries.
1235
79676006
DA		 12362010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1237
1238 PR gas/11395
1239 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1240
1bec78e9
RS		 12412010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1242
1243 * mips.h: Update commentary after last commit.
1244
98675402
RS		 12452010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1246
1247 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1248 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1249 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1250
aa137e4d
NC		 12512010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1252
1253 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1254
435b94a4
RS		 12552010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1256
1257 * mips.h: Fix previous commit.
1258
d051516a
NC		 12592010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1260
1261 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1262 (INSN_LOONGSON_3A): Clear bit 31.
1263
251665fc
MGD		 12642010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1265
1266 PR gas/12198
1267 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1268 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1269 (ARM_ARCH_V6M_ONLY): New define.
1270
fd503541
NC		 12712010-11-11 Mingming Sun <mingm.sun@gmail.com>
1272
1273 * mips.h (INSN_LOONGSON_3A): Defined.
1274 (CPU_LOONGSON_3A): Defined.
1275 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1276
4469d2be
AM		 12772010-10-09 Matt Rice <ratmice@gmail.com>
1278
1279 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1280 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1281
90ec0d68
MGD		 12822010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1283
1284 * arm.h (ARM_EXT_VIRT): New define.
1285 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1286 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1287 Extensions.
1288
eea54501 12892010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1290
eea54501
MGD		 1291 * arm.h (ARM_AEXT_ADIV): New define.
1292 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1293
b2a5fbdc
MGD		 12942010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1295
1296 * arm.h (ARM_EXT_OS): New define.
1297 (ARM_AEXT_V6SM): Likewise.
1298 (ARM_ARCH_V6SM): Likewise.
1299
60e5ef9f
MGD		 13002010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1301
1302 * arm.h (ARM_EXT_MP): Add.
1303 (ARM_ARCH_V7A_MP): Likewise.
1304
73a63ccf
MF		 13052010-09-22 Mike Frysinger <vapier@gentoo.org>
1306
1307 * bfin.h: Declare pseudoChr structs/defines.
1308
ee99860a
MF		 13092010-09-21 Mike Frysinger <vapier@gentoo.org>
1310
1311 * bfin.h: Strip trailing whitespace.
1312
f9c7014e
DD		 13132010-07-29 DJ Delorie <dj@redhat.com>
1314
1315 * rx.h (RX_Operand_Type): Add TwoReg.
1316 (RX_Opcode_ID): Remove ediv and ediv2.
1317
93378652
DD		 13182010-07-27 DJ Delorie <dj@redhat.com>
1319
1320 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1321
1cd986c5
NC		 13222010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1323 Ina Pandit <ina.pandit@kpitcummins.com>
1324
1325 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1326 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1327 PROCESSOR_V850E2_ALL.
1328 Remove PROCESSOR_V850EA support.
1329 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1330 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1331 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1332 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1333 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1334 V850_OPERAND_PERCENT.
1335 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1336 V850_NOT_R0.
1337 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1338 and V850E_PUSH_POP
1339
9a2c7088
MR		 13402010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1341
1342 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1343 (MIPS16_INSN_BRANCH): Rename to...
1344 (MIPS16_INSN_COND_BRANCH): ... this.
1345
bdc70b4a
AM		 13462010-07-03 Alan Modra <amodra@gmail.com>
1347
1348 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1349 Renumber other PPC_OPCODE defines.
1350
f2bae120
AM		 13512010-07-03 Alan Modra <amodra@gmail.com>
1352
1353 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1354
360cfc9c
AM		 13552010-06-29 Alan Modra <amodra@gmail.com>
1356
1357 * maxq.h: Delete file.
1358
e01d869a
AM		 13592010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1360
1361 * ppc.h (PPC_OPCODE_E500): Define.
1362
f79e2745
CM		 13632010-05-26 Catherine Moore <clm@codesourcery.com>
1364
1365 * opcode/mips.h (INSN_MIPS16): Remove.
1366
2462afa1
JM		 13672010-04-21 Joseph Myers <joseph@codesourcery.com>
1368
1369 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1370
e4e42b45
NC		 13712010-04-15 Nick Clifton <nickc@redhat.com>
1372
1373 * alpha.h: Update copyright notice to use GPLv3.
1374 * arc.h: Likewise.
1375 * arm.h: Likewise.
1376 * avr.h: Likewise.
1377 * bfin.h: Likewise.
1378 * cgen.h: Likewise.
1379 * convex.h: Likewise.
1380 * cr16.h: Likewise.
1381 * cris.h: Likewise.
1382 * crx.h: Likewise.
1383 * d10v.h: Likewise.
1384 * d30v.h: Likewise.
1385 * dlx.h: Likewise.
1386 * h8300.h: Likewise.
1387 * hppa.h: Likewise.
1388 * i370.h: Likewise.
1389 * i386.h: Likewise.
1390 * i860.h: Likewise.
1391 * i960.h: Likewise.
1392 * ia64.h: Likewise.
1393 * m68hc11.h: Likewise.
1394 * m68k.h: Likewise.
1395 * m88k.h: Likewise.
1396 * maxq.h: Likewise.
1397 * mips.h: Likewise.
1398 * mmix.h: Likewise.
1399 * mn10200.h: Likewise.
1400 * mn10300.h: Likewise.
1401 * msp430.h: Likewise.
1402 * np1.h: Likewise.
1403 * ns32k.h: Likewise.
1404 * or32.h: Likewise.
1405 * pdp11.h: Likewise.
1406 * pj.h: Likewise.
1407 * pn.h: Likewise.
1408 * ppc.h: Likewise.
1409 * pyr.h: Likewise.
1410 * rx.h: Likewise.
1411 * s390.h: Likewise.
1412 * score-datadep.h: Likewise.
1413 * score-inst.h: Likewise.
1414 * sparc.h: Likewise.
1415 * spu-insns.h: Likewise.
1416 * spu.h: Likewise.
1417 * tic30.h: Likewise.
1418 * tic4x.h: Likewise.
1419 * tic54x.h: Likewise.
1420 * tic80.h: Likewise.
1421 * v850.h: Likewise.
1422 * vax.h: Likewise.
1423
40b36596
JM		 14242010-03-25 Joseph Myers <joseph@codesourcery.com>
1425
1426 * tic6x-control-registers.h, tic6x-insn-formats.h,
1427 tic6x-opcode-table.h, tic6x.h: New.
1428
c67a084a
NC		 14292010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1430
1431 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1432
466ef64f
AM		 14332010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1434
1435 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1436
1319d143
L		 14372010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1438
1439 * ia64.h (ia64_find_opcode): Remove argument name.
1440 (ia64_find_next_opcode): Likewise.
1441 (ia64_dis_opcode): Likewise.
1442 (ia64_free_opcode): Likewise.
1443 (ia64_find_dependency): Likewise.
1444
1fbb9298
DE		 14452009-11-22 Doug Evans <dje@sebabeach.org>
1446
1447 * cgen.h: Include bfd_stdint.h.
1448 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1449
ada65aa3
PB		 14502009-11-18 Paul Brook <paul@codesourcery.com>
1451
1452 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1453
9e3c6df6
PB		 14542009-11-17 Paul Brook <paul@codesourcery.com>
1455 Daniel Jacobowitz <dan@codesourcery.com>
1456
1457 * arm.h (ARM_EXT_V6_DSP): Define.
1458 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1459 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1460
0d734b5d
DD		 14612009-11-04 DJ Delorie <dj@redhat.com>
1462
1463 * rx.h (rx_decode_opcode) (mvtipl): Add.
1464 (mvtcp, mvfcp, opecp): Remove.
1465
62f3b8c8
PB		 14662009-11-02 Paul Brook <paul@codesourcery.com>
1467
1468 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1469 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1470 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1471 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1472 FPU_ARCH_NEON_VFP_V4): Define.
1473
ac1e9eca
DE		 14742009-10-23 Doug Evans <dje@sebabeach.org>
1475
1476 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1477 * cgen.h: Update. Improve multi-inclusion macro name.
1478
9fe54b1c
PB		 14792009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1480
1481 * ppc.h (PPC_OPCODE_476): Define.
1482
634b50f2
PB		 14832009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1484
1485 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1486
c7927a3c
NC		 14872009-09-29 DJ Delorie <dj@redhat.com>
1488
1489 * rx.h: New file.
1490
b961e85b
AM		 14912009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1492
1493 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1494
e0d602ec
BE		 14952009-09-21 Ben Elliston <bje@au.ibm.com>
1496
1497 * ppc.h (PPC_OPCODE_PPCA2): New.
1498
96d56e9f
NC		 14992009-09-05 Martin Thuresson <martin@mtme.org>
1500
1501 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1502
d3ce72d0
NC		 15032009-08-29 Martin Thuresson <martin@mtme.org>
1504
1505 * tic30.h (template): Rename type template to
1506 insn_template. Updated code to use new name.
1507 * tic54x.h (template): Rename type template to
1508 insn_template.
1509
824b28db
NH		 15102009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1511
1512 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1513
f865a31d
AG		 15142009-06-11 Anthony Green <green@moxielogic.com>
1515
1516 * moxie.h (MOXIE_F3_PCREL): Define.
1517 (moxie_form3_opc_info): Grow.
1518
0e7c7f11
AG		 15192009-06-06 Anthony Green <green@moxielogic.com>
1520
1521 * moxie.h (MOXIE_F1_M): Define.
1522
20135e4c
NC		 15232009-04-15 Anthony Green <green@moxielogic.com>
1524
1525 * moxie.h: Created.
1526
bcb012d3
DD		 15272009-04-06 DJ Delorie <dj@redhat.com>
1528
1529 * h8300.h: Add relaxation attributes to MOVA opcodes.
1530
69fe9ce5
AM		 15312009-03-10 Alan Modra <amodra@bigpond.net.au>
1532
1533 * ppc.h (ppc_parse_cpu): Declare.
1534
c3b7224a
NC		 15352009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1536
1537 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1538 and _IMM11 for mbitclr and mbitset.
1539 * score-datadep.h: Update dependency information.
1540
066be9f7
PB		 15412009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1542
1543 * ppc.h (PPC_OPCODE_POWER7): New.
1544
fedc618e
DE		 15452009-02-06 Doug Evans <dje@google.com>
1546
1547 * i386.h: Add comment regarding sse* insns and prefixes.
1548
52b6b6b9
JM		 15492009-02-03 Sandip Matte <sandip@rmicorp.com>
1550
1551 * mips.h (INSN_XLR): Define.
1552 (INSN_CHIP_MASK): Update.
1553 (CPU_XLR): Define.
1554 (OPCODE_IS_MEMBER): Update.
1555 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1556
35669430
DE		 15572009-01-28 Doug Evans <dje@google.com>
1558
1559 * opcode/i386.h: Add multiple inclusion protection.
1560 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1561 (EDI_REG_NUM): New macros.
1562 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1563 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1564 (REX_PREFIX_P): New macro.
35669430 1565
1cb0a767
PB		 15662009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1567
1568 * ppc.h (struct powerpc_opcode): New field "deprecated".
1569 (PPC_OPCODE_NOPOWER4): Delete.
1570
3aa3176b
TS		 15712008-11-28 Joshua Kinard <kumba@gentoo.org>
1572
1573 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1574 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1575
8e79c3df
CM		 15762008-11-18 Catherine Moore <clm@codesourcery.com>
1577
1578 * arm.h (FPU_NEON_FP16): New.
1579 (FPU_ARCH_NEON_FP16): New.
1580
de9a3e51
CF		 15812008-11-06 Chao-ying Fu <fu@mips.com>
1582
1583 * mips.h: Doucument '1' for 5-bit sync type.
1584
1ca35711
L		 15852008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1586
1587 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1588 IA64_RS_CR.
1589
9b4e5766
PB		 15902008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1591
1592 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1593
081ba1b3
AM		 15942008-07-30 Michael J. Eager <eager@eagercon.com>
1595
1596 * ppc.h (PPC_OPCODE_405): Define.
1597 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1598
fa452fa6
PB		 15992008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1600
1601 * ppc.h (ppc_cpu_t): New typedef.
1602 (struct powerpc_opcode <flags>): Use it.
1603 (struct powerpc_operand <insert, extract>): Likewise.
1604 (struct powerpc_macro <flags>): Likewise.
1605
bb35fb24
NC		 16062008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1607
1608 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1609 Update comment before MIPS16 field descriptors to mention MIPS16.
1610 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1611 BBIT.
1612 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1613 New bit masks and shift counts for cins and exts.
1614
dd3cbb7e
NC		 1615 * mips.h: Document new field descriptors +Q.
1616 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1617
d0799671
AN		 16182008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1619
9aff4b7a 1620 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1621 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1622
19a6653c
AM		 16232008-04-14 Edmar Wienskoski <edmar@freescale.com>
1624
1625 * ppc.h: (PPC_OPCODE_E500MC): New.
1626
c0f3af97
L		 16272008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1628
1629 * i386.h (MAX_OPERANDS): Set to 5.
1630 (MAX_MNEM_SIZE): Changed to 20.
1631
e210c36b
NC		 16322008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1633
1634 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1635
b1cc4aeb
PB		 16362008-03-09 Paul Brook <paul@codesourcery.com>
1637
1638 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1639
7e806470
PB		 16402008-03-04 Paul Brook <paul@codesourcery.com>
1641
1642 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1643 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1644 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1645
7b2185f9 16462008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1647 Nick Clifton <nickc@redhat.com>
1648
1649 PR 3134
1650 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1651 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1652 set.
af7329f0 1653
796d5313
NC		 16542008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1655
1656 * cr16.h (cr16_num_optab): Declared.
1657
d669d37f
NC		 16582008-02-14 Hakan Ardo <hakan@debian.org>
1659
1660 PR gas/2626
1661 * avr.h (AVR_ISA_2xxe): Define.
1662
e6429699
AN		 16632008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1664
1665 * mips.h: Update copyright.
1666 (INSN_CHIP_MASK): New macro.
1667 (INSN_OCTEON): New macro.
1668 (CPU_OCTEON): New macro.
1669 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1670
e210c36b
NC		 16712008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1672
1673 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1674
16752008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1676
1677 * avr.h (AVR_ISA_USB162): Add new opcode set.
1678 (AVR_ISA_AVR3): Likewise.
1679
350cc38d
MS		 16802007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1681
1682 * mips.h (INSN_LOONGSON_2E): New.
1683 (INSN_LOONGSON_2F): New.
1684 (CPU_LOONGSON_2E): New.
1685 (CPU_LOONGSON_2F): New.
1686 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1687
56950294
MS		 16882007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1689
1690 * mips.h (INSN_ISA*): Redefine certain values as an
1691 enumeration. Update comments.
1692 (mips_isa_table): New.
1693 (ISA_MIPS*): Redefine to match enumeration.
1694 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1695 values.
1696
c3d65c1c
BE		 16972007-08-08 Ben Elliston <bje@au.ibm.com>
1698
1699 * ppc.h (PPC_OPCODE_PPCPS): New.
1700
0fdaa005
L		 17012007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1702
1703 * m68k.h: Document j K & E.
1704
17052007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1706
1707 * cr16.h: New file for CR16 target.
1708
3896c469
AM		 17092007-05-02 Alan Modra <amodra@bigpond.net.au>
1710
1711 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1712
9a2e615a
NS		 17132007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1714
1715 * m68k.h (mcfisa_c): New.
1716 (mcfusp, mcf_mask): Adjust.
1717
b84bf58a
AM		 17182007-04-20 Alan Modra <amodra@bigpond.net.au>
1719
1720 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1721 (num_powerpc_operands): Declare.
1722 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1723 (PPC_OPERAND_PLUS1): Define.
1724
831480e9 17252007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1726
1727 * i386.h (REX_MODE64): Renamed to ...
1728 (REX_W): This.
1729 (REX_EXTX): Renamed to ...
1730 (REX_R): This.
1731 (REX_EXTY): Renamed to ...
1732 (REX_X): This.
1733 (REX_EXTZ): Renamed to ...
1734 (REX_B): This.
1735
0b1cf022
L		 17362007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1737
1738 * i386.h: Add entries from config/tc-i386.h and move tables
1739 to opcodes/i386-opc.h.
1740
d796c0ad
L		 17412007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1742
1743 * i386.h (FloatDR): Removed.
1744 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1745
30ac7323
AM		 17462007-03-01 Alan Modra <amodra@bigpond.net.au>
1747
1748 * spu-insns.h: Add soma double-float insns.
1749
8b082fb1 17502007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1751 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1752
1753 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1754 (INSN_DSPR2): Add flag for DSP R2 instructions.
1755 (M_BALIGN): New macro.
1756
4eed87de
AM		 17572007-02-14 Alan Modra <amodra@bigpond.net.au>
1758
1759 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1760 and Seg3ShortFrom with Shortform.
1761
fda592e8
L		 17622007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1763
1764 PR gas/4027
1765 * i386.h (i386_optab): Put the real "test" before the pseudo
1766 one.
1767
3bdcfdf4
KH		 17682007-01-08 Kazu Hirata <kazu@codesourcery.com>
1769
1770 * m68k.h (m68010up): OR fido_a.
1771
9840d27e
KH		 17722006-12-25 Kazu Hirata <kazu@codesourcery.com>
1773
1774 * m68k.h (fido_a): New.
1775
c629cdac
KH		 17762006-12-24 Kazu Hirata <kazu@codesourcery.com>
1777
1778 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1779 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1780 values.
1781
b7d9ef37
L		 17822006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1783
1784 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1785
b138abaa
NC		 17862006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1787
1788 * score-inst.h (enum score_insn_type): Add Insn_internal.
1789
e9f53129
AM		 17902006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1791 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1792 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1793 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1794 Alan Modra <amodra@bigpond.net.au>
1795
1796 * spu-insns.h: New file.
1797 * spu.h: New file.
1798
ede602d7
AM		 17992006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1800
1801 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1802
7918206c
MM		 18032006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1804
e4e42b45 1805 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1806 in amdfam10 architecture.
1807
ef05d495
L		 18082006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1809
1810 * i386.h: Replace CpuMNI with CpuSSSE3.
1811
2d447fca 18122006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1813 Joseph Myers <joseph@codesourcery.com>
1814 Ian Lance Taylor <ian@wasabisystems.com>
1815 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1816
1817 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1818
1c0d3aa6
NC		 18192006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1820
1821 * score-datadep.h: New file.
1822 * score-inst.h: New file.
1823
c2f0420e
L		 18242006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1825
1826 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1827 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1828 movdq2q and movq2dq.
1829
050dfa73
MM		 18302006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1831 Michael Meissner <michael.meissner@amd.com>
1832
1833 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1834
15965411
L		 18352006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1836
1837 * i386.h (i386_optab): Add "nop" with memory reference.
1838
46e883c5
L		 18392006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1840
1841 * i386.h (i386_optab): Update comment for 64bit NOP.
1842
9622b051
AM		 18432006-06-06 Ben Elliston <bje@au.ibm.com>
1844 Anton Blanchard <anton@samba.org>
1845
1846 * ppc.h (PPC_OPCODE_POWER6): Define.
1847 Adjust whitespace.
1848
a9e24354
TS		 18492006-06-05 Thiemo Seufer <ths@mips.com>
1850
e4e42b45 1851 * mips.h: Improve description of MT flags.
a9e24354 1852
a596001e
RS		 18532006-05-25 Richard Sandiford <richard@codesourcery.com>
1854
1855 * m68k.h (mcf_mask): Define.
1856
d43b4baf 18572006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1858 David Ung <davidu@mips.com>
d43b4baf
TS		 1859
1860 * mips.h (enum): Add macro M_CACHE_AB.
1861
39a7806d 18622006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1863 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1864 David Ung <davidu@mips.com>
1865
1866 * mips.h: Add INSN_SMARTMIPS define.
1867
9bcd4f99 18682006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1869 David Ung <davidu@mips.com>
9bcd4f99
TS		 1870
1871 * mips.h: Defines udi bits and masks. Add description of
1872 characters which may appear in the args field of udi
1873 instructions.
1874
ef0ee844
TS		 18752006-04-26 Thiemo Seufer <ths@networkno.de>
1876
1877 * mips.h: Improve comments describing the bitfield instruction
1878 fields.
1879
f7675147
L		 18802006-04-26 Julian Brown <julian@codesourcery.com>
1881
1882 * arm.h (FPU_VFP_EXT_V3): Define constant.
1883 (FPU_NEON_EXT_V1): Likewise.
1884 (FPU_VFP_HARD): Update.
1885 (FPU_VFP_V3): Define macro.
1886 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1887
ef0ee844 18882006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1889
1890 * avr.h (AVR_ISA_PWMx): New.
1891
2da12c60
NS		 18922006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1893
1894 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1895 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1896 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1897 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1898 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1899
0715c387
PB		 19002006-03-10 Paul Brook <paul@codesourcery.com>
1901
1902 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1903
34bdd094
DA		 19042006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1905
1906 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1907 first. Correct mask of bb "B" opcode.
1908
331d2d0d
L		 19092006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1910
1911 * i386.h (i386_optab): Support Intel Merom New Instructions.
1912
62b3e311
PB		 19132006-02-24 Paul Brook <paul@codesourcery.com>
1914
1915 * arm.h: Add V7 feature bits.
1916
59cf82fe
L		 19172006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1918
1919 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1920
e74cfd16
PB		 19212006-01-31 Paul Brook <paul@codesourcery.com>
1922 Richard Earnshaw <rearnsha@arm.com>
1923
1924 * arm.h: Use ARM_CPU_FEATURE.
1925 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1926 (arm_feature_set): Change to a structure.
1927 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1928 ARM_FEATURE): New macros.
1929
5b3f8a92
HPN		 19302005-12-07 Hans-Peter Nilsson <hp@axis.com>
1931
1932 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1933 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1934 (ADD_PC_INCR_OPCODE): Don't define.
1935
cb712a9e
L		 19362005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1937
1938 PR gas/1874
1939 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1940
0499d65b
TS		 19412005-11-14 David Ung <davidu@mips.com>
1942
1943 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1944 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1945 save/restore encoding of the args field.
1946
ea5ca089
DB		 19472005-10-28 Dave Brolley <brolley@redhat.com>
1948
1949 Contribute the following changes:
1950 2005-02-16 Dave Brolley <brolley@redhat.com>
1951
1952 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1953 cgen_isa_mask_* to cgen_bitset_*.
1954 * cgen.h: Likewise.
1955
16175d96
DB		 1956 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1957
1958 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1959 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1960 (CGEN_CPU_TABLE): Make isas a ponter.
1961
1962 2003-09-29 Dave Brolley <brolley@redhat.com>
1963
1964 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1965 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1966 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1967
1968 2002-12-13 Dave Brolley <brolley@redhat.com>
1969
1970 * cgen.h (symcat.h): #include it.
1971 (cgen-bitset.h): #include it.
1972 (CGEN_ATTR_VALUE_TYPE): Now a union.
1973 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1974 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1975 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1976 * cgen-bitset.h: New file.
1977
3c9b82ba
NC		 19782005-09-30 Catherine Moore <clm@cm00re.com>
1979
1980 * bfin.h: New file.
1981
6a2375c6
JB		 19822005-10-24 Jan Beulich <jbeulich@novell.com>
1983
1984 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1985 indirect operands.
1986
c06a12f8
DA		 19872005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1988
1989 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1990 Add FLAG_STRICT to pa10 ftest opcode.
1991
4d443107
DA		 19922005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1993
1994 * hppa.h (pa_opcodes): Remove lha entries.
1995
f0a3b40f
DA		 19962005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1997
1998 * hppa.h (FLAG_STRICT): Revise comment.
1999 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
2000 before corresponding pa11 opcodes. Add strict pa10 register-immediate
2001 entries for "fdc".
2002
e210c36b
NC		 20032005-09-30 Catherine Moore <clm@cm00re.com>
2004
2005 * bfin.h: New file.
2006
1b7e1362
DA		 20072005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2008
2009 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
2010
089b39de
CF		 20112005-09-06 Chao-ying Fu <fu@mips.com>
2012
2013 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
2014 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
2015 define.
2016 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
2017 (INSN_ASE_MASK): Update to include INSN_MT.
2018 (INSN_MT): New define for MT ASE.
2019
93c34b9b
CF		 20202005-08-25 Chao-ying Fu <fu@mips.com>
2021
2022 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
2023 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
2024 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
2025 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
2026 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
2027 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
2028 instructions.
2029 (INSN_DSP): New define for DSP ASE.
2030
848cf006
AM		 20312005-08-18 Alan Modra <amodra@bigpond.net.au>
2032
2033 * a29k.h: Delete.
2034
36ae0db3
DJ		 20352005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
2036
2037 * ppc.h (PPC_OPCODE_E300): Define.
2038
8c929562
MS		 20392005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
2040
2041 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
2042
f7b8cccc
DA		 20432005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2044
2045 PR gas/336
2046 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
2047 and pitlb.
2048
8b5328ac
JB		 20492005-07-27 Jan Beulich <jbeulich@novell.com>
2050
2051 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
2052 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
2053 Add movq-s as 64-bit variants of movd-s.
2054
f417d200
DA		 20552005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2056
18b3bdfc
DA		 2057 * hppa.h: Fix punctuation in comment.
2058
f417d200
DA		 2059 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
2060 implicit space-register addressing. Set space-register bits on opcodes
2061 using implicit space-register addressing. Add various missing pa20
2062 long-immediate opcodes. Remove various opcodes using implicit 3-bit
2063 space-register addressing. Use "fE" instead of "fe" in various
2064 fstw opcodes.
2065
9a145ce6
JB		 20662005-07-18 Jan Beulich <jbeulich@novell.com>
2067
2068 * i386.h (i386_optab): Operands of aam and aad are unsigned.
2069
90700ea2
L		 20702007-07-15 H.J. Lu <hongjiu.lu@intel.com>
2071
2072 * i386.h (i386_optab): Support Intel VMX Instructions.
2073
48f130a8
DA		 20742005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2075
2076 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2077
30123838
JB		 20782005-07-05 Jan Beulich <jbeulich@novell.com>
2079
2080 * i386.h (i386_optab): Add new insns.
2081
47b0e7ad
NC		 20822005-07-01 Nick Clifton <nickc@redhat.com>
2083
2084 * sparc.h: Add typedefs to structure declarations.
2085
b300c311
L		 20862005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2087
2088 PR 1013
2089 * i386.h (i386_optab): Update comments for 64bit addressing on
2090 mov. Allow 64bit addressing for mov and movq.
2091
2db495be
DA		 20922005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2093
2094 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2095 respectively, in various floating-point load and store patterns.
2096
caa05036
DA		 20972005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2098
2099 * hppa.h (FLAG_STRICT): Correct comment.
2100 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2101 PA 2.0 mneumonics when equivalent. Entries with cache control
2102 completers now require PA 1.1. Adjust whitespace.
2103
f4411256
AM		 21042005-05-19 Anton Blanchard <anton@samba.org>
2105
2106 * ppc.h (PPC_OPCODE_POWER5): Define.
2107
e172dbf8
NC		 21082005-05-10 Nick Clifton <nickc@redhat.com>
2109
2110 * Update the address and phone number of the FSF organization in
2111 the GPL notices in the following files:
2112 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2113 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2114 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2115 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2116 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2117 tic54x.h, tic80.h, v850.h, vax.h
2118
e44823cf
JB		 21192005-05-09 Jan Beulich <jbeulich@novell.com>
2120
2121 * i386.h (i386_optab): Add ht and hnt.
2122
791fe849
MK		 21232005-04-18 Mark Kettenis <kettenis@gnu.org>
2124
2125 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2126 Add xcrypt-ctr. Provide aliases without hyphens.
2127
faa7ef87
L		 21282005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2129
a63027e5
L		 2130 Moved from ../ChangeLog
2131
faa7ef87
L		 2132 2005-04-12 Paul Brook <paul@codesourcery.com>
2133 * m88k.h: Rename psr macros to avoid conflicts.
2134
2135 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2136 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2137 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2138 and ARM_ARCH_V6ZKT2.
2139
2140 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2141 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2142 Remove redundant instruction types.
2143 (struct argument): X_op - new field.
2144 (struct cst4_entry): Remove.
2145 (no_op_insn): Declare.
2146
2147 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2148 * crx.h (enum argtype): Rename types, remove unused types.
2149
2150 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2151 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2152 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2153 (enum operand_type): Rearrange operands, edit comments.
2154 replace us<N> with ui<N> for unsigned immediate.
2155 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2156 displacements (respectively).
2157 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2158 (instruction type): Add NO_TYPE_INS.
2159 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2160 (operand_entry): New field - 'flags'.
2161 (operand flags): New.
2162
2163 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2164 * crx.h (operand_type): Remove redundant types i3, i4,
2165 i5, i8, i12.
2166 Add new unsigned immediate types us3, us4, us5, us16.
2167
bc4bd9ab
MK		 21682005-04-12 Mark Kettenis <kettenis@gnu.org>
2169
2170 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2171 adjust them accordingly.
2172
373ff435
JB		 21732005-04-01 Jan Beulich <jbeulich@novell.com>
2174
2175 * i386.h (i386_optab): Add rdtscp.
2176
4cc91dba
L		 21772005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2178
2179 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 2180 between memory and segment register. Allow movq for moving between
2181 general-purpose register and segment register.
4cc91dba 2182
9ae09ff9
JB		 21832005-02-09 Jan Beulich <jbeulich@novell.com>
2184
2185 PR gas/707
2186 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2187 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2188 fnstsw.
2189
638e7a64
NS		 21902006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2191
2192 * m68k.h (m68008, m68ec030, m68882): Remove.
2193 (m68k_mask): New.
2194 (cpu_m68k, cpu_cf): New.
2195 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2196 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2197
90219bd0
AO		 21982005-01-25 Alexandre Oliva <aoliva@redhat.com>
2199
2200 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2201 * cgen.h (enum cgen_parse_operand_type): Add
2202 CGEN_PARSE_OPERAND_SYMBOLIC.
2203
239cb185
FF		 22042005-01-21 Fred Fish <fnf@specifixinc.com>
2205
2206 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2207 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2208 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2209
dc9a9f39
FF		 22102005-01-19 Fred Fish <fnf@specifixinc.com>
2211
2212 * mips.h (struct mips_opcode): Add new pinfo2 member.
2213 (INSN_ALIAS): New define for opcode table entries that are
2214 specific instances of another entry, such as 'move' for an 'or'
2215 with a zero operand.
2216 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2217 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2218
98e7aba8
ILT		 22192004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2220
2221 * mips.h (CPU_RM9000): Define.
2222 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2223
37edbb65
JB		 22242004-11-25 Jan Beulich <jbeulich@novell.com>
2225
2226 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2227 to/from test registers are illegal in 64-bit mode. Add missing
2228 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2229 (previously one had to explicitly encode a rex64 prefix). Re-enable
2230 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2231 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2232
22332004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2234
2235 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2236 available only with SSE2. Change the MMX additions introduced by SSE
2237 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2238 instructions by their now designated identifier (since combining i686
2239 and 3DNow! does not really imply 3DNow!A).
2240
f5c7edf4
AM		 22412004-11-19 Alan Modra <amodra@bigpond.net.au>
2242
2243 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2244 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2245
7499d566
NC		 22462004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2247 Vineet Sharma <vineets@noida.hcltech.com>
2248
2249 * maxq.h: New file: Disassembly information for the maxq port.
2250
bcb9eebe
L		 22512004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2252
2253 * i386.h (i386_optab): Put back "movzb".
2254
94bb3d38
HPN		 22552004-11-04 Hans-Peter Nilsson <hp@axis.com>
2256
2257 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2258 comments. Remove member cris_ver_sim. Add members
2259 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2260 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2261 (struct cris_support_reg, struct cris_cond15): New types.
2262 (cris_conds15): Declare.
2263 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2264 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2265 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2266 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2267 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2268 SIZE_FIELD_UNSIGNED.
2269
37edbb65 22702004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2271
2272 * i386.h (sldx_Suf): Remove.
2273 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2274 (q_FP): Define, implying no REX64.
2275 (x_FP, sl_FP): Imply FloatMF.
2276 (i386_optab): Split reg and mem forms of moving from segment registers
2277 so that the memory forms can ignore the 16-/32-bit operand size
2278 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2279 all non-floating-point instructions. Unite 32- and 64-bit forms of
2280 movsx, movzx, and movd. Adjust floating point operations for the above
2281 changes to the *FP macros. Add DefaultSize to floating point control
2282 insns operating on larger memory ranges. Remove left over comments
2283 hinting at certain insns being Intel-syntax ones where the ones
2284 actually meant are already gone.
2285
48c9f030
NC		 22862004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2287
2288 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2289 instruction type.
2290
0dd132b6
NC		 22912004-09-30 Paul Brook <paul@codesourcery.com>
2292
2293 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2294 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2295
23794b24
MM		 22962004-09-11 Theodore A. Roth <troth@openavr.org>
2297
2298 * avr.h: Add support for
2299 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2300
2a309db0
AM		 23012004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2302
2303 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2304
b18c562e
NC		 23052004-08-24 Dmitry Diky <diwil@spec.ru>
2306
2307 * msp430.h (msp430_opc): Add new instructions.
2308 (msp430_rcodes): Declare new instructions.
2309 (msp430_hcodes): Likewise..
2310
45d313cd
NC		 23112004-08-13 Nick Clifton <nickc@redhat.com>
2312
2313 PR/301
2314 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2315 processors.
2316
30d1c836
ML		 23172004-08-30 Michal Ludvig <mludvig@suse.cz>
2318
2319 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2320
9a45f1c2
L		 23212004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2322
2323 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2324
543613e9
NC		 23252004-07-21 Jan Beulich <jbeulich@novell.com>
2326
2327 * i386.h: Adjust instruction descriptions to better match the
2328 specification.
2329
b781e558
RE		 23302004-07-16 Richard Earnshaw <rearnsha@arm.com>
2331
2332 * arm.h: Remove all old content. Replace with architecture defines
2333 from gas/config/tc-arm.c.
2334
8577e690
AS		 23352004-07-09 Andreas Schwab <schwab@suse.de>
2336
2337 * m68k.h: Fix comment.
2338
1fe1f39c
NC		 23392004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2340
2341 * crx.h: New file.
2342
1d9f512f
AM		 23432004-06-24 Alan Modra <amodra@bigpond.net.au>
2344
2345 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2346
be8c092b
NC		 23472004-05-24 Peter Barada <peter@the-baradas.com>
2348
2349 * m68k.h: Add 'size' to m68k_opcode.
2350
6b6e92f4
NC		 23512004-05-05 Peter Barada <peter@the-baradas.com>
2352
2353 * m68k.h: Switch from ColdFire chip name to core variant.
2354
23552004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2356
2357 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2358 descriptions for new EMAC cases.
2359 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2360 handle Motorola MAC syntax.
2361 Allow disassembly of ColdFire V4e object files.
2362
fdd12ef3
AM		 23632004-03-16 Alan Modra <amodra@bigpond.net.au>
2364
2365 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2366
3922a64c
L		 23672004-03-12 Jakub Jelinek <jakub@redhat.com>
2368
2369 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2370
1f45d988
ML		 23712004-03-12 Michal Ludvig <mludvig@suse.cz>
2372
2373 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2374
0f10071e
ML		 23752004-03-12 Michal Ludvig <mludvig@suse.cz>
2376
2377 * i386.h (i386_optab): Added xstore/xcrypt insns.
2378
3255318a
NC		 23792004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2380
2381 * h8300.h (32bit ldc/stc): Add relaxing support.
2382
ca9a79a1 23832004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2384
ca9a79a1
NC		 2385 * h8300.h (BITOP): Pass MEMRELAX flag.
2386
875a0b14
NC		 23872004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2388
2389 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2390 except for the H8S.
252b5132 2391
c9e214e5 2392For older changes see ChangeLog-9103
252b5132 2393\f
b90efa5b 2394Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2395
2396Copying and distribution of this file, with or without modification,
2397are permitted in any medium without royalty provided the copyright
2398notice and this notice are preserved.
2399
252b5132 2400Local Variables:
c9e214e5
AM		 2401mode: change-log
2402left-margin: 8
2403fill-column: 74
252b5132
RH		 2404version-control: never
2405End:
GDB Binutils - Deliverables
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