[deliverable/binutils-gdb.git] / include / opcode / ChangeLog

2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	PR gas/336
 	* hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
	and pitlb.

2005-07-27  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add comment to movd. Use LongMem for all
	movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
	Add movq-s as 64-bit variants of movd-s.

2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* hppa.h: Fix punctuation in comment.

	* hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
	implicit space-register addressing.  Set space-register bits on opcodes
	using implicit space-register addressing.  Add various missing pa20
	long-immediate opcodes.  Remove various opcodes using implicit 3-bit
	space-register addressing.  Use "fE" instead of "fe" in various
	fstw opcodes.

2005-07-18  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Operands of aam and aad are unsigned.

2007-07-15  H.J. Lu <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Support Intel VMX Instructions.

2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.

2005-07-05  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add new insns.

2005-07-01  Nick Clifton  <nickc@redhat.com>

	* sparc.h: Add typedefs to structure declarations.

2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>

	PR 1013
	* i386.h (i386_optab): Update comments for 64bit addressing on
	mov. Allow 64bit addressing for mov and movq.

2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
	respectively, in various floating-point load and store patterns.

2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* hppa.h (FLAG_STRICT): Correct comment.
	(pa_opcodes): Update load and store entries to allow both PA 1.X and
	PA 2.0 mneumonics when equivalent.  Entries with cache control
	completers now require PA 1.1.  Adjust whitespace.

2005-05-19  Anton Blanchard  <anton@samba.org>

	* ppc.h (PPC_OPCODE_POWER5): Define.

2005-05-10  Nick Clifton  <nickc@redhat.com>

	* Update the address and phone number of the FSF organization in
	the GPL notices in the following files:
	a29k.h,	alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
	crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
	i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
	mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
	pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
	tic54x.h, tic80.h, v850.h, vax.h

2005-05-09  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add ht and hnt.

2005-04-18  Mark Kettenis  <kettenis@gnu.org>

	* i386.h: Insert hyphens into selected VIA PadLock extensions.
	Add xcrypt-ctr.  Provide aliases without hyphens.

2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>

	Moved from ../ChangeLog

	2005-04-12  Paul Brook  <paul@codesourcery.com>
	* m88k.h: Rename psr macros to avoid conflicts.

	2005-03-12  Zack Weinberg  <zack@codesourcery.com>
	* arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
	Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
	and ARM_ARCH_V6ZKT2.

	2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
	* crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
	Remove redundant instruction types.
	(struct argument): X_op - new field.
	(struct cst4_entry): Remove.
	(no_op_insn): Declare.

	2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
	* crx.h (enum argtype): Rename types, remove unused types.

	2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
	* crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
	(enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
	(enum operand_type): Rearrange operands, edit comments.
	replace us<N> with ui<N> for unsigned immediate.
	replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
	displacements (respectively).
	replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
	(instruction type): Add NO_TYPE_INS.
	(instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
	(operand_entry): New field - 'flags'.
	(operand flags): New.

	2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
	* crx.h (operand_type): Remove redundant types i3, i4,
	i5, i8, i12.
	Add new unsigned immediate types us3, us4, us5, us16.

2005-04-12  Mark Kettenis  <kettenis@gnu.org>

	* i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
	adjust them accordingly.

2005-04-01  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add rdtscp.

2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Don't allow the `l' suffix for moving
	between memory and segment register. Allow movq for moving between
	general-purpose register and segment register.

2005-02-09  Jan Beulich  <jbeulich@novell.com>

	PR gas/707
	* i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
	FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
	fnstsw.

2005-01-25  Alexandre Oliva  <aoliva@redhat.com>

	2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
	* cgen.h (enum cgen_parse_operand_type): Add
	CGEN_PARSE_OPERAND_SYMBOLIC.

2005-01-21  Fred Fish  <fnf@specifixinc.com>

	* mips.h: Change INSN_ALIAS to INSN2_ALIAS.
	Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
	Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.

2005-01-19  Fred Fish  <fnf@specifixinc.com>

	* mips.h (struct mips_opcode): Add new pinfo2 member.
	(INSN_ALIAS): New define for opcode table entries that are
	specific instances of another entry, such as 'move' for an 'or'
	with a zero operand.
	(INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
	(INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.

2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>

	* mips.h (CPU_RM9000): Define.
	(OPCODE_IS_MEMBER): Handle CPU_RM9000.

2004-11-25 Jan Beulich  <jbeulich@novell.com>

	* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
	to/from test registers are illegal in 64-bit mode. Add missing
	NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
	(previously one had to explicitly encode a rex64 prefix). Re-enable
	lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
	support it there. Add cmpxchg16b as per Intel's 64-bit documentation.

2004-11-23 Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
	available only with SSE2. Change the MMX additions introduced by SSE
	and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
	instructions by their now designated identifier (since combining i686
	and 3DNow! does not really imply 3DNow!A).

2004-11-19  Alan Modra  <amodra@bigpond.net.au>

	* msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
	struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.

2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
	    Vineet Sharma      <vineets@noida.hcltech.com>

	* maxq.h: New file: Disassembly information for the maxq port.

2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Put back "movzb".

2004-11-04  Hans-Peter Nilsson  <hp@axis.com>

	* cris.h (enum cris_insn_version_usage): Tweak formatting and
	comments.  Remove member cris_ver_sim.  Add members
	cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
	cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
	(struct cris_support_reg, struct cris_cond15): New types.
	(cris_conds15): Declare.
	(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
	(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
	(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
	(NOP_Z_BITS): Define in terms of NOP_OPCODE.
	(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
	SIZE_FIELD_UNSIGNED.

2004-11-04 Jan Beulich  <jbeulich@novell.com>

	* i386.h (sldx_Suf): Remove.
	(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
	(q_FP): Define, implying no REX64.
	(x_FP, sl_FP): Imply FloatMF.
	(i386_optab): Split reg and mem forms of moving from segment registers
	so that the memory forms can ignore the 16-/32-bit operand size
	distinction. Adjust a few others for Intel mode. Remove *FP uses from
	all non-floating-point instructions. Unite 32- and 64-bit forms of
	movsx, movzx, and movd. Adjust floating point operations for the above
	changes to the *FP macros. Add DefaultSize to floating point control
	insns operating on larger memory ranges. Remove left over comments
	hinting at certain insns being Intel-syntax ones where the ones
	actually meant are already gone.

2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>

	* crx.h: Add COPS_REG_INS - Coprocessor Special register
	instruction type.

2004-09-30  Paul Brook  <paul@codesourcery.com>

	* arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
	(ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.

2004-09-11  Theodore A. Roth  <troth@openavr.org>

	* avr.h: Add support for
	atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.

2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>

	* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.

2004-08-24  Dmitry Diky  <diwil@spec.ru>

	* msp430.h (msp430_opc): Add new instructions.
	(msp430_rcodes): Declare new instructions.
	(msp430_hcodes): Likewise..

2004-08-13  Nick Clifton  <nickc@redhat.com>

	PR/301
	* h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
	processors.

2004-08-30  Michal Ludvig  <mludvig@suse.cz>

	* i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.

2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.

2004-07-21  Jan Beulich  <jbeulich@novell.com>

	* i386.h: Adjust instruction descriptions to better match the
	specification.

2004-07-16  Richard Earnshaw  <rearnsha@arm.com>

	* arm.h: Remove all old content.  Replace with architecture defines
	from gas/config/tc-arm.c.

2004-07-09  Andreas Schwab  <schwab@suse.de>

	* m68k.h: Fix comment.

2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>

	* crx.h: New file.

2004-06-24  Alan Modra  <amodra@bigpond.net.au>

	* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.

2004-05-24  Peter Barada  <peter@the-baradas.com>

	* m68k.h: Add 'size' to m68k_opcode.

2004-05-05  Peter Barada  <peter@the-baradas.com>

	* m68k.h: Switch from ColdFire chip name to core variant.

2004-04-22  Peter Barada  <peter@the-baradas.com>

	* m68k.h: Add mcfmac/mcfemac definitions.  Update operand
	descriptions for new EMAC cases.
	Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
	handle Motorola MAC syntax.
	Allow disassembly of ColdFire V4e object files.

2004-03-16  Alan Modra  <amodra@bigpond.net.au>

	* ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.

2004-03-12  Jakub Jelinek  <jakub@redhat.com>

	* i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.

2004-03-12  Michal Ludvig  <mludvig@suse.cz>

	* i386.h (i386_optab): Added xstore as an alias for xstorerng.

2004-03-12  Michal Ludvig  <mludvig@suse.cz>

	* i386.h (i386_optab): Added xstore/xcrypt insns.

2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>

	* h8300.h (32bit ldc/stc): Add relaxing support.

2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>

	* h8300.h (BITOP): Pass MEMRELAX flag.

2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>

	* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
	except for the H8S.

For older changes see ChangeLog-9103
\f
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
f7b8cccc DA	1	2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
	2
	3	PR gas/336
	4	* hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
	5	and pitlb.
	6
8b5328ac JB	7	2005-07-27 Jan Beulich <jbeulich@novell.com>
	8
	9	* i386.h (i386_optab): Add comment to movd. Use LongMem for all
	10	movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
	11	Add movq-s as 64-bit variants of movd-s.
	12
f417d200 DA	13	2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
f417d200 DA	14
18b3bdfc DA	15	* hppa.h: Fix punctuation in comment.
18b3bdfc DA	16
f417d200 DA	17	* hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
	18	implicit space-register addressing. Set space-register bits on opcodes
	19	using implicit space-register addressing. Add various missing pa20
	20	long-immediate opcodes. Remove various opcodes using implicit 3-bit
	21	space-register addressing. Use "fE" instead of "fe" in various
	22	fstw opcodes.
	23
9a145ce6 JB	24	2005-07-18 Jan Beulich <jbeulich@novell.com>
	25
	26	* i386.h (i386_optab): Operands of aam and aad are unsigned.
	27
90700ea2 L	28	2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
	29
	30	* i386.h (i386_optab): Support Intel VMX Instructions.
	31
48f130a8 DA	32	2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
	33
	34	* hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
	35
30123838 JB	36	2005-07-05 Jan Beulich <jbeulich@novell.com>
	37
	38	* i386.h (i386_optab): Add new insns.
	39
47b0e7ad NC	40	2005-07-01 Nick Clifton <nickc@redhat.com>
	41
	42	* sparc.h: Add typedefs to structure declarations.
	43
b300c311 L	44	2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
	45
	46	PR 1013
	47	* i386.h (i386_optab): Update comments for 64bit addressing on
	48	mov. Allow 64bit addressing for mov and movq.
	49
2db495be DA	50	2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
	51
	52	* hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
	53	respectively, in various floating-point load and store patterns.
	54
caa05036 DA	55	2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
	56
	57	* hppa.h (FLAG_STRICT): Correct comment.
	58	(pa_opcodes): Update load and store entries to allow both PA 1.X and
	59	PA 2.0 mneumonics when equivalent. Entries with cache control
	60	completers now require PA 1.1. Adjust whitespace.
	61
f4411256 AM	62	2005-05-19 Anton Blanchard <anton@samba.org>
	63
	64	* ppc.h (PPC_OPCODE_POWER5): Define.
	65
e172dbf8 NC	66	2005-05-10 Nick Clifton <nickc@redhat.com>
	67
	68	* Update the address and phone number of the FSF organization in
	69	the GPL notices in the following files:
	70	a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
	71	crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
	72	i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
	73	mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
	74	pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
	75	tic54x.h, tic80.h, v850.h, vax.h
	76
e44823cf JB	77	2005-05-09 Jan Beulich <jbeulich@novell.com>
	78
	79	* i386.h (i386_optab): Add ht and hnt.
	80
791fe849 MK	81	2005-04-18 Mark Kettenis <kettenis@gnu.org>
	82
	83	* i386.h: Insert hyphens into selected VIA PadLock extensions.
	84	Add xcrypt-ctr. Provide aliases without hyphens.
	85
faa7ef87 L	86	2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
faa7ef87 L	87
a63027e5 L	88	Moved from ../ChangeLog
a63027e5 L	89
faa7ef87 L	90	2005-04-12 Paul Brook <paul@codesourcery.com>
	91	* m88k.h: Rename psr macros to avoid conflicts.
	92
	93	2005-03-12 Zack Weinberg <zack@codesourcery.com>
	94	* arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
	95	Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
	96	and ARM_ARCH_V6ZKT2.
	97
	98	2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
	99	* crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
	100	Remove redundant instruction types.
	101	(struct argument): X_op - new field.
	102	(struct cst4_entry): Remove.
	103	(no_op_insn): Declare.
	104
	105	2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
	106	* crx.h (enum argtype): Rename types, remove unused types.
	107
	108	2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
	109	* crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
	110	(enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
	111	(enum operand_type): Rearrange operands, edit comments.
	112	replace us<N> with ui<N> for unsigned immediate.
	113	replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
	114	displacements (respectively).
	115	replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
	116	(instruction type): Add NO_TYPE_INS.
	117	(instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
	118	(operand_entry): New field - 'flags'.
	119	(operand flags): New.
	120
	121	2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
	122	* crx.h (operand_type): Remove redundant types i3, i4,
	123	i5, i8, i12.
	124	Add new unsigned immediate types us3, us4, us5, us16.
	125
bc4bd9ab MK	126	2005-04-12 Mark Kettenis <kettenis@gnu.org>
	127
	128	* i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
	129	adjust them accordingly.
	130
373ff435 JB	131	2005-04-01 Jan Beulich <jbeulich@novell.com>
	132
	133	* i386.h (i386_optab): Add rdtscp.
	134
4cc91dba L	135	2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
	136
	137	* i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca AS	138	between memory and segment register. Allow movq for moving between
418a8fca AS	139	general-purpose register and segment register.
4cc91dba	140
9ae09ff9 JB	141	2005-02-09 Jan Beulich <jbeulich@novell.com>
	142
	143	PR gas/707
	144	* i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
	145	FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
	146	fnstsw.
	147
90219bd0 AO	148	2005-01-25 Alexandre Oliva <aoliva@redhat.com>
	149
	150	2004-11-10 Alexandre Oliva <aoliva@redhat.com>
	151	* cgen.h (enum cgen_parse_operand_type): Add
	152	CGEN_PARSE_OPERAND_SYMBOLIC.
	153
239cb185 FF	154	2005-01-21 Fred Fish <fnf@specifixinc.com>
	155
	156	* mips.h: Change INSN_ALIAS to INSN2_ALIAS.
	157	Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
	158	Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
	159
dc9a9f39 FF	160	2005-01-19 Fred Fish <fnf@specifixinc.com>
	161
	162	* mips.h (struct mips_opcode): Add new pinfo2 member.
	163	(INSN_ALIAS): New define for opcode table entries that are
	164	specific instances of another entry, such as 'move' for an 'or'
	165	with a zero operand.
	166	(INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
	167	(INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
	168
98e7aba8 ILT	169	2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
	170
	171	* mips.h (CPU_RM9000): Define.
	172	(OPCODE_IS_MEMBER): Handle CPU_RM9000.
	173
37edbb65 JB	174	2004-11-25 Jan Beulich <jbeulich@novell.com>
	175
	176	* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
	177	to/from test registers are illegal in 64-bit mode. Add missing
	178	NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
	179	(previously one had to explicitly encode a rex64 prefix). Re-enable
	180	lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
	181	support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
	182
	183	2004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e JB	184
	185	* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
	186	available only with SSE2. Change the MMX additions introduced by SSE
	187	and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
	188	instructions by their now designated identifier (since combining i686
	189	and 3DNow! does not really imply 3DNow!A).
	190
f5c7edf4 AM	191	2004-11-19 Alan Modra <amodra@bigpond.net.au>
	192
	193	* msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
	194	struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
	195
7499d566 NC	196	2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
	197	Vineet Sharma <vineets@noida.hcltech.com>
	198
	199	* maxq.h: New file: Disassembly information for the maxq port.
	200
bcb9eebe L	201	2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
	202
	203	* i386.h (i386_optab): Put back "movzb".
	204
94bb3d38 HPN	205	2004-11-04 Hans-Peter Nilsson <hp@axis.com>
	206
	207	* cris.h (enum cris_insn_version_usage): Tweak formatting and
	208	comments. Remove member cris_ver_sim. Add members
	209	cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
	210	cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
	211	(struct cris_support_reg, struct cris_cond15): New types.
	212	(cris_conds15): Declare.
	213	(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
	214	(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
	215	(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
	216	(NOP_Z_BITS): Define in terms of NOP_OPCODE.
	217	(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
	218	SIZE_FIELD_UNSIGNED.
	219
37edbb65	220	2004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a JB	221
	222	* i386.h (sldx_Suf): Remove.
	223	(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
	224	(q_FP): Define, implying no REX64.
	225	(x_FP, sl_FP): Imply FloatMF.
	226	(i386_optab): Split reg and mem forms of moving from segment registers
	227	so that the memory forms can ignore the 16-/32-bit operand size
	228	distinction. Adjust a few others for Intel mode. Remove *FP uses from
	229	all non-floating-point instructions. Unite 32- and 64-bit forms of
	230	movsx, movzx, and movd. Adjust floating point operations for the above
	231	changes to the *FP macros. Add DefaultSize to floating point control
	232	insns operating on larger memory ranges. Remove left over comments
	233	hinting at certain insns being Intel-syntax ones where the ones
	234	actually meant are already gone.
	235
48c9f030 NC	236	2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
	237
	238	* crx.h: Add COPS_REG_INS - Coprocessor Special register
	239	instruction type.
	240
0dd132b6 NC	241	2004-09-30 Paul Brook <paul@codesourcery.com>
	242
	243	* arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
	244	(ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
	245
23794b24 MM	246	2004-09-11 Theodore A. Roth <troth@openavr.org>
	247
	248	* avr.h: Add support for
	249	atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
	250
2a309db0 AM	251	2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
	252
	253	* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
	254
b18c562e NC	255	2004-08-24 Dmitry Diky <diwil@spec.ru>
	256
	257	* msp430.h (msp430_opc): Add new instructions.
	258	(msp430_rcodes): Declare new instructions.
	259	(msp430_hcodes): Likewise..
	260
45d313cd NC	261	2004-08-13 Nick Clifton <nickc@redhat.com>
	262
	263	PR/301
	264	* h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
	265	processors.
	266
30d1c836 ML	267	2004-08-30 Michal Ludvig <mludvig@suse.cz>
	268
	269	* i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
	270
9a45f1c2 L	271	2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
	272
	273	* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
	274
543613e9 NC	275	2004-07-21 Jan Beulich <jbeulich@novell.com>
	276
	277	* i386.h: Adjust instruction descriptions to better match the
	278	specification.
	279
b781e558 RE	280	2004-07-16 Richard Earnshaw <rearnsha@arm.com>
	281
	282	* arm.h: Remove all old content. Replace with architecture defines
	283	from gas/config/tc-arm.c.
	284
8577e690 AS	285	2004-07-09 Andreas Schwab <schwab@suse.de>
	286
	287	* m68k.h: Fix comment.
	288
1fe1f39c NC	289	2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
	290
	291	* crx.h: New file.
	292
1d9f512f AM	293	2004-06-24 Alan Modra <amodra@bigpond.net.au>
	294
	295	* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
	296
be8c092b NC	297	2004-05-24 Peter Barada <peter@the-baradas.com>
	298
	299	* m68k.h: Add 'size' to m68k_opcode.
	300
6b6e92f4 NC	301	2004-05-05 Peter Barada <peter@the-baradas.com>
	302
	303	* m68k.h: Switch from ColdFire chip name to core variant.
	304
	305	2004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b NC	306
	307	* m68k.h: Add mcfmac/mcfemac definitions. Update operand
	308	descriptions for new EMAC cases.
	309	Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
	310	handle Motorola MAC syntax.
	311	Allow disassembly of ColdFire V4e object files.
	312
fdd12ef3 AM	313	2004-03-16 Alan Modra <amodra@bigpond.net.au>
	314
	315	* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
	316
3922a64c L	317	2004-03-12 Jakub Jelinek <jakub@redhat.com>
	318
	319	* i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
	320
1f45d988 ML	321	2004-03-12 Michal Ludvig <mludvig@suse.cz>
	322
	323	* i386.h (i386_optab): Added xstore as an alias for xstorerng.
	324
0f10071e ML	325	2004-03-12 Michal Ludvig <mludvig@suse.cz>
	326
	327	* i386.h (i386_optab): Added xstore/xcrypt insns.
	328
3255318a NC	329	2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
	330
	331	* h8300.h (32bit ldc/stc): Add relaxing support.
	332
ca9a79a1	333	2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3	334
ca9a79a1 NC	335	* h8300.h (BITOP): Pass MEMRELAX flag.
ca9a79a1 NC	336
875a0b14 NC	337	2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
	338
	339	* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
	340	except for the H8S.
252b5132	341
c9e214e5	342	For older changes see ChangeLog-9103
252b5132 RH	343	\f
252b5132 RH	344	Local Variables:
c9e214e5 AM	345	mode: change-log
	346	left-margin: 8
	347	fill-column: 74
252b5132 RH	348	version-control: never
252b5132 RH	349	End: