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Remove support for the (deprecated) openrisc and or32 configurations and replace
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
73589c9d
CS		 12014-04-22 Christian Svensson <blue@cmd.nu>
2
3 * or32.h: Delete.
4
4b95cf5c
AM		 52014-03-05 Alan Modra <amodra@gmail.com>
6
7 Update copyright years.
8
e269fea7
AB		 92013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
10
11 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
12 microMIPS.
13
35c08157
KLC		 142013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
15 Wei-Cheng Wang <cole945@gmail.com>
16
17 * nds32.h: New file for Andes NDS32.
18
594d8fa8
MF		 192013-12-07 Mike Frysinger <vapier@gentoo.org>
20
21 * bfin.h: Remove +x file mode.
22
87b8eed7
YZ		 232013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
24
25 * aarch64.h (aarch64_pstatefields): Change element type to
26 aarch64_sys_reg.
27
c9fb6e58
YZ		 282013-11-18 Renlin Li <Renlin.Li@arm.com>
29
30 * arm.h (ARM_AEXT_V7VE): New define.
31 (ARM_ARCH_V7VE): New define.
32 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
33
a203d9b7
YZ		 342013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
35
36 Revert
37
38 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
39
40 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
41 (aarch64_sys_reg_writeonly_p): Ditto.
42
75468c93
YZ		 432013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
44
45 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
46 (aarch64_sys_reg_writeonly_p): Ditto.
47
49eec193
YZ		 482013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
49
50 * aarch64.h (aarch64_sys_reg): New typedef.
51 (aarch64_sys_regs): Change to define with the new type.
52 (aarch64_sys_reg_deprecated_p): Declare.
53
68a64283
YZ		 542013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
55
56 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
57 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
58
387a82f1
CF		 592013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
60
61 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
62 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
63 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
64 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
65 For MIPS, update extension character sequences after +.
66 (ASE_MSA): New define.
67 (ASE_MSA64): New define.
68 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
69 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
70 For microMIPS, update extension character sequences after +.
71
9aff4b7a
NC		 722013-08-23 Yuri Chornoivan <yurchor@ukr.net>
73
74 PR binutils/15834
75 * i960.h: Fix typos.
76
e423441d
RS		 772013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
78
79 * mips.h: Remove references to "+I" and imm2_expr.
80
5e0dc5ba
RS		 812013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
82
83 * mips.h (M_DEXT, M_DINS): Delete.
84
0f35dbc4
RS		 852013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
86
87 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
88 (mips_optional_operand_p): New function.
89
14daeee3
RS		 902013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
91 Richard Sandiford <rdsandiford@googlemail.com>
92
93 * mips.h: Document new VU0 operand characters.
94 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
95 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
96 (OP_REG_R5900_ACC): New mips_reg_operand_types.
97 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
98 (mips_vu0_channel_mask): Declare.
99
3ccad066
RS		 1002013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
101
102 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
103 (mips_int_operand_min, mips_int_operand_max): New functions.
104 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
105
fc76e730
RS		 1062013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
107
108 * mips.h (mips_decode_reg_operand): New function.
109 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
110 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
111 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
112 New macros.
113 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
114 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
115 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
116 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
117 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
118 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
119 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
120 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
121 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
122 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
123 macros to cover the gaps.
124 (INSN2_MOD_SP): Replace with...
125 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
126 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
127 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
128 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
129 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
130 Delete.
131
26545944
RS		 1322013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
133
134 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
135 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
136 (MIPS16_INSN_COND_BRANCH): Delete.
137
7e8b059b
L		 1382013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
139 Kirill Yukhin <kirill.yukhin@intel.com>
140 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
141
142 * i386.h (BND_PREFIX_OPCODE): New.
143
c3c07478
RS		 1442013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
145
146 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
147 OP_SAVE_RESTORE_LIST.
148 (decode_mips16_operand): Declare.
149
ab902481
RS		 1502013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
151
152 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
153 (mips_operand, mips_int_operand, mips_mapped_int_operand)
154 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
155 (mips_pcrel_operand): New structures.
156 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
157 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
158 (decode_mips_operand, decode_micromips_operand): Declare.
159
cc537e56
RS		 1602013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
161
162 * mips.h: Document MIPS16 "I" opcode.
163
f2ae14a1
RS		 1642013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
165
166 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
167 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
168 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
169 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
170 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
171 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
172 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
173 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
174 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
175 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
176 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
177 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
178 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
179 Rename to...
180 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
181 (M_USD_AB): ...these.
182
5c324c16
RS		 1832013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
184
185 * mips.h: Remove documentation of "[" and "]". Update documentation
186 of "k" and the MDMX formats.
187
23e69e47
RS		 1882013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
189
190 * mips.h: Update documentation of "+s" and "+S".
191
27c5c572
RS		 1922013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
193
194 * mips.h: Document "+i".
195
e76ff5ab
RS		 1962013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
197
198 * mips.h: Remove "mi" documentation. Update "mh" documentation.
199 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
200 Delete.
201 (INSN2_WRITE_GPR_MHI): Rename to...
202 (INSN2_WRITE_GPR_MH): ...this.
203
fa7616a4
RS		 2042013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
205
206 * mips.h: Remove documentation of "+D" and "+T".
207
18870af7
RS		 2082013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
209
210 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
211 Use "source" rather than "destination" for microMIPS "G".
212
833794fc
MR		 2132013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
214
215 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
216 values.
217
c3678916
RS		 2182013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
219
220 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
221
7f3c4072
CM		 2222013-06-17 Catherine Moore <clm@codesourcery.com>
223 Maciej W. Rozycki <macro@codesourcery.com>
224 Chao-Ying Fu <fu@mips.com>
225
226 * mips.h (OP_SH_EVAOFFSET): Define.
227 (OP_MASK_EVAOFFSET): Define.
228 (INSN_ASE_MASK): Delete.
229 (ASE_EVA): Define.
230 (M_CACHEE_AB, M_CACHEE_OB): New.
231 (M_LBE_OB, M_LBE_AB): New.
232 (M_LBUE_OB, M_LBUE_AB): New.
233 (M_LHE_OB, M_LHE_AB): New.
234 (M_LHUE_OB, M_LHUE_AB): New.
235 (M_LLE_AB, M_LLE_OB): New.
236 (M_LWE_OB, M_LWE_AB): New.
237 (M_LWLE_AB, M_LWLE_OB): New.
238 (M_LWRE_AB, M_LWRE_OB): New.
239 (M_PREFE_AB, M_PREFE_OB): New.
240 (M_SCE_AB, M_SCE_OB): New.
241 (M_SBE_OB, M_SBE_AB): New.
242 (M_SHE_OB, M_SHE_AB): New.
243 (M_SWE_OB, M_SWE_AB): New.
244 (M_SWLE_AB, M_SWLE_OB): New.
245 (M_SWRE_AB, M_SWRE_OB): New.
246 (MICROMIPSOP_SH_EVAOFFSET): Define.
247 (MICROMIPSOP_MASK_EVAOFFSET): Define.
248
0c8fe7cf
SL		 2492013-06-12 Sandra Loosemore <sandra@codesourcery.com>
250
251 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
252
c77c0862
RS		 2532013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
254
255 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
256
b015e599
AP		 2572013-05-09 Andrew Pinski <apinski@cavium.com>
258
259 * mips.h (OP_MASK_CODE10): Correct definition.
260 (OP_SH_CODE10): Likewise.
261 Add a comment that "+J" is used now for OP_*CODE10.
262 (INSN_ASE_MASK): Update.
263 (INSN_VIRT): New macro.
264 (INSN_VIRT64): New macro
265
13761a11
NC		 2662013-05-02 Nick Clifton <nickc@redhat.com>
267
268 * msp430.h: Add patterns for MSP430X instructions.
269
0afd1215
DM		 2702013-04-06 David S. Miller <davem@davemloft.net>
271
272 * sparc.h (F_PREFERRED): Define.
273 (F_PREF_ALIAS): Define.
274
41702d50
NC		 2752013-04-03 Nick Clifton <nickc@redhat.com>
276
277 * v850.h (V850_INVERSE_PCREL): Define.
278
e21e1a51
NC		 2792013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
280
281 PR binutils/15068
282 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
283
51dcdd4d
NC		 2842013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
285
286 PR binutils/15068
287 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
288 Add 16-bit opcodes.
289 * tic6xc-opcode-table.h: Add 16-bit insns.
290 * tic6x.h: Add support for 16-bit insns.
291
81f5558e
NC		 2922013-03-21 Michael Schewe <michael.schewe@gmx.net>
293
294 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
295 and mov.b/w/l Rs,@(d:32,ERd).
296
165546ad
NC		 2972013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
298
299 PR gas/15082
300 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
301 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
302 tic6x_operand_xregpair operand coding type.
303 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
304 opcode field, usu ORXREGD1324 for the src2 operand and remove the
305 TIC6X_FLAG_NO_CROSS.
306
795b8e6b
NC		 3072013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
308
309 PR gas/15095
310 * tic6x.h (enum tic6x_coding_method): Add
311 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
312 separately the msb and lsb of a register pair. This is needed to
313 encode the opcodes in the same way as TI assembler does.
314 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
315 and rsqrdp opcodes to use the new field coding types.
316
dd5181d5
KT		 3172013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
318
319 * arm.h (CRC_EXT_ARMV8): New constant.
320 (ARCH_CRC_ARMV8): New macro.
321
e60bb1dd
YZ		 3222013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
323
324 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
325
36591ba1
SL		 3262013-02-06 Sandra Loosemore <sandra@codesourcery.com>
327 Andrew Jenner <andrew@codesourcery.com>
328
329 Based on patches from Altera Corporation.
330
331 * nios2.h: New file.
332
e30181a5
YZ		 3332013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
334
335 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
336
0c9573f4
NC		 3372013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
338
339 PR gas/15069
340 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
341
981dc7f1
NC		 3422013-01-24 Nick Clifton <nickc@redhat.com>
343
344 * v850.h: Add e3v5 support.
345
f5555712
YZ		 3462013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
347
348 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
349
5817ffd1
PB		 3502013-01-10 Peter Bergner <bergner@vnet.ibm.com>
351
352 * ppc.h (PPC_OPCODE_POWER8): New define.
353 (PPC_OPCODE_HTM): Likewise.
354
a3c62988
NC		 3552013-01-10 Will Newton <will.newton@imgtec.com>
356
357 * metag.h: New file.
358
73335eae
NC		 3592013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
360
361 * cr16.h (make_instruction): Rename to cr16_make_instruction.
362 (match_opcode): Rename to cr16_match_opcode.
363
e407c74b
NC		 3642013-01-04 Juergen Urban <JuergenUrban@gmx.de>
365
366 * mips.h: Add support for r5900 instructions including lq and sq.
367
bab4becb
NC		 3682013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
369
370 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
371 (make_instruction,match_opcode): Added function prototypes.
372 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
373
776fc418
AM		 3742012-11-23 Alan Modra <amodra@gmail.com>
375
376 * ppc.h (ppc_parse_cpu): Update prototype.
377
f05682d4
DA		 3782012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
379
380 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
381 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
382
cfc72779
AK		 3832012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
384
385 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
386
b3e14eda
L		 3872012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
388
389 * ia64.h (ia64_opnd): Add new operand types.
390
2c63854f
DM		 3912012-08-21 David S. Miller <davem@davemloft.net>
392
393 * sparc.h (F3F4): New macro.
394
a06ea964 3952012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 396 Laurent Desnogues <laurent.desnogues@arm.com>
397 Jim MacArthur <jim.macarthur@arm.com>
398 Marcus Shawcroft <marcus.shawcroft@arm.com>
399 Nigel Stephens <nigel.stephens@arm.com>
400 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
401 Richard Earnshaw <rearnsha@arm.com>
402 Sofiane Naci <sofiane.naci@arm.com>
403 Tejas Belagod <tejas.belagod@arm.com>
404 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 405
406 * aarch64.h: New file.
407
35d0a169 4082012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 409 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 410
411 * mips.h (mips_opcode): Add the exclusions field.
412 (OPCODE_IS_MEMBER): Remove macro.
413 (cpu_is_member): New inline function.
414 (opcode_is_member): Likewise.
415
03f66e8a 4162012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 417 Catherine Moore <clm@codesourcery.com>
418 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 419
420 * mips.h: Document microMIPS DSP ASE usage.
421 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
422 microMIPS DSP ASE support.
423 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
424 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
425 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
426 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
427 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
428 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
429 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
430
9d7b4c23
MR		 4312012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
432
433 * mips.h: Fix a typo in description.
434
76e879f8
NC		 4352012-06-07 Georg-Johann Lay <avr@gjlay.de>
436
437 * avr.h: (AVR_ISA_XCH): New define.
438 (AVR_ISA_XMEGA): Use it.
439 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
440
6927f982
NC		 4412012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
442
443 * m68hc11.h: Add XGate definitions.
444 (struct m68hc11_opcode): Add xg_mask field.
445
b9c361e0
JL		 4462012-05-14 Catherine Moore <clm@codesourcery.com>
447 Maciej W. Rozycki <macro@codesourcery.com>
448 Rhonda Wittels <rhonda@codesourcery.com>
449
6927f982 450 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 451 (PPC_OP_SA): New macro.
452 (PPC_OP_SE_VLE): New macro.
453 (PPC_OP): Use a variable shift amount.
454 (powerpc_operand): Update comments.
455 (PPC_OPSHIFT_INV): New macro.
456 (PPC_OPERAND_CR): Replace with...
457 (PPC_OPERAND_CR_BIT): ...this and
458 (PPC_OPERAND_CR_REG): ...this.
459
460
f6c1a2d5
NC		 4612012-05-03 Sean Keys <skeys@ipdatasys.com>
462
463 * xgate.h: Header file for XGATE assembler.
464
ec668d69
DM		 4652012-04-27 David S. Miller <davem@davemloft.net>
466
6cda1326
DM		 467 * sparc.h: Document new arg code' )' for crypto RS3
468 immediates.
469
ec668d69
DM		 470 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
471 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
472 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
473 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
474 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
475 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
476 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
477 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
478 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
479 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
480 HWCAP_CBCOND, HWCAP_CRC32): New defines.
481
aea77599
AM		 4822012-03-10 Edmar Wienskoski <edmar@freescale.com>
483
484 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
485
1f42f8b3
AM		 4862012-02-27 Alan Modra <amodra@gmail.com>
487
488 * crx.h (cst4_map): Update declaration.
489
6f7be959
WL		 4902012-02-25 Walter Lee <walt@tilera.com>
491
492 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
493 TILEGX_OPC_LD_TLS.
494 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
495 TILEPRO_OPC_LW_TLS_SN.
496
42164a71
L		 4972012-02-08 H.J. Lu <hongjiu.lu@intel.com>
498
499 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
500 (XRELEASE_PREFIX_OPCODE): Likewise.
501
432233b3 5022011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 503 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 504
505 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
506 (INSN_OCTEON2): New macro.
507 (CPU_OCTEON2): New macro.
508 (OPCODE_IS_MEMBER): Add Octeon2.
509
dd6a37e7
AP		 5102011-11-29 Andrew Pinski <apinski@cavium.com>
511
512 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
513 (INSN_OCTEONP): New macro.
514 (CPU_OCTEONP): New macro.
515 (OPCODE_IS_MEMBER): Add Octeon+.
516 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
517
99c513f6
DD		 5182011-11-01 DJ Delorie <dj@redhat.com>
519
520 * rl78.h: New file.
521
26f85d7a
MR		 5222011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
523
524 * mips.h: Fix a typo in description.
525
9e8c70f9
DM		 5262011-09-21 David S. Miller <davem@davemloft.net>
527
528 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
529 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
530 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
531 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
532
dec0624d 5332011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 534 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 535
536 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
537 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
538 (INSN_ASE_MASK): Add the MCU bit.
539 (INSN_MCU): New macro.
540 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
541 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
542
2b0c8b40
MR		 5432011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
544
545 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
546 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
547 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
548 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
549 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
550 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
551 (INSN2_READ_GPR_MMN): Likewise.
552 (INSN2_READ_FPR_D): Change the bit used.
553 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
554 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
555 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
556 (INSN2_COND_BRANCH): Likewise.
557 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
558 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
559 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
560 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
561 (INSN2_MOD_GPR_MN): Likewise.
562
ea783ef3
DM		 5632011-08-05 David S. Miller <davem@davemloft.net>
564
565 * sparc.h: Document new format codes '4', '5', and '('.
566 (OPF_LOW4, RS3): New macros.
567
7c176fa8
MR		 5682011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
569
570 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
571 order of flags documented.
572
2309ddf2
MR		 5732011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
574
575 * mips.h: Clarify the description of microMIPS instruction
576 manipulation macros.
577 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
578
df58fc94 5792011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 580 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 581
582 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
583 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
584 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
585 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
586 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
587 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
588 (OP_MASK_RS3, OP_SH_RS3): Likewise.
589 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
590 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
591 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
592 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
593 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
594 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
595 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
596 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
597 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
598 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
599 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
600 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
601 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
602 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
603 (INSN_WRITE_GPR_S): New macro.
604 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
605 (INSN2_READ_FPR_D): Likewise.
606 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
607 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
608 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
609 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
610 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
611 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
612 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
613 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
614 (CPU_MICROMIPS): New macro.
615 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
616 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
617 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
618 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
619 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
620 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
621 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
622 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
623 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
624 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
625 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
626 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
627 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
628 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
629 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
630 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
631 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
632 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
633 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
634 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
635 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
636 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
637 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
638 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
639 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
640 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
641 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
642 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
643 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
644 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
645 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
646 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
647 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
648 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
649 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
650 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
651 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
652 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
653 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
654 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
655 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
656 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
657 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
658 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
659 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
660 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
661 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
662 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
663 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
664 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
665 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
666 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
667 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
668 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
669 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
670 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
671 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
672 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
673 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
674 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
675 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
676 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
677 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
678 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
679 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
680 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
681 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
682 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
683 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
684 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
685 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
686 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
687 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
688 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
689 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
690 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
691 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
692 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
693 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
694 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
695 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
696 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
697 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
698 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
699 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
700 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
701 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
702 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
703 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
704 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
705 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
706 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
707 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
708 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
709 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
710 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
711 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
712 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
713 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
714 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
715 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
716 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
717 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
718 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
719 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
720 (micromips_opcodes): New declaration.
721 (bfd_micromips_num_opcodes): Likewise.
722
bcd530a7
RS		 7232011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
724
725 * mips.h (INSN_TRAP): Rename to...
726 (INSN_NO_DELAY_SLOT): ... this.
727 (INSN_SYNC): Remove macro.
728
2dad5a91
EW		 7292011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
730
731 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
732 a duplicate of AVR_ISA_SPM.
733
5d73b1f1
NC		 7342011-07-01 Nick Clifton <nickc@redhat.com>
735
736 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
737
ef26d60e
MF		 7382011-06-18 Robin Getz <robin.getz@analog.com>
739
740 * bfin.h (is_macmod_signed): New func
741
8fb8dca7
MF		 7422011-06-18 Mike Frysinger <vapier@gentoo.org>
743
744 * bfin.h (is_macmod_pmove): Add missing space before func args.
745 (is_macmod_hmove): Likewise.
746
aa137e4d
NC		 7472011-06-13 Walter Lee <walt@tilera.com>
748
749 * tilegx.h: New file.
750 * tilepro.h: New file.
751
3b2f0793
PB		 7522011-05-31 Paul Brook <paul@codesourcery.com>
753
aa137e4d
NC		 754 * arm.h (ARM_ARCH_V7R_IDIV): Define.
755
7562011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
757
758 * s390.h: Replace S390_OPERAND_REG_EVEN with
759 S390_OPERAND_REG_PAIR.
760
7612011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
762
763 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 764
ac7f631b
NC		 7652011-04-18 Julian Brown <julian@codesourcery.com>
766
767 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
768
84701018
NC		 7692011-04-11 Dan McDonald <dan@wellkeeper.com>
770
771 PR gas/12296
772 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
773
8cc66334
EW		 7742011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
775
776 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
777 New instruction set flags.
778 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
779
3eebd5eb
MR		 7802011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
781
782 * mips.h (M_PREF_AB): New enum value.
783
26bb3ddd
MF		 7842011-02-12 Mike Frysinger <vapier@gentoo.org>
785
89c0d58c
MR		 786 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
787 M_IU): Define.
788 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 789
dd76fcb8
MF		 7902011-02-11 Mike Frysinger <vapier@gentoo.org>
791
792 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
793
98d23bef
BS		 7942011-02-04 Bernd Schmidt <bernds@codesourcery.com>
795
796 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
797 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
798
3c853d93
DA		 7992010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
800
801 PR gas/11395
802 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
803 "bb" entries.
804
79676006
DA		 8052010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
806
807 PR gas/11395
808 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
809
1bec78e9
RS		 8102010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
811
812 * mips.h: Update commentary after last commit.
813
98675402
RS		 8142010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
815
816 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
817 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
818 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
819
aa137e4d
NC		 8202010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
821
822 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
823
435b94a4
RS		 8242010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
825
826 * mips.h: Fix previous commit.
827
d051516a
NC		 8282010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
829
830 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
831 (INSN_LOONGSON_3A): Clear bit 31.
832
251665fc
MGD		 8332010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
834
835 PR gas/12198
836 * arm.h (ARM_AEXT_V6M_ONLY): New define.
837 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
838 (ARM_ARCH_V6M_ONLY): New define.
839
fd503541
NC		 8402010-11-11 Mingming Sun <mingm.sun@gmail.com>
841
842 * mips.h (INSN_LOONGSON_3A): Defined.
843 (CPU_LOONGSON_3A): Defined.
844 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
845
4469d2be
AM		 8462010-10-09 Matt Rice <ratmice@gmail.com>
847
848 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
849 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
850
90ec0d68
MGD		 8512010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
852
853 * arm.h (ARM_EXT_VIRT): New define.
854 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
855 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
856 Extensions.
857
eea54501 8582010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 859
eea54501
MGD		 860 * arm.h (ARM_AEXT_ADIV): New define.
861 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
862
b2a5fbdc
MGD		 8632010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
864
865 * arm.h (ARM_EXT_OS): New define.
866 (ARM_AEXT_V6SM): Likewise.
867 (ARM_ARCH_V6SM): Likewise.
868
60e5ef9f
MGD		 8692010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
870
871 * arm.h (ARM_EXT_MP): Add.
872 (ARM_ARCH_V7A_MP): Likewise.
873
73a63ccf
MF		 8742010-09-22 Mike Frysinger <vapier@gentoo.org>
875
876 * bfin.h: Declare pseudoChr structs/defines.
877
ee99860a
MF		 8782010-09-21 Mike Frysinger <vapier@gentoo.org>
879
880 * bfin.h: Strip trailing whitespace.
881
f9c7014e
DD		 8822010-07-29 DJ Delorie <dj@redhat.com>
883
884 * rx.h (RX_Operand_Type): Add TwoReg.
885 (RX_Opcode_ID): Remove ediv and ediv2.
886
93378652
DD		 8872010-07-27 DJ Delorie <dj@redhat.com>
888
889 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
890
1cd986c5
NC		 8912010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
892 Ina Pandit <ina.pandit@kpitcummins.com>
893
894 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
895 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
896 PROCESSOR_V850E2_ALL.
897 Remove PROCESSOR_V850EA support.
898 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
899 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
900 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
901 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
902 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
903 V850_OPERAND_PERCENT.
904 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
905 V850_NOT_R0.
906 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
907 and V850E_PUSH_POP
908
9a2c7088
MR		 9092010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
910
911 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
912 (MIPS16_INSN_BRANCH): Rename to...
913 (MIPS16_INSN_COND_BRANCH): ... this.
914
bdc70b4a
AM		 9152010-07-03 Alan Modra <amodra@gmail.com>
916
917 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
918 Renumber other PPC_OPCODE defines.
919
f2bae120
AM		 9202010-07-03 Alan Modra <amodra@gmail.com>
921
922 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
923
360cfc9c
AM		 9242010-06-29 Alan Modra <amodra@gmail.com>
925
926 * maxq.h: Delete file.
927
e01d869a
AM		 9282010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
929
930 * ppc.h (PPC_OPCODE_E500): Define.
931
f79e2745
CM		 9322010-05-26 Catherine Moore <clm@codesourcery.com>
933
934 * opcode/mips.h (INSN_MIPS16): Remove.
935
2462afa1
JM		 9362010-04-21 Joseph Myers <joseph@codesourcery.com>
937
938 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
939
e4e42b45
NC		 9402010-04-15 Nick Clifton <nickc@redhat.com>
941
942 * alpha.h: Update copyright notice to use GPLv3.
943 * arc.h: Likewise.
944 * arm.h: Likewise.
945 * avr.h: Likewise.
946 * bfin.h: Likewise.
947 * cgen.h: Likewise.
948 * convex.h: Likewise.
949 * cr16.h: Likewise.
950 * cris.h: Likewise.
951 * crx.h: Likewise.
952 * d10v.h: Likewise.
953 * d30v.h: Likewise.
954 * dlx.h: Likewise.
955 * h8300.h: Likewise.
956 * hppa.h: Likewise.
957 * i370.h: Likewise.
958 * i386.h: Likewise.
959 * i860.h: Likewise.
960 * i960.h: Likewise.
961 * ia64.h: Likewise.
962 * m68hc11.h: Likewise.
963 * m68k.h: Likewise.
964 * m88k.h: Likewise.
965 * maxq.h: Likewise.
966 * mips.h: Likewise.
967 * mmix.h: Likewise.
968 * mn10200.h: Likewise.
969 * mn10300.h: Likewise.
970 * msp430.h: Likewise.
971 * np1.h: Likewise.
972 * ns32k.h: Likewise.
973 * or32.h: Likewise.
974 * pdp11.h: Likewise.
975 * pj.h: Likewise.
976 * pn.h: Likewise.
977 * ppc.h: Likewise.
978 * pyr.h: Likewise.
979 * rx.h: Likewise.
980 * s390.h: Likewise.
981 * score-datadep.h: Likewise.
982 * score-inst.h: Likewise.
983 * sparc.h: Likewise.
984 * spu-insns.h: Likewise.
985 * spu.h: Likewise.
986 * tic30.h: Likewise.
987 * tic4x.h: Likewise.
988 * tic54x.h: Likewise.
989 * tic80.h: Likewise.
990 * v850.h: Likewise.
991 * vax.h: Likewise.
992
40b36596
JM		 9932010-03-25 Joseph Myers <joseph@codesourcery.com>
994
995 * tic6x-control-registers.h, tic6x-insn-formats.h,
996 tic6x-opcode-table.h, tic6x.h: New.
997
c67a084a
NC		 9982010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
999
1000 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1001
466ef64f
AM		 10022010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1003
1004 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1005
1319d143
L		 10062010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1007
1008 * ia64.h (ia64_find_opcode): Remove argument name.
1009 (ia64_find_next_opcode): Likewise.
1010 (ia64_dis_opcode): Likewise.
1011 (ia64_free_opcode): Likewise.
1012 (ia64_find_dependency): Likewise.
1013
1fbb9298
DE		 10142009-11-22 Doug Evans <dje@sebabeach.org>
1015
1016 * cgen.h: Include bfd_stdint.h.
1017 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1018
ada65aa3
PB		 10192009-11-18 Paul Brook <paul@codesourcery.com>
1020
1021 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1022
9e3c6df6
PB		 10232009-11-17 Paul Brook <paul@codesourcery.com>
1024 Daniel Jacobowitz <dan@codesourcery.com>
1025
1026 * arm.h (ARM_EXT_V6_DSP): Define.
1027 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1028 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1029
0d734b5d
DD		 10302009-11-04 DJ Delorie <dj@redhat.com>
1031
1032 * rx.h (rx_decode_opcode) (mvtipl): Add.
1033 (mvtcp, mvfcp, opecp): Remove.
1034
62f3b8c8
PB		 10352009-11-02 Paul Brook <paul@codesourcery.com>
1036
1037 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1038 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1039 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1040 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1041 FPU_ARCH_NEON_VFP_V4): Define.
1042
ac1e9eca
DE		 10432009-10-23 Doug Evans <dje@sebabeach.org>
1044
1045 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1046 * cgen.h: Update. Improve multi-inclusion macro name.
1047
9fe54b1c
PB		 10482009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1049
1050 * ppc.h (PPC_OPCODE_476): Define.
1051
634b50f2
PB		 10522009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1053
1054 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1055
c7927a3c
NC		 10562009-09-29 DJ Delorie <dj@redhat.com>
1057
1058 * rx.h: New file.
1059
b961e85b
AM		 10602009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1061
1062 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1063
e0d602ec
BE		 10642009-09-21 Ben Elliston <bje@au.ibm.com>
1065
1066 * ppc.h (PPC_OPCODE_PPCA2): New.
1067
96d56e9f
NC		 10682009-09-05 Martin Thuresson <martin@mtme.org>
1069
1070 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1071
d3ce72d0
NC		 10722009-08-29 Martin Thuresson <martin@mtme.org>
1073
1074 * tic30.h (template): Rename type template to
1075 insn_template. Updated code to use new name.
1076 * tic54x.h (template): Rename type template to
1077 insn_template.
1078
824b28db
NH		 10792009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1080
1081 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1082
f865a31d
AG		 10832009-06-11 Anthony Green <green@moxielogic.com>
1084
1085 * moxie.h (MOXIE_F3_PCREL): Define.
1086 (moxie_form3_opc_info): Grow.
1087
0e7c7f11
AG		 10882009-06-06 Anthony Green <green@moxielogic.com>
1089
1090 * moxie.h (MOXIE_F1_M): Define.
1091
20135e4c
NC		 10922009-04-15 Anthony Green <green@moxielogic.com>
1093
1094 * moxie.h: Created.
1095
bcb012d3
DD		 10962009-04-06 DJ Delorie <dj@redhat.com>
1097
1098 * h8300.h: Add relaxation attributes to MOVA opcodes.
1099
69fe9ce5
AM		 11002009-03-10 Alan Modra <amodra@bigpond.net.au>
1101
1102 * ppc.h (ppc_parse_cpu): Declare.
1103
c3b7224a
NC		 11042009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1105
1106 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1107 and _IMM11 for mbitclr and mbitset.
1108 * score-datadep.h: Update dependency information.
1109
066be9f7
PB		 11102009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1111
1112 * ppc.h (PPC_OPCODE_POWER7): New.
1113
fedc618e
DE		 11142009-02-06 Doug Evans <dje@google.com>
1115
1116 * i386.h: Add comment regarding sse* insns and prefixes.
1117
52b6b6b9
JM		 11182009-02-03 Sandip Matte <sandip@rmicorp.com>
1119
1120 * mips.h (INSN_XLR): Define.
1121 (INSN_CHIP_MASK): Update.
1122 (CPU_XLR): Define.
1123 (OPCODE_IS_MEMBER): Update.
1124 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1125
35669430
DE		 11262009-01-28 Doug Evans <dje@google.com>
1127
1128 * opcode/i386.h: Add multiple inclusion protection.
1129 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1130 (EDI_REG_NUM): New macros.
1131 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1132 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1133 (REX_PREFIX_P): New macro.
35669430 1134
1cb0a767
PB		 11352009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1136
1137 * ppc.h (struct powerpc_opcode): New field "deprecated".
1138 (PPC_OPCODE_NOPOWER4): Delete.
1139
3aa3176b
TS		 11402008-11-28 Joshua Kinard <kumba@gentoo.org>
1141
1142 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1143 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1144
8e79c3df
CM		 11452008-11-18 Catherine Moore <clm@codesourcery.com>
1146
1147 * arm.h (FPU_NEON_FP16): New.
1148 (FPU_ARCH_NEON_FP16): New.
1149
de9a3e51
CF		 11502008-11-06 Chao-ying Fu <fu@mips.com>
1151
1152 * mips.h: Doucument '1' for 5-bit sync type.
1153
1ca35711
L		 11542008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1155
1156 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1157 IA64_RS_CR.
1158
9b4e5766
PB		 11592008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1160
1161 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1162
081ba1b3
AM		 11632008-07-30 Michael J. Eager <eager@eagercon.com>
1164
1165 * ppc.h (PPC_OPCODE_405): Define.
1166 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1167
fa452fa6
PB		 11682008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1169
1170 * ppc.h (ppc_cpu_t): New typedef.
1171 (struct powerpc_opcode <flags>): Use it.
1172 (struct powerpc_operand <insert, extract>): Likewise.
1173 (struct powerpc_macro <flags>): Likewise.
1174
bb35fb24
NC		 11752008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1176
1177 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1178 Update comment before MIPS16 field descriptors to mention MIPS16.
1179 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1180 BBIT.
1181 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1182 New bit masks and shift counts for cins and exts.
1183
dd3cbb7e
NC		 1184 * mips.h: Document new field descriptors +Q.
1185 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1186
d0799671
AN		 11872008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1188
9aff4b7a 1189 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1190 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1191
19a6653c
AM		 11922008-04-14 Edmar Wienskoski <edmar@freescale.com>
1193
1194 * ppc.h: (PPC_OPCODE_E500MC): New.
1195
c0f3af97
L		 11962008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1197
1198 * i386.h (MAX_OPERANDS): Set to 5.
1199 (MAX_MNEM_SIZE): Changed to 20.
1200
e210c36b
NC		 12012008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1202
1203 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1204
b1cc4aeb
PB		 12052008-03-09 Paul Brook <paul@codesourcery.com>
1206
1207 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1208
7e806470
PB		 12092008-03-04 Paul Brook <paul@codesourcery.com>
1210
1211 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1212 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1213 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1214
7b2185f9 12152008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1216 Nick Clifton <nickc@redhat.com>
1217
1218 PR 3134
1219 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1220 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1221 set.
af7329f0 1222
796d5313
NC		 12232008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1224
1225 * cr16.h (cr16_num_optab): Declared.
1226
d669d37f
NC		 12272008-02-14 Hakan Ardo <hakan@debian.org>
1228
1229 PR gas/2626
1230 * avr.h (AVR_ISA_2xxe): Define.
1231
e6429699
AN		 12322008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1233
1234 * mips.h: Update copyright.
1235 (INSN_CHIP_MASK): New macro.
1236 (INSN_OCTEON): New macro.
1237 (CPU_OCTEON): New macro.
1238 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1239
e210c36b
NC		 12402008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1241
1242 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1243
12442008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1245
1246 * avr.h (AVR_ISA_USB162): Add new opcode set.
1247 (AVR_ISA_AVR3): Likewise.
1248
350cc38d
MS		 12492007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1250
1251 * mips.h (INSN_LOONGSON_2E): New.
1252 (INSN_LOONGSON_2F): New.
1253 (CPU_LOONGSON_2E): New.
1254 (CPU_LOONGSON_2F): New.
1255 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1256
56950294
MS		 12572007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1258
1259 * mips.h (INSN_ISA*): Redefine certain values as an
1260 enumeration. Update comments.
1261 (mips_isa_table): New.
1262 (ISA_MIPS*): Redefine to match enumeration.
1263 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1264 values.
1265
c3d65c1c
BE		 12662007-08-08 Ben Elliston <bje@au.ibm.com>
1267
1268 * ppc.h (PPC_OPCODE_PPCPS): New.
1269
0fdaa005
L		 12702007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1271
1272 * m68k.h: Document j K & E.
1273
12742007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1275
1276 * cr16.h: New file for CR16 target.
1277
3896c469
AM		 12782007-05-02 Alan Modra <amodra@bigpond.net.au>
1279
1280 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1281
9a2e615a
NS		 12822007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1283
1284 * m68k.h (mcfisa_c): New.
1285 (mcfusp, mcf_mask): Adjust.
1286
b84bf58a
AM		 12872007-04-20 Alan Modra <amodra@bigpond.net.au>
1288
1289 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1290 (num_powerpc_operands): Declare.
1291 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1292 (PPC_OPERAND_PLUS1): Define.
1293
831480e9 12942007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1295
1296 * i386.h (REX_MODE64): Renamed to ...
1297 (REX_W): This.
1298 (REX_EXTX): Renamed to ...
1299 (REX_R): This.
1300 (REX_EXTY): Renamed to ...
1301 (REX_X): This.
1302 (REX_EXTZ): Renamed to ...
1303 (REX_B): This.
1304
0b1cf022
L		 13052007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1306
1307 * i386.h: Add entries from config/tc-i386.h and move tables
1308 to opcodes/i386-opc.h.
1309
d796c0ad
L		 13102007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1311
1312 * i386.h (FloatDR): Removed.
1313 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1314
30ac7323
AM		 13152007-03-01 Alan Modra <amodra@bigpond.net.au>
1316
1317 * spu-insns.h: Add soma double-float insns.
1318
8b082fb1 13192007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1320 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1321
1322 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1323 (INSN_DSPR2): Add flag for DSP R2 instructions.
1324 (M_BALIGN): New macro.
1325
4eed87de
AM		 13262007-02-14 Alan Modra <amodra@bigpond.net.au>
1327
1328 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1329 and Seg3ShortFrom with Shortform.
1330
fda592e8
L		 13312007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1332
1333 PR gas/4027
1334 * i386.h (i386_optab): Put the real "test" before the pseudo
1335 one.
1336
3bdcfdf4
KH		 13372007-01-08 Kazu Hirata <kazu@codesourcery.com>
1338
1339 * m68k.h (m68010up): OR fido_a.
1340
9840d27e
KH		 13412006-12-25 Kazu Hirata <kazu@codesourcery.com>
1342
1343 * m68k.h (fido_a): New.
1344
c629cdac
KH		 13452006-12-24 Kazu Hirata <kazu@codesourcery.com>
1346
1347 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1348 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1349 values.
1350
b7d9ef37
L		 13512006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1352
1353 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1354
b138abaa
NC		 13552006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1356
1357 * score-inst.h (enum score_insn_type): Add Insn_internal.
1358
e9f53129
AM		 13592006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1360 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1361 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1362 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1363 Alan Modra <amodra@bigpond.net.au>
1364
1365 * spu-insns.h: New file.
1366 * spu.h: New file.
1367
ede602d7
AM		 13682006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1369
1370 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1371
7918206c
MM		 13722006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1373
e4e42b45 1374 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1375 in amdfam10 architecture.
1376
ef05d495
L		 13772006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1378
1379 * i386.h: Replace CpuMNI with CpuSSSE3.
1380
2d447fca 13812006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1382 Joseph Myers <joseph@codesourcery.com>
1383 Ian Lance Taylor <ian@wasabisystems.com>
1384 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1385
1386 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1387
1c0d3aa6
NC		 13882006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1389
1390 * score-datadep.h: New file.
1391 * score-inst.h: New file.
1392
c2f0420e
L		 13932006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1394
1395 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1396 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1397 movdq2q and movq2dq.
1398
050dfa73
MM		 13992006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1400 Michael Meissner <michael.meissner@amd.com>
1401
1402 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1403
15965411
L		 14042006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1405
1406 * i386.h (i386_optab): Add "nop" with memory reference.
1407
46e883c5
L		 14082006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1409
1410 * i386.h (i386_optab): Update comment for 64bit NOP.
1411
9622b051
AM		 14122006-06-06 Ben Elliston <bje@au.ibm.com>
1413 Anton Blanchard <anton@samba.org>
1414
1415 * ppc.h (PPC_OPCODE_POWER6): Define.
1416 Adjust whitespace.
1417
a9e24354
TS		 14182006-06-05 Thiemo Seufer <ths@mips.com>
1419
e4e42b45 1420 * mips.h: Improve description of MT flags.
a9e24354 1421
a596001e
RS		 14222006-05-25 Richard Sandiford <richard@codesourcery.com>
1423
1424 * m68k.h (mcf_mask): Define.
1425
d43b4baf 14262006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1427 David Ung <davidu@mips.com>
d43b4baf
TS		 1428
1429 * mips.h (enum): Add macro M_CACHE_AB.
1430
39a7806d 14312006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1432 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1433 David Ung <davidu@mips.com>
1434
1435 * mips.h: Add INSN_SMARTMIPS define.
1436
9bcd4f99 14372006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1438 David Ung <davidu@mips.com>
9bcd4f99
TS		 1439
1440 * mips.h: Defines udi bits and masks. Add description of
1441 characters which may appear in the args field of udi
1442 instructions.
1443
ef0ee844
TS		 14442006-04-26 Thiemo Seufer <ths@networkno.de>
1445
1446 * mips.h: Improve comments describing the bitfield instruction
1447 fields.
1448
f7675147
L		 14492006-04-26 Julian Brown <julian@codesourcery.com>
1450
1451 * arm.h (FPU_VFP_EXT_V3): Define constant.
1452 (FPU_NEON_EXT_V1): Likewise.
1453 (FPU_VFP_HARD): Update.
1454 (FPU_VFP_V3): Define macro.
1455 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1456
ef0ee844 14572006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1458
1459 * avr.h (AVR_ISA_PWMx): New.
1460
2da12c60
NS		 14612006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1462
1463 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1464 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1465 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1466 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1467 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1468
0715c387
PB		 14692006-03-10 Paul Brook <paul@codesourcery.com>
1470
1471 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1472
34bdd094
DA		 14732006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1474
1475 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1476 first. Correct mask of bb "B" opcode.
1477
331d2d0d
L		 14782006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1479
1480 * i386.h (i386_optab): Support Intel Merom New Instructions.
1481
62b3e311
PB		 14822006-02-24 Paul Brook <paul@codesourcery.com>
1483
1484 * arm.h: Add V7 feature bits.
1485
59cf82fe
L		 14862006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1487
1488 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1489
e74cfd16
PB		 14902006-01-31 Paul Brook <paul@codesourcery.com>
1491 Richard Earnshaw <rearnsha@arm.com>
1492
1493 * arm.h: Use ARM_CPU_FEATURE.
1494 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1495 (arm_feature_set): Change to a structure.
1496 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1497 ARM_FEATURE): New macros.
1498
5b3f8a92
HPN		 14992005-12-07 Hans-Peter Nilsson <hp@axis.com>
1500
1501 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1502 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1503 (ADD_PC_INCR_OPCODE): Don't define.
1504
cb712a9e
L		 15052005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1506
1507 PR gas/1874
1508 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1509
0499d65b
TS		 15102005-11-14 David Ung <davidu@mips.com>
1511
1512 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1513 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1514 save/restore encoding of the args field.
1515
ea5ca089
DB		 15162005-10-28 Dave Brolley <brolley@redhat.com>
1517
1518 Contribute the following changes:
1519 2005-02-16 Dave Brolley <brolley@redhat.com>
1520
1521 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1522 cgen_isa_mask_* to cgen_bitset_*.
1523 * cgen.h: Likewise.
1524
16175d96
DB		 1525 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1526
1527 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1528 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1529 (CGEN_CPU_TABLE): Make isas a ponter.
1530
1531 2003-09-29 Dave Brolley <brolley@redhat.com>
1532
1533 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1534 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1535 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1536
1537 2002-12-13 Dave Brolley <brolley@redhat.com>
1538
1539 * cgen.h (symcat.h): #include it.
1540 (cgen-bitset.h): #include it.
1541 (CGEN_ATTR_VALUE_TYPE): Now a union.
1542 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1543 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1544 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1545 * cgen-bitset.h: New file.
1546
3c9b82ba
NC		 15472005-09-30 Catherine Moore <clm@cm00re.com>
1548
1549 * bfin.h: New file.
1550
6a2375c6
JB		 15512005-10-24 Jan Beulich <jbeulich@novell.com>
1552
1553 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1554 indirect operands.
1555
c06a12f8
DA		 15562005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1557
1558 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1559 Add FLAG_STRICT to pa10 ftest opcode.
1560
4d443107
DA		 15612005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1562
1563 * hppa.h (pa_opcodes): Remove lha entries.
1564
f0a3b40f
DA		 15652005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1566
1567 * hppa.h (FLAG_STRICT): Revise comment.
1568 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1569 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1570 entries for "fdc".
1571
e210c36b
NC		 15722005-09-30 Catherine Moore <clm@cm00re.com>
1573
1574 * bfin.h: New file.
1575
1b7e1362
DA		 15762005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1577
1578 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1579
089b39de
CF		 15802005-09-06 Chao-ying Fu <fu@mips.com>
1581
1582 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1583 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1584 define.
1585 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1586 (INSN_ASE_MASK): Update to include INSN_MT.
1587 (INSN_MT): New define for MT ASE.
1588
93c34b9b
CF		 15892005-08-25 Chao-ying Fu <fu@mips.com>
1590
1591 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1592 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1593 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1594 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1595 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1596 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1597 instructions.
1598 (INSN_DSP): New define for DSP ASE.
1599
848cf006
AM		 16002005-08-18 Alan Modra <amodra@bigpond.net.au>
1601
1602 * a29k.h: Delete.
1603
36ae0db3
DJ		 16042005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1605
1606 * ppc.h (PPC_OPCODE_E300): Define.
1607
8c929562
MS		 16082005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1609
1610 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1611
f7b8cccc
DA		 16122005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1613
1614 PR gas/336
1615 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1616 and pitlb.
1617
8b5328ac
JB		 16182005-07-27 Jan Beulich <jbeulich@novell.com>
1619
1620 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1621 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1622 Add movq-s as 64-bit variants of movd-s.
1623
f417d200
DA		 16242005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1625
18b3bdfc
DA		 1626 * hppa.h: Fix punctuation in comment.
1627
f417d200
DA		 1628 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1629 implicit space-register addressing. Set space-register bits on opcodes
1630 using implicit space-register addressing. Add various missing pa20
1631 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1632 space-register addressing. Use "fE" instead of "fe" in various
1633 fstw opcodes.
1634
9a145ce6
JB		 16352005-07-18 Jan Beulich <jbeulich@novell.com>
1636
1637 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1638
90700ea2
L		 16392007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1640
1641 * i386.h (i386_optab): Support Intel VMX Instructions.
1642
48f130a8
DA		 16432005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1644
1645 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1646
30123838
JB		 16472005-07-05 Jan Beulich <jbeulich@novell.com>
1648
1649 * i386.h (i386_optab): Add new insns.
1650
47b0e7ad
NC		 16512005-07-01 Nick Clifton <nickc@redhat.com>
1652
1653 * sparc.h: Add typedefs to structure declarations.
1654
b300c311
L		 16552005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1656
1657 PR 1013
1658 * i386.h (i386_optab): Update comments for 64bit addressing on
1659 mov. Allow 64bit addressing for mov and movq.
1660
2db495be
DA		 16612005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1662
1663 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1664 respectively, in various floating-point load and store patterns.
1665
caa05036
DA		 16662005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1667
1668 * hppa.h (FLAG_STRICT): Correct comment.
1669 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1670 PA 2.0 mneumonics when equivalent. Entries with cache control
1671 completers now require PA 1.1. Adjust whitespace.
1672
f4411256
AM		 16732005-05-19 Anton Blanchard <anton@samba.org>
1674
1675 * ppc.h (PPC_OPCODE_POWER5): Define.
1676
e172dbf8
NC		 16772005-05-10 Nick Clifton <nickc@redhat.com>
1678
1679 * Update the address and phone number of the FSF organization in
1680 the GPL notices in the following files:
1681 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1682 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1683 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1684 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1685 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1686 tic54x.h, tic80.h, v850.h, vax.h
1687
e44823cf
JB		 16882005-05-09 Jan Beulich <jbeulich@novell.com>
1689
1690 * i386.h (i386_optab): Add ht and hnt.
1691
791fe849
MK		 16922005-04-18 Mark Kettenis <kettenis@gnu.org>
1693
1694 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1695 Add xcrypt-ctr. Provide aliases without hyphens.
1696
faa7ef87
L		 16972005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1698
a63027e5
L		 1699 Moved from ../ChangeLog
1700
faa7ef87
L		 1701 2005-04-12 Paul Brook <paul@codesourcery.com>
1702 * m88k.h: Rename psr macros to avoid conflicts.
1703
1704 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1705 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1706 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1707 and ARM_ARCH_V6ZKT2.
1708
1709 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1710 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1711 Remove redundant instruction types.
1712 (struct argument): X_op - new field.
1713 (struct cst4_entry): Remove.
1714 (no_op_insn): Declare.
1715
1716 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1717 * crx.h (enum argtype): Rename types, remove unused types.
1718
1719 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1720 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1721 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1722 (enum operand_type): Rearrange operands, edit comments.
1723 replace us<N> with ui<N> for unsigned immediate.
1724 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1725 displacements (respectively).
1726 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1727 (instruction type): Add NO_TYPE_INS.
1728 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1729 (operand_entry): New field - 'flags'.
1730 (operand flags): New.
1731
1732 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1733 * crx.h (operand_type): Remove redundant types i3, i4,
1734 i5, i8, i12.
1735 Add new unsigned immediate types us3, us4, us5, us16.
1736
bc4bd9ab
MK		 17372005-04-12 Mark Kettenis <kettenis@gnu.org>
1738
1739 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1740 adjust them accordingly.
1741
373ff435
JB		 17422005-04-01 Jan Beulich <jbeulich@novell.com>
1743
1744 * i386.h (i386_optab): Add rdtscp.
1745
4cc91dba
L		 17462005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1747
1748 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 1749 between memory and segment register. Allow movq for moving between
1750 general-purpose register and segment register.
4cc91dba 1751
9ae09ff9
JB		 17522005-02-09 Jan Beulich <jbeulich@novell.com>
1753
1754 PR gas/707
1755 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1756 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1757 fnstsw.
1758
638e7a64
NS		 17592006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1760
1761 * m68k.h (m68008, m68ec030, m68882): Remove.
1762 (m68k_mask): New.
1763 (cpu_m68k, cpu_cf): New.
1764 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1765 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1766
90219bd0
AO		 17672005-01-25 Alexandre Oliva <aoliva@redhat.com>
1768
1769 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1770 * cgen.h (enum cgen_parse_operand_type): Add
1771 CGEN_PARSE_OPERAND_SYMBOLIC.
1772
239cb185
FF		 17732005-01-21 Fred Fish <fnf@specifixinc.com>
1774
1775 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1776 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1777 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1778
dc9a9f39
FF		 17792005-01-19 Fred Fish <fnf@specifixinc.com>
1780
1781 * mips.h (struct mips_opcode): Add new pinfo2 member.
1782 (INSN_ALIAS): New define for opcode table entries that are
1783 specific instances of another entry, such as 'move' for an 'or'
1784 with a zero operand.
1785 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1786 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1787
98e7aba8
ILT		 17882004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1789
1790 * mips.h (CPU_RM9000): Define.
1791 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1792
37edbb65
JB		 17932004-11-25 Jan Beulich <jbeulich@novell.com>
1794
1795 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1796 to/from test registers are illegal in 64-bit mode. Add missing
1797 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1798 (previously one had to explicitly encode a rex64 prefix). Re-enable
1799 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1800 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1801
18022004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 1803
1804 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1805 available only with SSE2. Change the MMX additions introduced by SSE
1806 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1807 instructions by their now designated identifier (since combining i686
1808 and 3DNow! does not really imply 3DNow!A).
1809
f5c7edf4
AM		 18102004-11-19 Alan Modra <amodra@bigpond.net.au>
1811
1812 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1813 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1814
7499d566
NC		 18152004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1816 Vineet Sharma <vineets@noida.hcltech.com>
1817
1818 * maxq.h: New file: Disassembly information for the maxq port.
1819
bcb9eebe
L		 18202004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1821
1822 * i386.h (i386_optab): Put back "movzb".
1823
94bb3d38
HPN		 18242004-11-04 Hans-Peter Nilsson <hp@axis.com>
1825
1826 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1827 comments. Remove member cris_ver_sim. Add members
1828 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1829 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1830 (struct cris_support_reg, struct cris_cond15): New types.
1831 (cris_conds15): Declare.
1832 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1833 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1834 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1835 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1836 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1837 SIZE_FIELD_UNSIGNED.
1838
37edbb65 18392004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 1840
1841 * i386.h (sldx_Suf): Remove.
1842 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1843 (q_FP): Define, implying no REX64.
1844 (x_FP, sl_FP): Imply FloatMF.
1845 (i386_optab): Split reg and mem forms of moving from segment registers
1846 so that the memory forms can ignore the 16-/32-bit operand size
1847 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1848 all non-floating-point instructions. Unite 32- and 64-bit forms of
1849 movsx, movzx, and movd. Adjust floating point operations for the above
1850 changes to the *FP macros. Add DefaultSize to floating point control
1851 insns operating on larger memory ranges. Remove left over comments
1852 hinting at certain insns being Intel-syntax ones where the ones
1853 actually meant are already gone.
1854
48c9f030
NC		 18552004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1856
1857 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1858 instruction type.
1859
0dd132b6
NC		 18602004-09-30 Paul Brook <paul@codesourcery.com>
1861
1862 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1863 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1864
23794b24
MM		 18652004-09-11 Theodore A. Roth <troth@openavr.org>
1866
1867 * avr.h: Add support for
1868 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1869
2a309db0
AM		 18702004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1871
1872 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1873
b18c562e
NC		 18742004-08-24 Dmitry Diky <diwil@spec.ru>
1875
1876 * msp430.h (msp430_opc): Add new instructions.
1877 (msp430_rcodes): Declare new instructions.
1878 (msp430_hcodes): Likewise..
1879
45d313cd
NC		 18802004-08-13 Nick Clifton <nickc@redhat.com>
1881
1882 PR/301
1883 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1884 processors.
1885
30d1c836
ML		 18862004-08-30 Michal Ludvig <mludvig@suse.cz>
1887
1888 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1889
9a45f1c2
L		 18902004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1891
1892 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1893
543613e9
NC		 18942004-07-21 Jan Beulich <jbeulich@novell.com>
1895
1896 * i386.h: Adjust instruction descriptions to better match the
1897 specification.
1898
b781e558
RE		 18992004-07-16 Richard Earnshaw <rearnsha@arm.com>
1900
1901 * arm.h: Remove all old content. Replace with architecture defines
1902 from gas/config/tc-arm.c.
1903
8577e690
AS		 19042004-07-09 Andreas Schwab <schwab@suse.de>
1905
1906 * m68k.h: Fix comment.
1907
1fe1f39c
NC		 19082004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1909
1910 * crx.h: New file.
1911
1d9f512f
AM		 19122004-06-24 Alan Modra <amodra@bigpond.net.au>
1913
1914 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1915
be8c092b
NC		 19162004-05-24 Peter Barada <peter@the-baradas.com>
1917
1918 * m68k.h: Add 'size' to m68k_opcode.
1919
6b6e92f4
NC		 19202004-05-05 Peter Barada <peter@the-baradas.com>
1921
1922 * m68k.h: Switch from ColdFire chip name to core variant.
1923
19242004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 1925
1926 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1927 descriptions for new EMAC cases.
1928 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1929 handle Motorola MAC syntax.
1930 Allow disassembly of ColdFire V4e object files.
1931
fdd12ef3
AM		 19322004-03-16 Alan Modra <amodra@bigpond.net.au>
1933
1934 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1935
3922a64c
L		 19362004-03-12 Jakub Jelinek <jakub@redhat.com>
1937
1938 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1939
1f45d988
ML		 19402004-03-12 Michal Ludvig <mludvig@suse.cz>
1941
1942 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1943
0f10071e
ML		 19442004-03-12 Michal Ludvig <mludvig@suse.cz>
1945
1946 * i386.h (i386_optab): Added xstore/xcrypt insns.
1947
3255318a
NC		 19482004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1949
1950 * h8300.h (32bit ldc/stc): Add relaxing support.
1951
ca9a79a1 19522004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 1953
ca9a79a1
NC		 1954 * h8300.h (BITOP): Pass MEMRELAX flag.
1955
875a0b14
NC		 19562004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1957
1958 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1959 except for the H8S.
252b5132 1960
c9e214e5 1961For older changes see ChangeLog-9103
252b5132 1962\f
4b95cf5c 1963Copyright (C) 2004-2014 Free Software Foundation, Inc.
752937aa
NC		 1964
1965Copying and distribution of this file, with or without modification,
1966are permitted in any medium without royalty provided the copyright
1967notice and this notice are preserved.
1968
252b5132 1969Local Variables:
c9e214e5
AM		 1970mode: change-log
1971left-margin: 8
1972fill-column: 74
252b5132
RH		 1973version-control: never
1974End:
GDB Binutils - Deliverables
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