[deliverable/binutils-gdb.git] / include / opcode / ChangeLog

2005-01-21  Fred Fish  <fnf@specifixinc.com>

	* mips.h: Change INSN_ALIAS to INSN2_ALIAS.
	Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
	Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.

2005-01-19  Fred Fish  <fnf@specifixinc.com>

	* mips.h (struct mips_opcode): Add new pinfo2 member.
	(INSN_ALIAS): New define for opcode table entries that are
	specific instances of another entry, such as 'move' for an 'or'
	with a zero operand.
	(INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
	(INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.

2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>

	* mips.h (CPU_RM9000): Define.
	(OPCODE_IS_MEMBER): Handle CPU_RM9000.

2004-11-25 Jan Beulich  <jbeulich@novell.com>

	* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
	to/from test registers are illegal in 64-bit mode. Add missing
	NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
	(previously one had to explicitly encode a rex64 prefix). Re-enable
	lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
	support it there. Add cmpxchg16b as per Intel's 64-bit documentation.

2004-11-23 Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
	available only with SSE2. Change the MMX additions introduced by SSE
	and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
	instructions by their now designated identifier (since combining i686
	and 3DNow! does not really imply 3DNow!A).

2004-11-19  Alan Modra  <amodra@bigpond.net.au>

	* msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
	struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.

2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
	    Vineet Sharma      <vineets@noida.hcltech.com>

	* maxq.h: New file: Disassembly information for the maxq port.

2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Put back "movzb".

2004-11-04  Hans-Peter Nilsson  <hp@axis.com>

	* cris.h (enum cris_insn_version_usage): Tweak formatting and
	comments.  Remove member cris_ver_sim.  Add members
	cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
	cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
	(struct cris_support_reg, struct cris_cond15): New types.
	(cris_conds15): Declare.
	(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
	(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
	(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
	(NOP_Z_BITS): Define in terms of NOP_OPCODE.
	(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
	SIZE_FIELD_UNSIGNED.

2004-11-04 Jan Beulich  <jbeulich@novell.com>

	* i386.h (sldx_Suf): Remove.
	(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
	(q_FP): Define, implying no REX64.
	(x_FP, sl_FP): Imply FloatMF.
	(i386_optab): Split reg and mem forms of moving from segment registers
	so that the memory forms can ignore the 16-/32-bit operand size
	distinction. Adjust a few others for Intel mode. Remove *FP uses from
	all non-floating-point instructions. Unite 32- and 64-bit forms of
	movsx, movzx, and movd. Adjust floating point operations for the above
	changes to the *FP macros. Add DefaultSize to floating point control
	insns operating on larger memory ranges. Remove left over comments
	hinting at certain insns being Intel-syntax ones where the ones
	actually meant are already gone.

2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>

	* crx.h: Add COPS_REG_INS - Coprocessor Special register
	instruction type.

2004-09-30  Paul Brook  <paul@codesourcery.com>

	* arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
	(ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.

2004-09-11  Theodore A. Roth  <troth@openavr.org>

	* avr.h: Add support for
	atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.

2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>

	* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.

2004-08-24  Dmitry Diky  <diwil@spec.ru>

	* msp430.h (msp430_opc): Add new instructions.
	(msp430_rcodes): Declare new instructions.
	(msp430_hcodes): Likewise..

2004-08-13  Nick Clifton  <nickc@redhat.com>

	PR/301
	* h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
	processors.

2004-08-30  Michal Ludvig  <mludvig@suse.cz>

	* i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.

2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.

2004-07-21  Jan Beulich  <jbeulich@novell.com>

	* i386.h: Adjust instruction descriptions to better match the
	specification.

2004-07-16  Richard Earnshaw  <rearnsha@arm.com>

	* arm.h: Remove all old content.  Replace with architecture defines
	from gas/config/tc-arm.c.

2004-07-09  Andreas Schwab  <schwab@suse.de>

	* m68k.h: Fix comment.

2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>

	* crx.h: New file.

2004-06-24  Alan Modra  <amodra@bigpond.net.au>

	* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.

2004-05-24  Peter Barada  <peter@the-baradas.com>

	* m68k.h: Add 'size' to m68k_opcode.

2004-05-05  Peter Barada  <peter@the-baradas.com>

	* m68k.h: Switch from ColdFire chip name to core variant.

2004-04-22  Peter Barada  <peter@the-baradas.com>

	* m68k.h: Add mcfmac/mcfemac definitions.  Update operand
	descriptions for new EMAC cases.
	Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
	handle Motorola MAC syntax.
	Allow disassembly of ColdFire V4e object files.

2004-03-16  Alan Modra  <amodra@bigpond.net.au>

	* ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.

2004-03-12  Jakub Jelinek  <jakub@redhat.com>

	* i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.

2004-03-12  Michal Ludvig  <mludvig@suse.cz>

	* i386.h (i386_optab): Added xstore as an alias for xstorerng.

2004-03-12  Michal Ludvig  <mludvig@suse.cz>

	* i386.h (i386_optab): Added xstore/xcrypt insns.

2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>

	* h8300.h (32bit ldc/stc): Add relaxing support.

2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>

	* h8300.h (BITOP): Pass MEMRELAX flag.

2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>

	* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
	except for the H8S.

For older changes see ChangeLog-9103
\f
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
239cb185 FF	1	2005-01-21 Fred Fish <fnf@specifixinc.com>
	2
	3	* mips.h: Change INSN_ALIAS to INSN2_ALIAS.
	4	Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
	5	Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
	6
dc9a9f39 FF	7	2005-01-19 Fred Fish <fnf@specifixinc.com>
	8
	9	* mips.h (struct mips_opcode): Add new pinfo2 member.
	10	(INSN_ALIAS): New define for opcode table entries that are
	11	specific instances of another entry, such as 'move' for an 'or'
	12	with a zero operand.
	13	(INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
	14	(INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
	15
98e7aba8 ILT	16	2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
	17
	18	* mips.h (CPU_RM9000): Define.
	19	(OPCODE_IS_MEMBER): Handle CPU_RM9000.
	20
37edbb65 JB	21	2004-11-25 Jan Beulich <jbeulich@novell.com>
	22
	23	* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
	24	to/from test registers are illegal in 64-bit mode. Add missing
	25	NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
	26	(previously one had to explicitly encode a rex64 prefix). Re-enable
	27	lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
	28	support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
	29
	30	2004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e JB	31
	32	* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
	33	available only with SSE2. Change the MMX additions introduced by SSE
	34	and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
	35	instructions by their now designated identifier (since combining i686
	36	and 3DNow! does not really imply 3DNow!A).
	37
f5c7edf4 AM	38	2004-11-19 Alan Modra <amodra@bigpond.net.au>
	39
	40	* msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
	41	struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
	42
7499d566 NC	43	2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
	44	Vineet Sharma <vineets@noida.hcltech.com>
	45
	46	* maxq.h: New file: Disassembly information for the maxq port.
	47
bcb9eebe L	48	2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
	49
	50	* i386.h (i386_optab): Put back "movzb".
	51
94bb3d38 HPN	52	2004-11-04 Hans-Peter Nilsson <hp@axis.com>
	53
	54	* cris.h (enum cris_insn_version_usage): Tweak formatting and
	55	comments. Remove member cris_ver_sim. Add members
	56	cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
	57	cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
	58	(struct cris_support_reg, struct cris_cond15): New types.
	59	(cris_conds15): Declare.
	60	(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
	61	(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
	62	(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
	63	(NOP_Z_BITS): Define in terms of NOP_OPCODE.
	64	(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
	65	SIZE_FIELD_UNSIGNED.
	66
37edbb65	67	2004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a JB	68
	69	* i386.h (sldx_Suf): Remove.
	70	(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
	71	(q_FP): Define, implying no REX64.
	72	(x_FP, sl_FP): Imply FloatMF.
	73	(i386_optab): Split reg and mem forms of moving from segment registers
	74	so that the memory forms can ignore the 16-/32-bit operand size
	75	distinction. Adjust a few others for Intel mode. Remove *FP uses from
	76	all non-floating-point instructions. Unite 32- and 64-bit forms of
	77	movsx, movzx, and movd. Adjust floating point operations for the above
	78	changes to the *FP macros. Add DefaultSize to floating point control
	79	insns operating on larger memory ranges. Remove left over comments
	80	hinting at certain insns being Intel-syntax ones where the ones
	81	actually meant are already gone.
	82
48c9f030 NC	83	2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
	84
	85	* crx.h: Add COPS_REG_INS - Coprocessor Special register
	86	instruction type.
	87
0dd132b6 NC	88	2004-09-30 Paul Brook <paul@codesourcery.com>
	89
	90	* arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
	91	(ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
	92
23794b24 MM	93	2004-09-11 Theodore A. Roth <troth@openavr.org>
	94
	95	* avr.h: Add support for
	96	atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
	97
2a309db0 AM	98	2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
	99
	100	* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
	101
b18c562e NC	102	2004-08-24 Dmitry Diky <diwil@spec.ru>
	103
	104	* msp430.h (msp430_opc): Add new instructions.
	105	(msp430_rcodes): Declare new instructions.
	106	(msp430_hcodes): Likewise..
	107
45d313cd NC	108	2004-08-13 Nick Clifton <nickc@redhat.com>
	109
	110	PR/301
	111	* h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
	112	processors.
	113
30d1c836 ML	114	2004-08-30 Michal Ludvig <mludvig@suse.cz>
	115
	116	* i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
	117
9a45f1c2 L	118	2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
	119
	120	* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
	121
543613e9 NC	122	2004-07-21 Jan Beulich <jbeulich@novell.com>
	123
	124	* i386.h: Adjust instruction descriptions to better match the
	125	specification.
	126
b781e558 RE	127	2004-07-16 Richard Earnshaw <rearnsha@arm.com>
	128
	129	* arm.h: Remove all old content. Replace with architecture defines
	130	from gas/config/tc-arm.c.
	131
8577e690 AS	132	2004-07-09 Andreas Schwab <schwab@suse.de>
	133
	134	* m68k.h: Fix comment.
	135
1fe1f39c NC	136	2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
	137
	138	* crx.h: New file.
	139
1d9f512f AM	140	2004-06-24 Alan Modra <amodra@bigpond.net.au>
	141
	142	* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
	143
be8c092b NC	144	2004-05-24 Peter Barada <peter@the-baradas.com>
	145
	146	* m68k.h: Add 'size' to m68k_opcode.
	147
6b6e92f4 NC	148	2004-05-05 Peter Barada <peter@the-baradas.com>
	149
	150	* m68k.h: Switch from ColdFire chip name to core variant.
	151
	152	2004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b NC	153
	154	* m68k.h: Add mcfmac/mcfemac definitions. Update operand
	155	descriptions for new EMAC cases.
	156	Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
	157	handle Motorola MAC syntax.
	158	Allow disassembly of ColdFire V4e object files.
	159
fdd12ef3 AM	160	2004-03-16 Alan Modra <amodra@bigpond.net.au>
	161
	162	* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
	163
3922a64c L	164	2004-03-12 Jakub Jelinek <jakub@redhat.com>
	165
	166	* i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
	167
1f45d988 ML	168	2004-03-12 Michal Ludvig <mludvig@suse.cz>
	169
	170	* i386.h (i386_optab): Added xstore as an alias for xstorerng.
	171
0f10071e ML	172	2004-03-12 Michal Ludvig <mludvig@suse.cz>
	173
	174	* i386.h (i386_optab): Added xstore/xcrypt insns.
	175
3255318a NC	176	2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
	177
	178	* h8300.h (32bit ldc/stc): Add relaxing support.
	179
ca9a79a1	180	2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3	181
ca9a79a1 NC	182	* h8300.h (BITOP): Pass MEMRELAX flag.
ca9a79a1 NC	183
875a0b14 NC	184	2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
	185
	186	* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
	187	except for the H8S.
252b5132	188
c9e214e5	189	For older changes see ChangeLog-9103
252b5132 RH	190	\f
252b5132 RH	191	Local Variables:
c9e214e5 AM	192	mode: change-log
	193	left-margin: 8
	194	fill-column: 74
252b5132 RH	195	version-control: never
252b5132 RH	196	End: