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Add mach parameter to nios2_find_opcode_hash.
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
b4714c7c
SL		 12014-11-06 Sandra Loosemore <sandra@codesourcery.com>
2
3 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
4 declaration. Fix obsolete comment.
5
96ba4233
SL		 62014-10-23 Sandra Loosemore <sandra@codesourcery.com>
7
8 * nios2.h (enum iw_format_type): New.
9 (struct nios2_opcode): Update comments. Add size and format fields.
10 (NIOS2_INSN_OPTARG): New.
11 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
12 (struct nios2_reg): Add regtype field.
13 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
14 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
15 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
16 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
17 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
18 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
19 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
20 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
21 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
22 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
23 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
24 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
25 (OP_MASK_OP, OP_SH_OP): Delete.
26 (OP_MASK_IOP, OP_SH_IOP): Delete.
27 (OP_MASK_IRD, OP_SH_IRD): Delete.
28 (OP_MASK_IRT, OP_SH_IRT): Delete.
29 (OP_MASK_IRS, OP_SH_IRS): Delete.
30 (OP_MASK_ROP, OP_SH_ROP): Delete.
31 (OP_MASK_RRD, OP_SH_RRD): Delete.
32 (OP_MASK_RRT, OP_SH_RRT): Delete.
33 (OP_MASK_RRS, OP_SH_RRS): Delete.
34 (OP_MASK_JOP, OP_SH_JOP): Delete.
35 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
36 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
37 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
38 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
39 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
40 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
41 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
42 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
43 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
44 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
45 (OP_MASK_<insn>, OP_MASK): Delete.
46 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
47 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
48 Include nios2r1.h to define new instruction opcode constants
49 and accessors.
50 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
51 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
52 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
53 (NUMOPCODES, NUMREGISTERS): Delete.
54 * nios2r1.h: New file.
55
0b6be415
JM		 562014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
57
58 * sparc.h (HWCAP2_VIS3B): Documentation improved.
59
3d68f91c
JM		 602014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
61
62 * sparc.h (sparc_opcode): new field `hwcaps2'.
63 (HWCAP2_FJATHPLUS): New define.
64 (HWCAP2_VIS3B): Likewise.
65 (HWCAP2_ADP): Likewise.
66 (HWCAP2_SPARC5): Likewise.
67 (HWCAP2_MWAIT): Likewise.
68 (HWCAP2_XMPMUL): Likewise.
69 (HWCAP2_XMONT): Likewise.
70 (HWCAP2_NSEC): Likewise.
71 (HWCAP2_FJATHHPC): Likewise.
72 (HWCAP2_FJDES): Likewise.
73 (HWCAP2_FJAES): Likewise.
74 Document the new operand kind `{', corresponding to the mcdper
75 ancillary state register.
76 Document the new operand kind }, which represents frsd floating
77 point registers (double precision) which must be the same than
78 frs1 in its containing instruction.
79
40c7a7cb
KLC		 802014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
81
82 * nds32.h: Add new opcode declaration.
83
7361da2c
AB		 842014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
85 Matthew Fortune <matthew.fortune@imgtec.com>
86
87 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
88 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
89 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
90 +I, +O, +R, +:, +\, +", +;
91 (mips_check_prev_operand): New struct.
92 (INSN2_FORBIDDEN_SLOT): New define.
93 (INSN_ISA32R6): New define.
94 (INSN_ISA64R6): New define.
95 (INSN_UPTO32R6): New define.
96 (INSN_UPTO64R6): New define.
97 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
98 (ISA_MIPS32R6): New define.
99 (ISA_MIPS64R6): New define.
100 (CPU_MIPS32R6): New define.
101 (CPU_MIPS64R6): New define.
102 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
103
ee804238
JW		 1042014-09-03 Jiong Wang <jiong.wang@arm.com>
105
106 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
107 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
108 (aarch64_insn_class): Add lse_atomic.
109 (F_LSE_SZ): New field added.
110 (opcode_has_special_coder): Recognize F_LSE_SZ.
111
5575639b
MR		 1122014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
113
114 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
115 over to `+J'.
116
43885403
MF		 1172014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
118
119 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
120 (INSN_LOAD_COPROC): New define.
121 (INSN_COPROC_MOVE_DELAY): Rename to...
122 (INSN_COPROC_MOVE): New define.
123
f36e8886
BS		 1242014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
125 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
126 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
127 Soundararajan <Sounderarajan.D@atmel.com>
128
129 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
130 (AVR_ISA_2xxxa): Define ISA without LPM.
131 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
132 Add doc for contraint used in 16 bit lds/sts.
133 Adjust ISA group for icall, ijmp, pop and push.
134 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
135
00b32ff2
NC		 1362014-05-19 Nick Clifton <nickc@redhat.com>
137
138 * msp430.h (struct msp430_operand_s): Add vshift field.
139
ae52f483
AB		 1402014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
141
142 * mips.h (INSN_ISA_MASK): Updated.
143 (INSN_ISA32R3): New define.
144 (INSN_ISA32R5): New define.
145 (INSN_ISA64R3): New define.
146 (INSN_ISA64R5): New define.
147 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
148 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
149 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
150 mips64r5.
151 (INSN_UPTO32R3): New define.
152 (INSN_UPTO32R5): New define.
153 (INSN_UPTO64R3): New define.
154 (INSN_UPTO64R5): New define.
155 (ISA_MIPS32R3): New define.
156 (ISA_MIPS32R5): New define.
157 (ISA_MIPS64R3): New define.
158 (ISA_MIPS64R5): New define.
159 (CPU_MIPS32R3): New define.
160 (CPU_MIPS32R5): New define.
161 (CPU_MIPS64R3): New define.
162 (CPU_MIPS64R5): New define.
163
3efe9ec5
RS		 1642014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
165
166 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
167
73589c9d
CS		 1682014-04-22 Christian Svensson <blue@cmd.nu>
169
170 * or32.h: Delete.
171
4b95cf5c
AM		 1722014-03-05 Alan Modra <amodra@gmail.com>
173
174 Update copyright years.
175
e269fea7
AB		 1762013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
177
178 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
179 microMIPS.
180
35c08157
KLC		 1812013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
182 Wei-Cheng Wang <cole945@gmail.com>
183
184 * nds32.h: New file for Andes NDS32.
185
594d8fa8
MF		 1862013-12-07 Mike Frysinger <vapier@gentoo.org>
187
188 * bfin.h: Remove +x file mode.
189
87b8eed7
YZ		 1902013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
191
192 * aarch64.h (aarch64_pstatefields): Change element type to
193 aarch64_sys_reg.
194
c9fb6e58
YZ		 1952013-11-18 Renlin Li <Renlin.Li@arm.com>
196
197 * arm.h (ARM_AEXT_V7VE): New define.
198 (ARM_ARCH_V7VE): New define.
199 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
200
a203d9b7
YZ		 2012013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
202
203 Revert
204
205 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
206
207 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
208 (aarch64_sys_reg_writeonly_p): Ditto.
209
75468c93
YZ		 2102013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
211
212 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
213 (aarch64_sys_reg_writeonly_p): Ditto.
214
49eec193
YZ		 2152013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
216
217 * aarch64.h (aarch64_sys_reg): New typedef.
218 (aarch64_sys_regs): Change to define with the new type.
219 (aarch64_sys_reg_deprecated_p): Declare.
220
68a64283
YZ		 2212013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
222
223 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
224 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
225
387a82f1
CF		 2262013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
227
228 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
229 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
230 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
231 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
232 For MIPS, update extension character sequences after +.
233 (ASE_MSA): New define.
234 (ASE_MSA64): New define.
235 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
236 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
237 For microMIPS, update extension character sequences after +.
238
9aff4b7a
NC		 2392013-08-23 Yuri Chornoivan <yurchor@ukr.net>
240
241 PR binutils/15834
242 * i960.h: Fix typos.
243
e423441d
RS		 2442013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
245
246 * mips.h: Remove references to "+I" and imm2_expr.
247
5e0dc5ba
RS		 2482013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
249
250 * mips.h (M_DEXT, M_DINS): Delete.
251
0f35dbc4
RS		 2522013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
253
254 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
255 (mips_optional_operand_p): New function.
256
14daeee3
RS		 2572013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
258 Richard Sandiford <rdsandiford@googlemail.com>
259
260 * mips.h: Document new VU0 operand characters.
261 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
262 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
263 (OP_REG_R5900_ACC): New mips_reg_operand_types.
264 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
265 (mips_vu0_channel_mask): Declare.
266
3ccad066
RS		 2672013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
268
269 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
270 (mips_int_operand_min, mips_int_operand_max): New functions.
271 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
272
fc76e730
RS		 2732013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
274
275 * mips.h (mips_decode_reg_operand): New function.
276 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
277 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
278 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
279 New macros.
280 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
281 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
282 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
283 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
284 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
285 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
286 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
287 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
288 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
289 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
290 macros to cover the gaps.
291 (INSN2_MOD_SP): Replace with...
292 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
293 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
294 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
295 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
296 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
297 Delete.
298
26545944
RS		 2992013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
300
301 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
302 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
303 (MIPS16_INSN_COND_BRANCH): Delete.
304
7e8b059b
L		 3052013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
306 Kirill Yukhin <kirill.yukhin@intel.com>
307 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
308
309 * i386.h (BND_PREFIX_OPCODE): New.
310
c3c07478
RS		 3112013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
312
313 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
314 OP_SAVE_RESTORE_LIST.
315 (decode_mips16_operand): Declare.
316
ab902481
RS		 3172013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
318
319 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
320 (mips_operand, mips_int_operand, mips_mapped_int_operand)
321 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
322 (mips_pcrel_operand): New structures.
323 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
324 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
325 (decode_mips_operand, decode_micromips_operand): Declare.
326
cc537e56
RS		 3272013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
328
329 * mips.h: Document MIPS16 "I" opcode.
330
f2ae14a1
RS		 3312013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
332
333 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
334 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
335 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
336 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
337 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
338 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
339 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
340 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
341 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
342 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
343 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
344 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
345 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
346 Rename to...
347 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
348 (M_USD_AB): ...these.
349
5c324c16
RS		 3502013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
351
352 * mips.h: Remove documentation of "[" and "]". Update documentation
353 of "k" and the MDMX formats.
354
23e69e47
RS		 3552013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
356
357 * mips.h: Update documentation of "+s" and "+S".
358
27c5c572
RS		 3592013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
360
361 * mips.h: Document "+i".
362
e76ff5ab
RS		 3632013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
364
365 * mips.h: Remove "mi" documentation. Update "mh" documentation.
366 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
367 Delete.
368 (INSN2_WRITE_GPR_MHI): Rename to...
369 (INSN2_WRITE_GPR_MH): ...this.
370
fa7616a4
RS		 3712013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
372
373 * mips.h: Remove documentation of "+D" and "+T".
374
18870af7
RS		 3752013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
376
377 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
378 Use "source" rather than "destination" for microMIPS "G".
379
833794fc
MR		 3802013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
381
382 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
383 values.
384
c3678916
RS		 3852013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
386
387 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
388
7f3c4072
CM		 3892013-06-17 Catherine Moore <clm@codesourcery.com>
390 Maciej W. Rozycki <macro@codesourcery.com>
391 Chao-Ying Fu <fu@mips.com>
392
393 * mips.h (OP_SH_EVAOFFSET): Define.
394 (OP_MASK_EVAOFFSET): Define.
395 (INSN_ASE_MASK): Delete.
396 (ASE_EVA): Define.
397 (M_CACHEE_AB, M_CACHEE_OB): New.
398 (M_LBE_OB, M_LBE_AB): New.
399 (M_LBUE_OB, M_LBUE_AB): New.
400 (M_LHE_OB, M_LHE_AB): New.
401 (M_LHUE_OB, M_LHUE_AB): New.
402 (M_LLE_AB, M_LLE_OB): New.
403 (M_LWE_OB, M_LWE_AB): New.
404 (M_LWLE_AB, M_LWLE_OB): New.
405 (M_LWRE_AB, M_LWRE_OB): New.
406 (M_PREFE_AB, M_PREFE_OB): New.
407 (M_SCE_AB, M_SCE_OB): New.
408 (M_SBE_OB, M_SBE_AB): New.
409 (M_SHE_OB, M_SHE_AB): New.
410 (M_SWE_OB, M_SWE_AB): New.
411 (M_SWLE_AB, M_SWLE_OB): New.
412 (M_SWRE_AB, M_SWRE_OB): New.
413 (MICROMIPSOP_SH_EVAOFFSET): Define.
414 (MICROMIPSOP_MASK_EVAOFFSET): Define.
415
0c8fe7cf
SL		 4162013-06-12 Sandra Loosemore <sandra@codesourcery.com>
417
418 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
419
c77c0862
RS		 4202013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
421
422 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
423
b015e599
AP		 4242013-05-09 Andrew Pinski <apinski@cavium.com>
425
426 * mips.h (OP_MASK_CODE10): Correct definition.
427 (OP_SH_CODE10): Likewise.
428 Add a comment that "+J" is used now for OP_*CODE10.
429 (INSN_ASE_MASK): Update.
430 (INSN_VIRT): New macro.
431 (INSN_VIRT64): New macro
432
13761a11
NC		 4332013-05-02 Nick Clifton <nickc@redhat.com>
434
435 * msp430.h: Add patterns for MSP430X instructions.
436
0afd1215
DM		 4372013-04-06 David S. Miller <davem@davemloft.net>
438
439 * sparc.h (F_PREFERRED): Define.
440 (F_PREF_ALIAS): Define.
441
41702d50
NC		 4422013-04-03 Nick Clifton <nickc@redhat.com>
443
444 * v850.h (V850_INVERSE_PCREL): Define.
445
e21e1a51
NC		 4462013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
447
448 PR binutils/15068
449 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
450
51dcdd4d
NC		 4512013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
452
453 PR binutils/15068
454 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
455 Add 16-bit opcodes.
456 * tic6xc-opcode-table.h: Add 16-bit insns.
457 * tic6x.h: Add support for 16-bit insns.
458
81f5558e
NC		 4592013-03-21 Michael Schewe <michael.schewe@gmx.net>
460
461 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
462 and mov.b/w/l Rs,@(d:32,ERd).
463
165546ad
NC		 4642013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
465
466 PR gas/15082
467 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
468 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
469 tic6x_operand_xregpair operand coding type.
470 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
471 opcode field, usu ORXREGD1324 for the src2 operand and remove the
472 TIC6X_FLAG_NO_CROSS.
473
795b8e6b
NC		 4742013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
475
476 PR gas/15095
477 * tic6x.h (enum tic6x_coding_method): Add
478 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
479 separately the msb and lsb of a register pair. This is needed to
480 encode the opcodes in the same way as TI assembler does.
481 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
482 and rsqrdp opcodes to use the new field coding types.
483
dd5181d5
KT		 4842013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
485
486 * arm.h (CRC_EXT_ARMV8): New constant.
487 (ARCH_CRC_ARMV8): New macro.
488
e60bb1dd
YZ		 4892013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
490
491 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
492
36591ba1
SL		 4932013-02-06 Sandra Loosemore <sandra@codesourcery.com>
494 Andrew Jenner <andrew@codesourcery.com>
495
496 Based on patches from Altera Corporation.
497
498 * nios2.h: New file.
499
e30181a5
YZ		 5002013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
501
502 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
503
0c9573f4
NC		 5042013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
505
506 PR gas/15069
507 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
508
981dc7f1
NC		 5092013-01-24 Nick Clifton <nickc@redhat.com>
510
511 * v850.h: Add e3v5 support.
512
f5555712
YZ		 5132013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
514
515 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
516
5817ffd1
PB		 5172013-01-10 Peter Bergner <bergner@vnet.ibm.com>
518
519 * ppc.h (PPC_OPCODE_POWER8): New define.
520 (PPC_OPCODE_HTM): Likewise.
521
a3c62988
NC		 5222013-01-10 Will Newton <will.newton@imgtec.com>
523
524 * metag.h: New file.
525
73335eae
NC		 5262013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
527
528 * cr16.h (make_instruction): Rename to cr16_make_instruction.
529 (match_opcode): Rename to cr16_match_opcode.
530
e407c74b
NC		 5312013-01-04 Juergen Urban <JuergenUrban@gmx.de>
532
533 * mips.h: Add support for r5900 instructions including lq and sq.
534
bab4becb
NC		 5352013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
536
537 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
538 (make_instruction,match_opcode): Added function prototypes.
539 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
540
776fc418
AM		 5412012-11-23 Alan Modra <amodra@gmail.com>
542
543 * ppc.h (ppc_parse_cpu): Update prototype.
544
f05682d4
DA		 5452012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
546
547 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
548 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
549
cfc72779
AK		 5502012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
551
552 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
553
b3e14eda
L		 5542012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
555
556 * ia64.h (ia64_opnd): Add new operand types.
557
2c63854f
DM		 5582012-08-21 David S. Miller <davem@davemloft.net>
559
560 * sparc.h (F3F4): New macro.
561
a06ea964 5622012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 563 Laurent Desnogues <laurent.desnogues@arm.com>
564 Jim MacArthur <jim.macarthur@arm.com>
565 Marcus Shawcroft <marcus.shawcroft@arm.com>
566 Nigel Stephens <nigel.stephens@arm.com>
567 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
568 Richard Earnshaw <rearnsha@arm.com>
569 Sofiane Naci <sofiane.naci@arm.com>
570 Tejas Belagod <tejas.belagod@arm.com>
571 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 572
573 * aarch64.h: New file.
574
35d0a169 5752012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 576 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 577
578 * mips.h (mips_opcode): Add the exclusions field.
579 (OPCODE_IS_MEMBER): Remove macro.
580 (cpu_is_member): New inline function.
581 (opcode_is_member): Likewise.
582
03f66e8a 5832012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 584 Catherine Moore <clm@codesourcery.com>
585 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 586
587 * mips.h: Document microMIPS DSP ASE usage.
588 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
589 microMIPS DSP ASE support.
590 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
591 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
592 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
593 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
594 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
595 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
596 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
597
9d7b4c23
MR		 5982012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
599
600 * mips.h: Fix a typo in description.
601
76e879f8
NC		 6022012-06-07 Georg-Johann Lay <avr@gjlay.de>
603
604 * avr.h: (AVR_ISA_XCH): New define.
605 (AVR_ISA_XMEGA): Use it.
606 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
607
6927f982
NC		 6082012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
609
610 * m68hc11.h: Add XGate definitions.
611 (struct m68hc11_opcode): Add xg_mask field.
612
b9c361e0
JL		 6132012-05-14 Catherine Moore <clm@codesourcery.com>
614 Maciej W. Rozycki <macro@codesourcery.com>
615 Rhonda Wittels <rhonda@codesourcery.com>
616
6927f982 617 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 618 (PPC_OP_SA): New macro.
619 (PPC_OP_SE_VLE): New macro.
620 (PPC_OP): Use a variable shift amount.
621 (powerpc_operand): Update comments.
622 (PPC_OPSHIFT_INV): New macro.
623 (PPC_OPERAND_CR): Replace with...
624 (PPC_OPERAND_CR_BIT): ...this and
625 (PPC_OPERAND_CR_REG): ...this.
626
627
f6c1a2d5
NC		 6282012-05-03 Sean Keys <skeys@ipdatasys.com>
629
630 * xgate.h: Header file for XGATE assembler.
631
ec668d69
DM		 6322012-04-27 David S. Miller <davem@davemloft.net>
633
6cda1326
DM		 634 * sparc.h: Document new arg code' )' for crypto RS3
635 immediates.
636
ec668d69
DM		 637 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
638 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
639 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
640 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
641 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
642 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
643 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
644 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
645 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
646 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
647 HWCAP_CBCOND, HWCAP_CRC32): New defines.
648
aea77599
AM		 6492012-03-10 Edmar Wienskoski <edmar@freescale.com>
650
651 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
652
1f42f8b3
AM		 6532012-02-27 Alan Modra <amodra@gmail.com>
654
655 * crx.h (cst4_map): Update declaration.
656
6f7be959
WL		 6572012-02-25 Walter Lee <walt@tilera.com>
658
659 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
660 TILEGX_OPC_LD_TLS.
661 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
662 TILEPRO_OPC_LW_TLS_SN.
663
42164a71
L		 6642012-02-08 H.J. Lu <hongjiu.lu@intel.com>
665
666 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
667 (XRELEASE_PREFIX_OPCODE): Likewise.
668
432233b3 6692011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 670 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 671
672 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
673 (INSN_OCTEON2): New macro.
674 (CPU_OCTEON2): New macro.
675 (OPCODE_IS_MEMBER): Add Octeon2.
676
dd6a37e7
AP		 6772011-11-29 Andrew Pinski <apinski@cavium.com>
678
679 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
680 (INSN_OCTEONP): New macro.
681 (CPU_OCTEONP): New macro.
682 (OPCODE_IS_MEMBER): Add Octeon+.
683 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
684
99c513f6
DD		 6852011-11-01 DJ Delorie <dj@redhat.com>
686
687 * rl78.h: New file.
688
26f85d7a
MR		 6892011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
690
691 * mips.h: Fix a typo in description.
692
9e8c70f9
DM		 6932011-09-21 David S. Miller <davem@davemloft.net>
694
695 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
696 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
697 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
698 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
699
dec0624d 7002011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 701 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 702
703 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
704 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
705 (INSN_ASE_MASK): Add the MCU bit.
706 (INSN_MCU): New macro.
707 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
708 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
709
2b0c8b40
MR		 7102011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
711
712 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
713 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
714 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
715 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
716 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
717 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
718 (INSN2_READ_GPR_MMN): Likewise.
719 (INSN2_READ_FPR_D): Change the bit used.
720 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
721 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
722 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
723 (INSN2_COND_BRANCH): Likewise.
724 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
725 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
726 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
727 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
728 (INSN2_MOD_GPR_MN): Likewise.
729
ea783ef3
DM		 7302011-08-05 David S. Miller <davem@davemloft.net>
731
732 * sparc.h: Document new format codes '4', '5', and '('.
733 (OPF_LOW4, RS3): New macros.
734
7c176fa8
MR		 7352011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
736
737 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
738 order of flags documented.
739
2309ddf2
MR		 7402011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
741
742 * mips.h: Clarify the description of microMIPS instruction
743 manipulation macros.
744 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
745
df58fc94 7462011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 747 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 748
749 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
750 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
751 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
752 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
753 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
754 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
755 (OP_MASK_RS3, OP_SH_RS3): Likewise.
756 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
757 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
758 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
759 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
760 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
761 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
762 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
763 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
764 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
765 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
766 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
767 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
768 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
769 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
770 (INSN_WRITE_GPR_S): New macro.
771 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
772 (INSN2_READ_FPR_D): Likewise.
773 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
774 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
775 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
776 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
777 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
778 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
779 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
780 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
781 (CPU_MICROMIPS): New macro.
782 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
783 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
784 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
785 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
786 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
787 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
788 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
789 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
790 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
791 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
792 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
793 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
794 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
795 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
796 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
797 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
798 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
799 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
800 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
801 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
802 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
803 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
804 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
805 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
806 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
807 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
808 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
809 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
810 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
811 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
812 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
813 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
814 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
815 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
816 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
817 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
818 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
819 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
820 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
821 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
822 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
823 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
824 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
825 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
826 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
827 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
828 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
829 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
830 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
831 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
832 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
833 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
834 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
835 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
836 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
837 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
838 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
839 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
840 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
841 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
842 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
843 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
844 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
845 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
846 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
847 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
848 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
849 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
850 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
851 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
852 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
853 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
854 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
855 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
856 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
857 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
858 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
859 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
860 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
861 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
862 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
863 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
864 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
865 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
866 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
867 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
868 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
869 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
870 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
871 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
872 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
873 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
874 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
875 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
876 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
877 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
878 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
879 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
880 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
881 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
882 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
883 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
884 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
885 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
886 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
887 (micromips_opcodes): New declaration.
888 (bfd_micromips_num_opcodes): Likewise.
889
bcd530a7
RS		 8902011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
891
892 * mips.h (INSN_TRAP): Rename to...
893 (INSN_NO_DELAY_SLOT): ... this.
894 (INSN_SYNC): Remove macro.
895
2dad5a91
EW		 8962011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
897
898 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
899 a duplicate of AVR_ISA_SPM.
900
5d73b1f1
NC		 9012011-07-01 Nick Clifton <nickc@redhat.com>
902
903 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
904
ef26d60e
MF		 9052011-06-18 Robin Getz <robin.getz@analog.com>
906
907 * bfin.h (is_macmod_signed): New func
908
8fb8dca7
MF		 9092011-06-18 Mike Frysinger <vapier@gentoo.org>
910
911 * bfin.h (is_macmod_pmove): Add missing space before func args.
912 (is_macmod_hmove): Likewise.
913
aa137e4d
NC		 9142011-06-13 Walter Lee <walt@tilera.com>
915
916 * tilegx.h: New file.
917 * tilepro.h: New file.
918
3b2f0793
PB		 9192011-05-31 Paul Brook <paul@codesourcery.com>
920
aa137e4d
NC		 921 * arm.h (ARM_ARCH_V7R_IDIV): Define.
922
9232011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
924
925 * s390.h: Replace S390_OPERAND_REG_EVEN with
926 S390_OPERAND_REG_PAIR.
927
9282011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
929
930 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 931
ac7f631b
NC		 9322011-04-18 Julian Brown <julian@codesourcery.com>
933
934 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
935
84701018
NC		 9362011-04-11 Dan McDonald <dan@wellkeeper.com>
937
938 PR gas/12296
939 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
940
8cc66334
EW		 9412011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
942
943 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
944 New instruction set flags.
945 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
946
3eebd5eb
MR		 9472011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
948
949 * mips.h (M_PREF_AB): New enum value.
950
26bb3ddd
MF		 9512011-02-12 Mike Frysinger <vapier@gentoo.org>
952
89c0d58c
MR		 953 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
954 M_IU): Define.
955 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 956
dd76fcb8
MF		 9572011-02-11 Mike Frysinger <vapier@gentoo.org>
958
959 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
960
98d23bef
BS		 9612011-02-04 Bernd Schmidt <bernds@codesourcery.com>
962
963 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
964 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
965
3c853d93
DA		 9662010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
967
968 PR gas/11395
969 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
970 "bb" entries.
971
79676006
DA		 9722010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
973
974 PR gas/11395
975 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
976
1bec78e9
RS		 9772010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
978
979 * mips.h: Update commentary after last commit.
980
98675402
RS		 9812010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
982
983 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
984 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
985 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
986
aa137e4d
NC		 9872010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
988
989 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
990
435b94a4
RS		 9912010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
992
993 * mips.h: Fix previous commit.
994
d051516a
NC		 9952010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
996
997 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
998 (INSN_LOONGSON_3A): Clear bit 31.
999
251665fc
MGD		 10002010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1001
1002 PR gas/12198
1003 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1004 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1005 (ARM_ARCH_V6M_ONLY): New define.
1006
fd503541
NC		 10072010-11-11 Mingming Sun <mingm.sun@gmail.com>
1008
1009 * mips.h (INSN_LOONGSON_3A): Defined.
1010 (CPU_LOONGSON_3A): Defined.
1011 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1012
4469d2be
AM		 10132010-10-09 Matt Rice <ratmice@gmail.com>
1014
1015 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1016 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1017
90ec0d68
MGD		 10182010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1019
1020 * arm.h (ARM_EXT_VIRT): New define.
1021 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1022 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1023 Extensions.
1024
eea54501 10252010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1026
eea54501
MGD		 1027 * arm.h (ARM_AEXT_ADIV): New define.
1028 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1029
b2a5fbdc
MGD		 10302010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1031
1032 * arm.h (ARM_EXT_OS): New define.
1033 (ARM_AEXT_V6SM): Likewise.
1034 (ARM_ARCH_V6SM): Likewise.
1035
60e5ef9f
MGD		 10362010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1037
1038 * arm.h (ARM_EXT_MP): Add.
1039 (ARM_ARCH_V7A_MP): Likewise.
1040
73a63ccf
MF		 10412010-09-22 Mike Frysinger <vapier@gentoo.org>
1042
1043 * bfin.h: Declare pseudoChr structs/defines.
1044
ee99860a
MF		 10452010-09-21 Mike Frysinger <vapier@gentoo.org>
1046
1047 * bfin.h: Strip trailing whitespace.
1048
f9c7014e
DD		 10492010-07-29 DJ Delorie <dj@redhat.com>
1050
1051 * rx.h (RX_Operand_Type): Add TwoReg.
1052 (RX_Opcode_ID): Remove ediv and ediv2.
1053
93378652
DD		 10542010-07-27 DJ Delorie <dj@redhat.com>
1055
1056 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1057
1cd986c5
NC		 10582010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1059 Ina Pandit <ina.pandit@kpitcummins.com>
1060
1061 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1062 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1063 PROCESSOR_V850E2_ALL.
1064 Remove PROCESSOR_V850EA support.
1065 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1066 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1067 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1068 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1069 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1070 V850_OPERAND_PERCENT.
1071 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1072 V850_NOT_R0.
1073 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1074 and V850E_PUSH_POP
1075
9a2c7088
MR		 10762010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1077
1078 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1079 (MIPS16_INSN_BRANCH): Rename to...
1080 (MIPS16_INSN_COND_BRANCH): ... this.
1081
bdc70b4a
AM		 10822010-07-03 Alan Modra <amodra@gmail.com>
1083
1084 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1085 Renumber other PPC_OPCODE defines.
1086
f2bae120
AM		 10872010-07-03 Alan Modra <amodra@gmail.com>
1088
1089 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1090
360cfc9c
AM		 10912010-06-29 Alan Modra <amodra@gmail.com>
1092
1093 * maxq.h: Delete file.
1094
e01d869a
AM		 10952010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1096
1097 * ppc.h (PPC_OPCODE_E500): Define.
1098
f79e2745
CM		 10992010-05-26 Catherine Moore <clm@codesourcery.com>
1100
1101 * opcode/mips.h (INSN_MIPS16): Remove.
1102
2462afa1
JM		 11032010-04-21 Joseph Myers <joseph@codesourcery.com>
1104
1105 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1106
e4e42b45
NC		 11072010-04-15 Nick Clifton <nickc@redhat.com>
1108
1109 * alpha.h: Update copyright notice to use GPLv3.
1110 * arc.h: Likewise.
1111 * arm.h: Likewise.
1112 * avr.h: Likewise.
1113 * bfin.h: Likewise.
1114 * cgen.h: Likewise.
1115 * convex.h: Likewise.
1116 * cr16.h: Likewise.
1117 * cris.h: Likewise.
1118 * crx.h: Likewise.
1119 * d10v.h: Likewise.
1120 * d30v.h: Likewise.
1121 * dlx.h: Likewise.
1122 * h8300.h: Likewise.
1123 * hppa.h: Likewise.
1124 * i370.h: Likewise.
1125 * i386.h: Likewise.
1126 * i860.h: Likewise.
1127 * i960.h: Likewise.
1128 * ia64.h: Likewise.
1129 * m68hc11.h: Likewise.
1130 * m68k.h: Likewise.
1131 * m88k.h: Likewise.
1132 * maxq.h: Likewise.
1133 * mips.h: Likewise.
1134 * mmix.h: Likewise.
1135 * mn10200.h: Likewise.
1136 * mn10300.h: Likewise.
1137 * msp430.h: Likewise.
1138 * np1.h: Likewise.
1139 * ns32k.h: Likewise.
1140 * or32.h: Likewise.
1141 * pdp11.h: Likewise.
1142 * pj.h: Likewise.
1143 * pn.h: Likewise.
1144 * ppc.h: Likewise.
1145 * pyr.h: Likewise.
1146 * rx.h: Likewise.
1147 * s390.h: Likewise.
1148 * score-datadep.h: Likewise.
1149 * score-inst.h: Likewise.
1150 * sparc.h: Likewise.
1151 * spu-insns.h: Likewise.
1152 * spu.h: Likewise.
1153 * tic30.h: Likewise.
1154 * tic4x.h: Likewise.
1155 * tic54x.h: Likewise.
1156 * tic80.h: Likewise.
1157 * v850.h: Likewise.
1158 * vax.h: Likewise.
1159
40b36596
JM		 11602010-03-25 Joseph Myers <joseph@codesourcery.com>
1161
1162 * tic6x-control-registers.h, tic6x-insn-formats.h,
1163 tic6x-opcode-table.h, tic6x.h: New.
1164
c67a084a
NC		 11652010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1166
1167 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1168
466ef64f
AM		 11692010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1170
1171 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1172
1319d143
L		 11732010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1174
1175 * ia64.h (ia64_find_opcode): Remove argument name.
1176 (ia64_find_next_opcode): Likewise.
1177 (ia64_dis_opcode): Likewise.
1178 (ia64_free_opcode): Likewise.
1179 (ia64_find_dependency): Likewise.
1180
1fbb9298
DE		 11812009-11-22 Doug Evans <dje@sebabeach.org>
1182
1183 * cgen.h: Include bfd_stdint.h.
1184 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1185
ada65aa3
PB		 11862009-11-18 Paul Brook <paul@codesourcery.com>
1187
1188 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1189
9e3c6df6
PB		 11902009-11-17 Paul Brook <paul@codesourcery.com>
1191 Daniel Jacobowitz <dan@codesourcery.com>
1192
1193 * arm.h (ARM_EXT_V6_DSP): Define.
1194 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1195 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1196
0d734b5d
DD		 11972009-11-04 DJ Delorie <dj@redhat.com>
1198
1199 * rx.h (rx_decode_opcode) (mvtipl): Add.
1200 (mvtcp, mvfcp, opecp): Remove.
1201
62f3b8c8
PB		 12022009-11-02 Paul Brook <paul@codesourcery.com>
1203
1204 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1205 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1206 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1207 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1208 FPU_ARCH_NEON_VFP_V4): Define.
1209
ac1e9eca
DE		 12102009-10-23 Doug Evans <dje@sebabeach.org>
1211
1212 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1213 * cgen.h: Update. Improve multi-inclusion macro name.
1214
9fe54b1c
PB		 12152009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1216
1217 * ppc.h (PPC_OPCODE_476): Define.
1218
634b50f2
PB		 12192009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1220
1221 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1222
c7927a3c
NC		 12232009-09-29 DJ Delorie <dj@redhat.com>
1224
1225 * rx.h: New file.
1226
b961e85b
AM		 12272009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1228
1229 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1230
e0d602ec
BE		 12312009-09-21 Ben Elliston <bje@au.ibm.com>
1232
1233 * ppc.h (PPC_OPCODE_PPCA2): New.
1234
96d56e9f
NC		 12352009-09-05 Martin Thuresson <martin@mtme.org>
1236
1237 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1238
d3ce72d0
NC		 12392009-08-29 Martin Thuresson <martin@mtme.org>
1240
1241 * tic30.h (template): Rename type template to
1242 insn_template. Updated code to use new name.
1243 * tic54x.h (template): Rename type template to
1244 insn_template.
1245
824b28db
NH		 12462009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1247
1248 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1249
f865a31d
AG		 12502009-06-11 Anthony Green <green@moxielogic.com>
1251
1252 * moxie.h (MOXIE_F3_PCREL): Define.
1253 (moxie_form3_opc_info): Grow.
1254
0e7c7f11
AG		 12552009-06-06 Anthony Green <green@moxielogic.com>
1256
1257 * moxie.h (MOXIE_F1_M): Define.
1258
20135e4c
NC		 12592009-04-15 Anthony Green <green@moxielogic.com>
1260
1261 * moxie.h: Created.
1262
bcb012d3
DD		 12632009-04-06 DJ Delorie <dj@redhat.com>
1264
1265 * h8300.h: Add relaxation attributes to MOVA opcodes.
1266
69fe9ce5
AM		 12672009-03-10 Alan Modra <amodra@bigpond.net.au>
1268
1269 * ppc.h (ppc_parse_cpu): Declare.
1270
c3b7224a
NC		 12712009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1272
1273 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1274 and _IMM11 for mbitclr and mbitset.
1275 * score-datadep.h: Update dependency information.
1276
066be9f7
PB		 12772009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1278
1279 * ppc.h (PPC_OPCODE_POWER7): New.
1280
fedc618e
DE		 12812009-02-06 Doug Evans <dje@google.com>
1282
1283 * i386.h: Add comment regarding sse* insns and prefixes.
1284
52b6b6b9
JM		 12852009-02-03 Sandip Matte <sandip@rmicorp.com>
1286
1287 * mips.h (INSN_XLR): Define.
1288 (INSN_CHIP_MASK): Update.
1289 (CPU_XLR): Define.
1290 (OPCODE_IS_MEMBER): Update.
1291 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1292
35669430
DE		 12932009-01-28 Doug Evans <dje@google.com>
1294
1295 * opcode/i386.h: Add multiple inclusion protection.
1296 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1297 (EDI_REG_NUM): New macros.
1298 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1299 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1300 (REX_PREFIX_P): New macro.
35669430 1301
1cb0a767
PB		 13022009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1303
1304 * ppc.h (struct powerpc_opcode): New field "deprecated".
1305 (PPC_OPCODE_NOPOWER4): Delete.
1306
3aa3176b
TS		 13072008-11-28 Joshua Kinard <kumba@gentoo.org>
1308
1309 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1310 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1311
8e79c3df
CM		 13122008-11-18 Catherine Moore <clm@codesourcery.com>
1313
1314 * arm.h (FPU_NEON_FP16): New.
1315 (FPU_ARCH_NEON_FP16): New.
1316
de9a3e51
CF		 13172008-11-06 Chao-ying Fu <fu@mips.com>
1318
1319 * mips.h: Doucument '1' for 5-bit sync type.
1320
1ca35711
L		 13212008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1322
1323 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1324 IA64_RS_CR.
1325
9b4e5766
PB		 13262008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1327
1328 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1329
081ba1b3
AM		 13302008-07-30 Michael J. Eager <eager@eagercon.com>
1331
1332 * ppc.h (PPC_OPCODE_405): Define.
1333 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1334
fa452fa6
PB		 13352008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1336
1337 * ppc.h (ppc_cpu_t): New typedef.
1338 (struct powerpc_opcode <flags>): Use it.
1339 (struct powerpc_operand <insert, extract>): Likewise.
1340 (struct powerpc_macro <flags>): Likewise.
1341
bb35fb24
NC		 13422008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1343
1344 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1345 Update comment before MIPS16 field descriptors to mention MIPS16.
1346 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1347 BBIT.
1348 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1349 New bit masks and shift counts for cins and exts.
1350
dd3cbb7e
NC		 1351 * mips.h: Document new field descriptors +Q.
1352 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1353
d0799671
AN		 13542008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1355
9aff4b7a 1356 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1357 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1358
19a6653c
AM		 13592008-04-14 Edmar Wienskoski <edmar@freescale.com>
1360
1361 * ppc.h: (PPC_OPCODE_E500MC): New.
1362
c0f3af97
L		 13632008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1364
1365 * i386.h (MAX_OPERANDS): Set to 5.
1366 (MAX_MNEM_SIZE): Changed to 20.
1367
e210c36b
NC		 13682008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1369
1370 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1371
b1cc4aeb
PB		 13722008-03-09 Paul Brook <paul@codesourcery.com>
1373
1374 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1375
7e806470
PB		 13762008-03-04 Paul Brook <paul@codesourcery.com>
1377
1378 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1379 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1380 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1381
7b2185f9 13822008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1383 Nick Clifton <nickc@redhat.com>
1384
1385 PR 3134
1386 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1387 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1388 set.
af7329f0 1389
796d5313
NC		 13902008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1391
1392 * cr16.h (cr16_num_optab): Declared.
1393
d669d37f
NC		 13942008-02-14 Hakan Ardo <hakan@debian.org>
1395
1396 PR gas/2626
1397 * avr.h (AVR_ISA_2xxe): Define.
1398
e6429699
AN		 13992008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1400
1401 * mips.h: Update copyright.
1402 (INSN_CHIP_MASK): New macro.
1403 (INSN_OCTEON): New macro.
1404 (CPU_OCTEON): New macro.
1405 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1406
e210c36b
NC		 14072008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1408
1409 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1410
14112008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1412
1413 * avr.h (AVR_ISA_USB162): Add new opcode set.
1414 (AVR_ISA_AVR3): Likewise.
1415
350cc38d
MS		 14162007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1417
1418 * mips.h (INSN_LOONGSON_2E): New.
1419 (INSN_LOONGSON_2F): New.
1420 (CPU_LOONGSON_2E): New.
1421 (CPU_LOONGSON_2F): New.
1422 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1423
56950294
MS		 14242007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1425
1426 * mips.h (INSN_ISA*): Redefine certain values as an
1427 enumeration. Update comments.
1428 (mips_isa_table): New.
1429 (ISA_MIPS*): Redefine to match enumeration.
1430 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1431 values.
1432
c3d65c1c
BE		 14332007-08-08 Ben Elliston <bje@au.ibm.com>
1434
1435 * ppc.h (PPC_OPCODE_PPCPS): New.
1436
0fdaa005
L		 14372007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1438
1439 * m68k.h: Document j K & E.
1440
14412007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1442
1443 * cr16.h: New file for CR16 target.
1444
3896c469
AM		 14452007-05-02 Alan Modra <amodra@bigpond.net.au>
1446
1447 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1448
9a2e615a
NS		 14492007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1450
1451 * m68k.h (mcfisa_c): New.
1452 (mcfusp, mcf_mask): Adjust.
1453
b84bf58a
AM		 14542007-04-20 Alan Modra <amodra@bigpond.net.au>
1455
1456 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1457 (num_powerpc_operands): Declare.
1458 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1459 (PPC_OPERAND_PLUS1): Define.
1460
831480e9 14612007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1462
1463 * i386.h (REX_MODE64): Renamed to ...
1464 (REX_W): This.
1465 (REX_EXTX): Renamed to ...
1466 (REX_R): This.
1467 (REX_EXTY): Renamed to ...
1468 (REX_X): This.
1469 (REX_EXTZ): Renamed to ...
1470 (REX_B): This.
1471
0b1cf022
L		 14722007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1473
1474 * i386.h: Add entries from config/tc-i386.h and move tables
1475 to opcodes/i386-opc.h.
1476
d796c0ad
L		 14772007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1478
1479 * i386.h (FloatDR): Removed.
1480 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1481
30ac7323
AM		 14822007-03-01 Alan Modra <amodra@bigpond.net.au>
1483
1484 * spu-insns.h: Add soma double-float insns.
1485
8b082fb1 14862007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1487 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1488
1489 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1490 (INSN_DSPR2): Add flag for DSP R2 instructions.
1491 (M_BALIGN): New macro.
1492
4eed87de
AM		 14932007-02-14 Alan Modra <amodra@bigpond.net.au>
1494
1495 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1496 and Seg3ShortFrom with Shortform.
1497
fda592e8
L		 14982007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1499
1500 PR gas/4027
1501 * i386.h (i386_optab): Put the real "test" before the pseudo
1502 one.
1503
3bdcfdf4
KH		 15042007-01-08 Kazu Hirata <kazu@codesourcery.com>
1505
1506 * m68k.h (m68010up): OR fido_a.
1507
9840d27e
KH		 15082006-12-25 Kazu Hirata <kazu@codesourcery.com>
1509
1510 * m68k.h (fido_a): New.
1511
c629cdac
KH		 15122006-12-24 Kazu Hirata <kazu@codesourcery.com>
1513
1514 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1515 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1516 values.
1517
b7d9ef37
L		 15182006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1519
1520 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1521
b138abaa
NC		 15222006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1523
1524 * score-inst.h (enum score_insn_type): Add Insn_internal.
1525
e9f53129
AM		 15262006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1527 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1528 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1529 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1530 Alan Modra <amodra@bigpond.net.au>
1531
1532 * spu-insns.h: New file.
1533 * spu.h: New file.
1534
ede602d7
AM		 15352006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1536
1537 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1538
7918206c
MM		 15392006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1540
e4e42b45 1541 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1542 in amdfam10 architecture.
1543
ef05d495
L		 15442006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1545
1546 * i386.h: Replace CpuMNI with CpuSSSE3.
1547
2d447fca 15482006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1549 Joseph Myers <joseph@codesourcery.com>
1550 Ian Lance Taylor <ian@wasabisystems.com>
1551 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1552
1553 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1554
1c0d3aa6
NC		 15552006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1556
1557 * score-datadep.h: New file.
1558 * score-inst.h: New file.
1559
c2f0420e
L		 15602006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1561
1562 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1563 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1564 movdq2q and movq2dq.
1565
050dfa73
MM		 15662006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1567 Michael Meissner <michael.meissner@amd.com>
1568
1569 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1570
15965411
L		 15712006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1572
1573 * i386.h (i386_optab): Add "nop" with memory reference.
1574
46e883c5
L		 15752006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1576
1577 * i386.h (i386_optab): Update comment for 64bit NOP.
1578
9622b051
AM		 15792006-06-06 Ben Elliston <bje@au.ibm.com>
1580 Anton Blanchard <anton@samba.org>
1581
1582 * ppc.h (PPC_OPCODE_POWER6): Define.
1583 Adjust whitespace.
1584
a9e24354
TS		 15852006-06-05 Thiemo Seufer <ths@mips.com>
1586
e4e42b45 1587 * mips.h: Improve description of MT flags.
a9e24354 1588
a596001e
RS		 15892006-05-25 Richard Sandiford <richard@codesourcery.com>
1590
1591 * m68k.h (mcf_mask): Define.
1592
d43b4baf 15932006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1594 David Ung <davidu@mips.com>
d43b4baf
TS		 1595
1596 * mips.h (enum): Add macro M_CACHE_AB.
1597
39a7806d 15982006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1599 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1600 David Ung <davidu@mips.com>
1601
1602 * mips.h: Add INSN_SMARTMIPS define.
1603
9bcd4f99 16042006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1605 David Ung <davidu@mips.com>
9bcd4f99
TS		 1606
1607 * mips.h: Defines udi bits and masks. Add description of
1608 characters which may appear in the args field of udi
1609 instructions.
1610
ef0ee844
TS		 16112006-04-26 Thiemo Seufer <ths@networkno.de>
1612
1613 * mips.h: Improve comments describing the bitfield instruction
1614 fields.
1615
f7675147
L		 16162006-04-26 Julian Brown <julian@codesourcery.com>
1617
1618 * arm.h (FPU_VFP_EXT_V3): Define constant.
1619 (FPU_NEON_EXT_V1): Likewise.
1620 (FPU_VFP_HARD): Update.
1621 (FPU_VFP_V3): Define macro.
1622 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1623
ef0ee844 16242006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1625
1626 * avr.h (AVR_ISA_PWMx): New.
1627
2da12c60
NS		 16282006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1629
1630 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1631 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1632 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1633 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1634 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1635
0715c387
PB		 16362006-03-10 Paul Brook <paul@codesourcery.com>
1637
1638 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1639
34bdd094
DA		 16402006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1641
1642 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1643 first. Correct mask of bb "B" opcode.
1644
331d2d0d
L		 16452006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1646
1647 * i386.h (i386_optab): Support Intel Merom New Instructions.
1648
62b3e311
PB		 16492006-02-24 Paul Brook <paul@codesourcery.com>
1650
1651 * arm.h: Add V7 feature bits.
1652
59cf82fe
L		 16532006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1654
1655 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1656
e74cfd16
PB		 16572006-01-31 Paul Brook <paul@codesourcery.com>
1658 Richard Earnshaw <rearnsha@arm.com>
1659
1660 * arm.h: Use ARM_CPU_FEATURE.
1661 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1662 (arm_feature_set): Change to a structure.
1663 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1664 ARM_FEATURE): New macros.
1665
5b3f8a92
HPN		 16662005-12-07 Hans-Peter Nilsson <hp@axis.com>
1667
1668 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1669 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1670 (ADD_PC_INCR_OPCODE): Don't define.
1671
cb712a9e
L		 16722005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1673
1674 PR gas/1874
1675 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1676
0499d65b
TS		 16772005-11-14 David Ung <davidu@mips.com>
1678
1679 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1680 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1681 save/restore encoding of the args field.
1682
ea5ca089
DB		 16832005-10-28 Dave Brolley <brolley@redhat.com>
1684
1685 Contribute the following changes:
1686 2005-02-16 Dave Brolley <brolley@redhat.com>
1687
1688 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1689 cgen_isa_mask_* to cgen_bitset_*.
1690 * cgen.h: Likewise.
1691
16175d96
DB		 1692 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1693
1694 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1695 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1696 (CGEN_CPU_TABLE): Make isas a ponter.
1697
1698 2003-09-29 Dave Brolley <brolley@redhat.com>
1699
1700 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1701 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1702 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1703
1704 2002-12-13 Dave Brolley <brolley@redhat.com>
1705
1706 * cgen.h (symcat.h): #include it.
1707 (cgen-bitset.h): #include it.
1708 (CGEN_ATTR_VALUE_TYPE): Now a union.
1709 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1710 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1711 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1712 * cgen-bitset.h: New file.
1713
3c9b82ba
NC		 17142005-09-30 Catherine Moore <clm@cm00re.com>
1715
1716 * bfin.h: New file.
1717
6a2375c6
JB		 17182005-10-24 Jan Beulich <jbeulich@novell.com>
1719
1720 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1721 indirect operands.
1722
c06a12f8
DA		 17232005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1724
1725 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1726 Add FLAG_STRICT to pa10 ftest opcode.
1727
4d443107
DA		 17282005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1729
1730 * hppa.h (pa_opcodes): Remove lha entries.
1731
f0a3b40f
DA		 17322005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1733
1734 * hppa.h (FLAG_STRICT): Revise comment.
1735 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1736 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1737 entries for "fdc".
1738
e210c36b
NC		 17392005-09-30 Catherine Moore <clm@cm00re.com>
1740
1741 * bfin.h: New file.
1742
1b7e1362
DA		 17432005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1744
1745 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1746
089b39de
CF		 17472005-09-06 Chao-ying Fu <fu@mips.com>
1748
1749 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1750 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1751 define.
1752 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1753 (INSN_ASE_MASK): Update to include INSN_MT.
1754 (INSN_MT): New define for MT ASE.
1755
93c34b9b
CF		 17562005-08-25 Chao-ying Fu <fu@mips.com>
1757
1758 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1759 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1760 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1761 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1762 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1763 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1764 instructions.
1765 (INSN_DSP): New define for DSP ASE.
1766
848cf006
AM		 17672005-08-18 Alan Modra <amodra@bigpond.net.au>
1768
1769 * a29k.h: Delete.
1770
36ae0db3
DJ		 17712005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1772
1773 * ppc.h (PPC_OPCODE_E300): Define.
1774
8c929562
MS		 17752005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1776
1777 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1778
f7b8cccc
DA		 17792005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1780
1781 PR gas/336
1782 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1783 and pitlb.
1784
8b5328ac
JB		 17852005-07-27 Jan Beulich <jbeulich@novell.com>
1786
1787 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1788 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1789 Add movq-s as 64-bit variants of movd-s.
1790
f417d200
DA		 17912005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1792
18b3bdfc
DA		 1793 * hppa.h: Fix punctuation in comment.
1794
f417d200
DA		 1795 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1796 implicit space-register addressing. Set space-register bits on opcodes
1797 using implicit space-register addressing. Add various missing pa20
1798 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1799 space-register addressing. Use "fE" instead of "fe" in various
1800 fstw opcodes.
1801
9a145ce6
JB		 18022005-07-18 Jan Beulich <jbeulich@novell.com>
1803
1804 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1805
90700ea2
L		 18062007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1807
1808 * i386.h (i386_optab): Support Intel VMX Instructions.
1809
48f130a8
DA		 18102005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1811
1812 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1813
30123838
JB		 18142005-07-05 Jan Beulich <jbeulich@novell.com>
1815
1816 * i386.h (i386_optab): Add new insns.
1817
47b0e7ad
NC		 18182005-07-01 Nick Clifton <nickc@redhat.com>
1819
1820 * sparc.h: Add typedefs to structure declarations.
1821
b300c311
L		 18222005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1823
1824 PR 1013
1825 * i386.h (i386_optab): Update comments for 64bit addressing on
1826 mov. Allow 64bit addressing for mov and movq.
1827
2db495be
DA		 18282005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1829
1830 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1831 respectively, in various floating-point load and store patterns.
1832
caa05036
DA		 18332005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1834
1835 * hppa.h (FLAG_STRICT): Correct comment.
1836 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1837 PA 2.0 mneumonics when equivalent. Entries with cache control
1838 completers now require PA 1.1. Adjust whitespace.
1839
f4411256
AM		 18402005-05-19 Anton Blanchard <anton@samba.org>
1841
1842 * ppc.h (PPC_OPCODE_POWER5): Define.
1843
e172dbf8
NC		 18442005-05-10 Nick Clifton <nickc@redhat.com>
1845
1846 * Update the address and phone number of the FSF organization in
1847 the GPL notices in the following files:
1848 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1849 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1850 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1851 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1852 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1853 tic54x.h, tic80.h, v850.h, vax.h
1854
e44823cf
JB		 18552005-05-09 Jan Beulich <jbeulich@novell.com>
1856
1857 * i386.h (i386_optab): Add ht and hnt.
1858
791fe849
MK		 18592005-04-18 Mark Kettenis <kettenis@gnu.org>
1860
1861 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1862 Add xcrypt-ctr. Provide aliases without hyphens.
1863
faa7ef87
L		 18642005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1865
a63027e5
L		 1866 Moved from ../ChangeLog
1867
faa7ef87
L		 1868 2005-04-12 Paul Brook <paul@codesourcery.com>
1869 * m88k.h: Rename psr macros to avoid conflicts.
1870
1871 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1872 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1873 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1874 and ARM_ARCH_V6ZKT2.
1875
1876 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1877 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1878 Remove redundant instruction types.
1879 (struct argument): X_op - new field.
1880 (struct cst4_entry): Remove.
1881 (no_op_insn): Declare.
1882
1883 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1884 * crx.h (enum argtype): Rename types, remove unused types.
1885
1886 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1887 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1888 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1889 (enum operand_type): Rearrange operands, edit comments.
1890 replace us<N> with ui<N> for unsigned immediate.
1891 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1892 displacements (respectively).
1893 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1894 (instruction type): Add NO_TYPE_INS.
1895 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1896 (operand_entry): New field - 'flags'.
1897 (operand flags): New.
1898
1899 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1900 * crx.h (operand_type): Remove redundant types i3, i4,
1901 i5, i8, i12.
1902 Add new unsigned immediate types us3, us4, us5, us16.
1903
bc4bd9ab
MK		 19042005-04-12 Mark Kettenis <kettenis@gnu.org>
1905
1906 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1907 adjust them accordingly.
1908
373ff435
JB		 19092005-04-01 Jan Beulich <jbeulich@novell.com>
1910
1911 * i386.h (i386_optab): Add rdtscp.
1912
4cc91dba
L		 19132005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1914
1915 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 1916 between memory and segment register. Allow movq for moving between
1917 general-purpose register and segment register.
4cc91dba 1918
9ae09ff9
JB		 19192005-02-09 Jan Beulich <jbeulich@novell.com>
1920
1921 PR gas/707
1922 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1923 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1924 fnstsw.
1925
638e7a64
NS		 19262006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1927
1928 * m68k.h (m68008, m68ec030, m68882): Remove.
1929 (m68k_mask): New.
1930 (cpu_m68k, cpu_cf): New.
1931 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1932 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1933
90219bd0
AO		 19342005-01-25 Alexandre Oliva <aoliva@redhat.com>
1935
1936 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1937 * cgen.h (enum cgen_parse_operand_type): Add
1938 CGEN_PARSE_OPERAND_SYMBOLIC.
1939
239cb185
FF		 19402005-01-21 Fred Fish <fnf@specifixinc.com>
1941
1942 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1943 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1944 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1945
dc9a9f39
FF		 19462005-01-19 Fred Fish <fnf@specifixinc.com>
1947
1948 * mips.h (struct mips_opcode): Add new pinfo2 member.
1949 (INSN_ALIAS): New define for opcode table entries that are
1950 specific instances of another entry, such as 'move' for an 'or'
1951 with a zero operand.
1952 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1953 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1954
98e7aba8
ILT		 19552004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1956
1957 * mips.h (CPU_RM9000): Define.
1958 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1959
37edbb65
JB		 19602004-11-25 Jan Beulich <jbeulich@novell.com>
1961
1962 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1963 to/from test registers are illegal in 64-bit mode. Add missing
1964 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1965 (previously one had to explicitly encode a rex64 prefix). Re-enable
1966 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1967 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1968
19692004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 1970
1971 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1972 available only with SSE2. Change the MMX additions introduced by SSE
1973 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1974 instructions by their now designated identifier (since combining i686
1975 and 3DNow! does not really imply 3DNow!A).
1976
f5c7edf4
AM		 19772004-11-19 Alan Modra <amodra@bigpond.net.au>
1978
1979 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1980 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1981
7499d566
NC		 19822004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1983 Vineet Sharma <vineets@noida.hcltech.com>
1984
1985 * maxq.h: New file: Disassembly information for the maxq port.
1986
bcb9eebe
L		 19872004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1988
1989 * i386.h (i386_optab): Put back "movzb".
1990
94bb3d38
HPN		 19912004-11-04 Hans-Peter Nilsson <hp@axis.com>
1992
1993 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1994 comments. Remove member cris_ver_sim. Add members
1995 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1996 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1997 (struct cris_support_reg, struct cris_cond15): New types.
1998 (cris_conds15): Declare.
1999 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2000 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2001 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2002 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2003 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2004 SIZE_FIELD_UNSIGNED.
2005
37edbb65 20062004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2007
2008 * i386.h (sldx_Suf): Remove.
2009 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2010 (q_FP): Define, implying no REX64.
2011 (x_FP, sl_FP): Imply FloatMF.
2012 (i386_optab): Split reg and mem forms of moving from segment registers
2013 so that the memory forms can ignore the 16-/32-bit operand size
2014 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2015 all non-floating-point instructions. Unite 32- and 64-bit forms of
2016 movsx, movzx, and movd. Adjust floating point operations for the above
2017 changes to the *FP macros. Add DefaultSize to floating point control
2018 insns operating on larger memory ranges. Remove left over comments
2019 hinting at certain insns being Intel-syntax ones where the ones
2020 actually meant are already gone.
2021
48c9f030
NC		 20222004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2023
2024 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2025 instruction type.
2026
0dd132b6
NC		 20272004-09-30 Paul Brook <paul@codesourcery.com>
2028
2029 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2030 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2031
23794b24
MM		 20322004-09-11 Theodore A. Roth <troth@openavr.org>
2033
2034 * avr.h: Add support for
2035 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2036
2a309db0
AM		 20372004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2038
2039 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2040
b18c562e
NC		 20412004-08-24 Dmitry Diky <diwil@spec.ru>
2042
2043 * msp430.h (msp430_opc): Add new instructions.
2044 (msp430_rcodes): Declare new instructions.
2045 (msp430_hcodes): Likewise..
2046
45d313cd
NC		 20472004-08-13 Nick Clifton <nickc@redhat.com>
2048
2049 PR/301
2050 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2051 processors.
2052
30d1c836
ML		 20532004-08-30 Michal Ludvig <mludvig@suse.cz>
2054
2055 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2056
9a45f1c2
L		 20572004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2058
2059 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2060
543613e9
NC		 20612004-07-21 Jan Beulich <jbeulich@novell.com>
2062
2063 * i386.h: Adjust instruction descriptions to better match the
2064 specification.
2065
b781e558
RE		 20662004-07-16 Richard Earnshaw <rearnsha@arm.com>
2067
2068 * arm.h: Remove all old content. Replace with architecture defines
2069 from gas/config/tc-arm.c.
2070
8577e690
AS		 20712004-07-09 Andreas Schwab <schwab@suse.de>
2072
2073 * m68k.h: Fix comment.
2074
1fe1f39c
NC		 20752004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2076
2077 * crx.h: New file.
2078
1d9f512f
AM		 20792004-06-24 Alan Modra <amodra@bigpond.net.au>
2080
2081 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2082
be8c092b
NC		 20832004-05-24 Peter Barada <peter@the-baradas.com>
2084
2085 * m68k.h: Add 'size' to m68k_opcode.
2086
6b6e92f4
NC		 20872004-05-05 Peter Barada <peter@the-baradas.com>
2088
2089 * m68k.h: Switch from ColdFire chip name to core variant.
2090
20912004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2092
2093 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2094 descriptions for new EMAC cases.
2095 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2096 handle Motorola MAC syntax.
2097 Allow disassembly of ColdFire V4e object files.
2098
fdd12ef3
AM		 20992004-03-16 Alan Modra <amodra@bigpond.net.au>
2100
2101 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2102
3922a64c
L		 21032004-03-12 Jakub Jelinek <jakub@redhat.com>
2104
2105 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2106
1f45d988
ML		 21072004-03-12 Michal Ludvig <mludvig@suse.cz>
2108
2109 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2110
0f10071e
ML		 21112004-03-12 Michal Ludvig <mludvig@suse.cz>
2112
2113 * i386.h (i386_optab): Added xstore/xcrypt insns.
2114
3255318a
NC		 21152004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2116
2117 * h8300.h (32bit ldc/stc): Add relaxing support.
2118
ca9a79a1 21192004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2120
ca9a79a1
NC		 2121 * h8300.h (BITOP): Pass MEMRELAX flag.
2122
875a0b14
NC		 21232004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2124
2125 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2126 except for the H8S.
252b5132 2127
c9e214e5 2128For older changes see ChangeLog-9103
252b5132 2129\f
4b95cf5c 2130Copyright (C) 2004-2014 Free Software Foundation, Inc.
752937aa
NC		 2131
2132Copying and distribution of this file, with or without modification,
2133are permitted in any medium without royalty provided the copyright
2134notice and this notice are preserved.
2135
252b5132 2136Local Variables:
c9e214e5
AM		 2137mode: change-log
2138left-margin: 8
2139fill-column: 74
252b5132
RH		 2140version-control: never
2141End:
GDB Binutils - Deliverables
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