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Fix compile time warnings generated when compiling with clang.
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
b6518b38
NC		 12015-09-23 Nick Clifton <nickc@redhat.com>
2
3 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
4 shifting.
5
f04265ec
NC		 62015-09-22 Nick Clifton <nickc@redhat.com>
7
8 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
9
7bdf96ef
NC		 102015-09-09 Daniel Santos <daniel.santos@pobox.com>
11
12 * visium.h (gen_reg_table): Make static.
13 (fp_reg_table): Likewise.
14 (cc_table): Likewise.
15
f33026a9
MW		 162015-07-20 Matthew Wahab <matthew.wahab@arm.com>
17
18 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
19 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
20 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
21 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
22
ef5a96d5
AM		 232015-07-03 Alan Modra <amodra@gmail.com>
24
25 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
26
c8c8175b
SL		 272015-07-01 Sandra Loosemore <sandra@codesourcery.com>
28 Cesar Philippidis <cesar@codesourcery.com>
29
30 * nios2.h (enum iw_format_type): Add R2 formats.
31 (enum overflow_type): Add signed_immed12_overflow and
32 enumeration_overflow for R2.
33 (struct nios2_opcode): Document new argument letters for R2.
34 (REG_3BIT, REG_LDWM, REG_POP): Define.
35 (includes): Include nios2r2.h.
36 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
37 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
38 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
39 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
40 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
41 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
42 Declare.
43 * nios2r2.h: New file.
44
11a0cf2e
PB		 452015-06-19 Peter Bergner <bergner@vnet.ibm.com>
46
47 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
48 (ppc_optional_operand_value): New inline function.
49
88f0ea34
MW		 502015-06-04 Matthew Wahab <matthew.wahab@arm.com>
51
52 * aarch64.h (AARCH64_V8_1): New.
53
a5932920
MW		 542015-06-03 Matthew Wahab <matthew.wahab@arm.com>
55
56 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
57 (ARM_ARCH_V8_1A): New.
58 (ARM_ARCH_V8_1A_FP): New.
59 (ARM_ARCH_V8_1A_SIMD): New.
60 (ARM_ARCH_V8_1A_CRYPTOV1): New.
61 (ARM_FEATURE_CORE): New.
62
ddfded2f
MW		 632015-06-02 Matthew Wahab <matthew.wahab@arm.com>
64
65 * arm.h (ARM_EXT2_PAN): New.
66 (ARM_FEATURE_CORE_HIGH): New.
67
1af1dd51
MW		 682015-06-02 Matthew Wahab <matthew.wahab@arm.com>
69
70 * arm.h (ARM_FEATURE_ALL): New.
71
9e1f0fa7
MW		 722015-06-02 Matthew Wahab <matthew.wahab@arm.com>
73
74 * aarch64.h (AARCH64_FEATURE_RDMA): New.
75
290806fd
MW		 762015-06-02 Matthew Wahab <matthew.wahab@arm.com>
77
78 * aarch64.h (AARCH64_FEATURE_LOR): New.
79
f21cce2c
MW		 802015-06-01 Matthew Wahab <matthew.wahab@arm.com>
81
82 * aarch64.h (AARCH64_FEATURE_PAN): New.
83 (aarch64_sys_reg_supported_p): Declare.
84 (aarch64_pstatefield_supported_p): Declare.
85
0952813b
DD		 862015-04-30 DJ Delorie <dj@redhat.com>
87
88 * rl78.h (RL78_Dis_Isa): New.
89 (rl78_decode_opcode): Add ISA parameter.
90
823d2571
TG		 912015-03-24 Terry Guo <terry.guo@arm.com>
92
93 * arm.h (arm_feature_set): Extended to provide more available bits.
94 (ARM_ANY): Updated to follow above new definition.
95 (ARM_CPU_HAS_FEATURE): Likewise.
96 (ARM_CPU_IS_ANY): Likewise.
97 (ARM_MERGE_FEATURE_SETS): Likewise.
98 (ARM_CLEAR_FEATURE): Likewise.
99 (ARM_FEATURE): Likewise.
100 (ARM_FEATURE_COPY): New macro.
101 (ARM_FEATURE_EQUAL): Likewise.
102 (ARM_FEATURE_ZERO): Likewise.
103 (ARM_FEATURE_CORE_EQUAL): Likewise.
104 (ARM_FEATURE_LOW): Likewise.
105 (ARM_FEATURE_CORE_LOW): Likewise.
106 (ARM_FEATURE_CORE_COPROC): Likewise.
107
f63c1776
PA		 1082015-02-19 Pedro Alves <palves@redhat.com>
109
110 * cgen.h [__cplusplus]: Wrap in extern "C".
111 * msp430-decode.h [__cplusplus]: Likewise.
112 * nios2.h [__cplusplus]: Likewise.
113 * rl78.h [__cplusplus]: Likewise.
114 * rx.h [__cplusplus]: Likewise.
115 * tilegx.h [__cplusplus]: Likewise.
116
3f8107ab
AM		 1172015-01-28 James Bowman <james.bowman@ftdichip.com>
118
119 * ft32.h: New file.
120
1e2e8c52
AK		 1212015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
122
123 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
124
b90efa5b
AM		 1252015-01-01 Alan Modra <amodra@gmail.com>
126
127 Update year range in copyright notice of all files.
128
bffb6004
AG		 1292014-12-27 Anthony Green <green@moxielogic.com>
130
131 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
132 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
133
1945cfa5
EB		 1342014-12-06 Eric Botcazou <ebotcazou@adacore.com>
135
136 * visium.h: New file.
137
d306ce58
SL		 1382014-11-28 Sandra Loosemore <sandra@codesourcery.com>
139
140 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
141 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
142 (NIOS2_INSN_OPTARG): Renumber.
143
b4714c7c
SL		 1442014-11-06 Sandra Loosemore <sandra@codesourcery.com>
145
146 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
147 declaration. Fix obsolete comment.
148
96ba4233
SL		 1492014-10-23 Sandra Loosemore <sandra@codesourcery.com>
150
151 * nios2.h (enum iw_format_type): New.
152 (struct nios2_opcode): Update comments. Add size and format fields.
153 (NIOS2_INSN_OPTARG): New.
154 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
155 (struct nios2_reg): Add regtype field.
156 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
157 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
158 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
159 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
160 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
161 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
162 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
163 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
164 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
165 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
166 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
167 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
168 (OP_MASK_OP, OP_SH_OP): Delete.
169 (OP_MASK_IOP, OP_SH_IOP): Delete.
170 (OP_MASK_IRD, OP_SH_IRD): Delete.
171 (OP_MASK_IRT, OP_SH_IRT): Delete.
172 (OP_MASK_IRS, OP_SH_IRS): Delete.
173 (OP_MASK_ROP, OP_SH_ROP): Delete.
174 (OP_MASK_RRD, OP_SH_RRD): Delete.
175 (OP_MASK_RRT, OP_SH_RRT): Delete.
176 (OP_MASK_RRS, OP_SH_RRS): Delete.
177 (OP_MASK_JOP, OP_SH_JOP): Delete.
178 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
179 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
180 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
181 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
182 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
183 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
184 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
185 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
186 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
187 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
188 (OP_MASK_<insn>, OP_MASK): Delete.
189 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
190 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
191 Include nios2r1.h to define new instruction opcode constants
192 and accessors.
193 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
194 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
195 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
196 (NUMOPCODES, NUMREGISTERS): Delete.
197 * nios2r1.h: New file.
198
0b6be415
JM		 1992014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
200
201 * sparc.h (HWCAP2_VIS3B): Documentation improved.
202
3d68f91c
JM		 2032014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
204
205 * sparc.h (sparc_opcode): new field `hwcaps2'.
206 (HWCAP2_FJATHPLUS): New define.
207 (HWCAP2_VIS3B): Likewise.
208 (HWCAP2_ADP): Likewise.
209 (HWCAP2_SPARC5): Likewise.
210 (HWCAP2_MWAIT): Likewise.
211 (HWCAP2_XMPMUL): Likewise.
212 (HWCAP2_XMONT): Likewise.
213 (HWCAP2_NSEC): Likewise.
214 (HWCAP2_FJATHHPC): Likewise.
215 (HWCAP2_FJDES): Likewise.
216 (HWCAP2_FJAES): Likewise.
217 Document the new operand kind `{', corresponding to the mcdper
218 ancillary state register.
219 Document the new operand kind }, which represents frsd floating
220 point registers (double precision) which must be the same than
221 frs1 in its containing instruction.
222
40c7a7cb
KLC		 2232014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
224
72f4393d 225 * nds32.h: Add new opcode declaration.
40c7a7cb 226
7361da2c
AB		 2272014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
228 Matthew Fortune <matthew.fortune@imgtec.com>
229
230 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
231 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
232 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
233 +I, +O, +R, +:, +\, +", +;
234 (mips_check_prev_operand): New struct.
235 (INSN2_FORBIDDEN_SLOT): New define.
236 (INSN_ISA32R6): New define.
237 (INSN_ISA64R6): New define.
238 (INSN_UPTO32R6): New define.
239 (INSN_UPTO64R6): New define.
240 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
241 (ISA_MIPS32R6): New define.
242 (ISA_MIPS64R6): New define.
243 (CPU_MIPS32R6): New define.
244 (CPU_MIPS64R6): New define.
245 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
246
ee804238
JW		 2472014-09-03 Jiong Wang <jiong.wang@arm.com>
248
249 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
250 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
251 (aarch64_insn_class): Add lse_atomic.
252 (F_LSE_SZ): New field added.
253 (opcode_has_special_coder): Recognize F_LSE_SZ.
254
5575639b
MR		 2552014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
256
257 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
258 over to `+J'.
259
43885403
MF		 2602014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
261
262 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
263 (INSN_LOAD_COPROC): New define.
264 (INSN_COPROC_MOVE_DELAY): Rename to...
265 (INSN_COPROC_MOVE): New define.
266
f36e8886 2672014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
72f4393d
L		 268 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
269 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
270 Soundararajan <Sounderarajan.D@atmel.com>
f36e8886
BS		 271
272 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
273 (AVR_ISA_2xxxa): Define ISA without LPM.
274 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
275 Add doc for contraint used in 16 bit lds/sts.
276 Adjust ISA group for icall, ijmp, pop and push.
277 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
278
00b32ff2
NC		 2792014-05-19 Nick Clifton <nickc@redhat.com>
280
281 * msp430.h (struct msp430_operand_s): Add vshift field.
282
ae52f483
AB		 2832014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
284
285 * mips.h (INSN_ISA_MASK): Updated.
286 (INSN_ISA32R3): New define.
287 (INSN_ISA32R5): New define.
288 (INSN_ISA64R3): New define.
289 (INSN_ISA64R5): New define.
290 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
291 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
292 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
293 mips64r5.
294 (INSN_UPTO32R3): New define.
295 (INSN_UPTO32R5): New define.
296 (INSN_UPTO64R3): New define.
297 (INSN_UPTO64R5): New define.
298 (ISA_MIPS32R3): New define.
299 (ISA_MIPS32R5): New define.
300 (ISA_MIPS64R3): New define.
301 (ISA_MIPS64R5): New define.
302 (CPU_MIPS32R3): New define.
303 (CPU_MIPS32R5): New define.
304 (CPU_MIPS64R3): New define.
305 (CPU_MIPS64R5): New define.
306
3efe9ec5
RS		 3072014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
308
309 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
310
73589c9d
CS		 3112014-04-22 Christian Svensson <blue@cmd.nu>
312
313 * or32.h: Delete.
314
4b95cf5c
AM		 3152014-03-05 Alan Modra <amodra@gmail.com>
316
317 Update copyright years.
318
e269fea7
AB		 3192013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
320
321 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
322 microMIPS.
323
35c08157
KLC		 3242013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
325 Wei-Cheng Wang <cole945@gmail.com>
326
327 * nds32.h: New file for Andes NDS32.
328
594d8fa8
MF		 3292013-12-07 Mike Frysinger <vapier@gentoo.org>
330
331 * bfin.h: Remove +x file mode.
332
87b8eed7
YZ		 3332013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
334
335 * aarch64.h (aarch64_pstatefields): Change element type to
336 aarch64_sys_reg.
337
c9fb6e58
YZ		 3382013-11-18 Renlin Li <Renlin.Li@arm.com>
339
340 * arm.h (ARM_AEXT_V7VE): New define.
341 (ARM_ARCH_V7VE): New define.
342 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
343
a203d9b7
YZ		 3442013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
345
346 Revert
347
348 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
349
350 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
351 (aarch64_sys_reg_writeonly_p): Ditto.
352
75468c93
YZ		 3532013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
354
355 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
356 (aarch64_sys_reg_writeonly_p): Ditto.
357
49eec193
YZ		 3582013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
359
360 * aarch64.h (aarch64_sys_reg): New typedef.
361 (aarch64_sys_regs): Change to define with the new type.
362 (aarch64_sys_reg_deprecated_p): Declare.
363
68a64283
YZ		 3642013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
365
366 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
367 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
368
387a82f1
CF		 3692013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
370
371 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
372 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
373 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
374 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
375 For MIPS, update extension character sequences after +.
376 (ASE_MSA): New define.
377 (ASE_MSA64): New define.
378 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
379 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
380 For microMIPS, update extension character sequences after +.
381
9aff4b7a
NC		 3822013-08-23 Yuri Chornoivan <yurchor@ukr.net>
383
384 PR binutils/15834
385 * i960.h: Fix typos.
386
e423441d
RS		 3872013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
388
389 * mips.h: Remove references to "+I" and imm2_expr.
390
5e0dc5ba
RS		 3912013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
392
393 * mips.h (M_DEXT, M_DINS): Delete.
394
0f35dbc4
RS		 3952013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
396
397 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
398 (mips_optional_operand_p): New function.
399
14daeee3
RS		 4002013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
401 Richard Sandiford <rdsandiford@googlemail.com>
402
403 * mips.h: Document new VU0 operand characters.
404 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
405 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
406 (OP_REG_R5900_ACC): New mips_reg_operand_types.
407 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
408 (mips_vu0_channel_mask): Declare.
409
3ccad066
RS		 4102013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
411
412 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
413 (mips_int_operand_min, mips_int_operand_max): New functions.
414 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
415
fc76e730
RS		 4162013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
417
418 * mips.h (mips_decode_reg_operand): New function.
419 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
420 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
421 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
422 New macros.
423 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
424 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
425 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
426 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
427 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
428 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
429 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
430 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
431 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
432 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
433 macros to cover the gaps.
434 (INSN2_MOD_SP): Replace with...
435 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
436 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
437 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
438 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
439 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
440 Delete.
441
26545944
RS		 4422013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
443
444 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
445 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
446 (MIPS16_INSN_COND_BRANCH): Delete.
447
7e8b059b
L		 4482013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
449 Kirill Yukhin <kirill.yukhin@intel.com>
450 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
451
452 * i386.h (BND_PREFIX_OPCODE): New.
453
c3c07478
RS		 4542013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
455
456 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
457 OP_SAVE_RESTORE_LIST.
458 (decode_mips16_operand): Declare.
459
ab902481
RS		 4602013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
461
462 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
463 (mips_operand, mips_int_operand, mips_mapped_int_operand)
464 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
465 (mips_pcrel_operand): New structures.
466 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
467 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
468 (decode_mips_operand, decode_micromips_operand): Declare.
469
cc537e56
RS		 4702013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
471
472 * mips.h: Document MIPS16 "I" opcode.
473
f2ae14a1
RS		 4742013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
475
476 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
477 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
478 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
479 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
480 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
481 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
482 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
483 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
484 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
485 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
486 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
487 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
488 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
489 Rename to...
490 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
491 (M_USD_AB): ...these.
492
5c324c16
RS		 4932013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
494
495 * mips.h: Remove documentation of "[" and "]". Update documentation
496 of "k" and the MDMX formats.
497
23e69e47
RS		 4982013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
499
500 * mips.h: Update documentation of "+s" and "+S".
501
27c5c572
RS		 5022013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
503
504 * mips.h: Document "+i".
505
e76ff5ab
RS		 5062013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
507
508 * mips.h: Remove "mi" documentation. Update "mh" documentation.
509 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
510 Delete.
511 (INSN2_WRITE_GPR_MHI): Rename to...
512 (INSN2_WRITE_GPR_MH): ...this.
513
fa7616a4
RS		 5142013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
515
516 * mips.h: Remove documentation of "+D" and "+T".
517
18870af7
RS		 5182013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
519
520 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
521 Use "source" rather than "destination" for microMIPS "G".
522
833794fc
MR		 5232013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
524
525 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
526 values.
527
c3678916
RS		 5282013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
529
530 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
531
7f3c4072
CM		 5322013-06-17 Catherine Moore <clm@codesourcery.com>
533 Maciej W. Rozycki <macro@codesourcery.com>
534 Chao-Ying Fu <fu@mips.com>
535
536 * mips.h (OP_SH_EVAOFFSET): Define.
537 (OP_MASK_EVAOFFSET): Define.
538 (INSN_ASE_MASK): Delete.
539 (ASE_EVA): Define.
540 (M_CACHEE_AB, M_CACHEE_OB): New.
541 (M_LBE_OB, M_LBE_AB): New.
542 (M_LBUE_OB, M_LBUE_AB): New.
543 (M_LHE_OB, M_LHE_AB): New.
544 (M_LHUE_OB, M_LHUE_AB): New.
545 (M_LLE_AB, M_LLE_OB): New.
546 (M_LWE_OB, M_LWE_AB): New.
547 (M_LWLE_AB, M_LWLE_OB): New.
548 (M_LWRE_AB, M_LWRE_OB): New.
549 (M_PREFE_AB, M_PREFE_OB): New.
550 (M_SCE_AB, M_SCE_OB): New.
551 (M_SBE_OB, M_SBE_AB): New.
552 (M_SHE_OB, M_SHE_AB): New.
553 (M_SWE_OB, M_SWE_AB): New.
554 (M_SWLE_AB, M_SWLE_OB): New.
555 (M_SWRE_AB, M_SWRE_OB): New.
556 (MICROMIPSOP_SH_EVAOFFSET): Define.
557 (MICROMIPSOP_MASK_EVAOFFSET): Define.
558
0c8fe7cf
SL		 5592013-06-12 Sandra Loosemore <sandra@codesourcery.com>
560
561 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
562
c77c0862
RS		 5632013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
564
565 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
566
b015e599
AP		 5672013-05-09 Andrew Pinski <apinski@cavium.com>
568
569 * mips.h (OP_MASK_CODE10): Correct definition.
570 (OP_SH_CODE10): Likewise.
571 Add a comment that "+J" is used now for OP_*CODE10.
572 (INSN_ASE_MASK): Update.
573 (INSN_VIRT): New macro.
574 (INSN_VIRT64): New macro
575
13761a11
NC		 5762013-05-02 Nick Clifton <nickc@redhat.com>
577
578 * msp430.h: Add patterns for MSP430X instructions.
579
0afd1215
DM		 5802013-04-06 David S. Miller <davem@davemloft.net>
581
582 * sparc.h (F_PREFERRED): Define.
583 (F_PREF_ALIAS): Define.
584
41702d50
NC		 5852013-04-03 Nick Clifton <nickc@redhat.com>
586
587 * v850.h (V850_INVERSE_PCREL): Define.
588
e21e1a51
NC		 5892013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
590
591 PR binutils/15068
592 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
593
51dcdd4d
NC		 5942013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
595
596 PR binutils/15068
597 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
598 Add 16-bit opcodes.
599 * tic6xc-opcode-table.h: Add 16-bit insns.
600 * tic6x.h: Add support for 16-bit insns.
601
81f5558e
NC		 6022013-03-21 Michael Schewe <michael.schewe@gmx.net>
603
604 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
605 and mov.b/w/l Rs,@(d:32,ERd).
606
165546ad
NC		 6072013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
608
609 PR gas/15082
610 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
611 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
612 tic6x_operand_xregpair operand coding type.
613 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
614 opcode field, usu ORXREGD1324 for the src2 operand and remove the
615 TIC6X_FLAG_NO_CROSS.
616
795b8e6b
NC		 6172013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
618
619 PR gas/15095
620 * tic6x.h (enum tic6x_coding_method): Add
621 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
622 separately the msb and lsb of a register pair. This is needed to
623 encode the opcodes in the same way as TI assembler does.
624 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
625 and rsqrdp opcodes to use the new field coding types.
626
dd5181d5
KT		 6272013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
628
629 * arm.h (CRC_EXT_ARMV8): New constant.
630 (ARCH_CRC_ARMV8): New macro.
631
e60bb1dd
YZ		 6322013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
633
634 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
635
36591ba1 6362013-02-06 Sandra Loosemore <sandra@codesourcery.com>
72f4393d 637 Andrew Jenner <andrew@codesourcery.com>
36591ba1
SL		 638
639 Based on patches from Altera Corporation.
640
641 * nios2.h: New file.
642
e30181a5
YZ		 6432013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
644
645 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
646
0c9573f4
NC		 6472013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
648
649 PR gas/15069
650 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
651
981dc7f1
NC		 6522013-01-24 Nick Clifton <nickc@redhat.com>
653
654 * v850.h: Add e3v5 support.
655
f5555712
YZ		 6562013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
657
658 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
659
5817ffd1
PB		 6602013-01-10 Peter Bergner <bergner@vnet.ibm.com>
661
662 * ppc.h (PPC_OPCODE_POWER8): New define.
663 (PPC_OPCODE_HTM): Likewise.
664
a3c62988
NC		 6652013-01-10 Will Newton <will.newton@imgtec.com>
666
667 * metag.h: New file.
668
73335eae
NC		 6692013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
670
671 * cr16.h (make_instruction): Rename to cr16_make_instruction.
672 (match_opcode): Rename to cr16_match_opcode.
673
e407c74b
NC		 6742013-01-04 Juergen Urban <JuergenUrban@gmx.de>
675
676 * mips.h: Add support for r5900 instructions including lq and sq.
677
bab4becb
NC		 6782013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
679
680 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
681 (make_instruction,match_opcode): Added function prototypes.
682 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
683
776fc418
AM		 6842012-11-23 Alan Modra <amodra@gmail.com>
685
686 * ppc.h (ppc_parse_cpu): Update prototype.
687
f05682d4
DA		 6882012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
689
690 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
691 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
692
cfc72779
AK		 6932012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
694
695 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
696
b3e14eda
L		 6972012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
698
699 * ia64.h (ia64_opnd): Add new operand types.
700
2c63854f
DM		 7012012-08-21 David S. Miller <davem@davemloft.net>
702
703 * sparc.h (F3F4): New macro.
704
a06ea964 7052012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 706 Laurent Desnogues <laurent.desnogues@arm.com>
707 Jim MacArthur <jim.macarthur@arm.com>
708 Marcus Shawcroft <marcus.shawcroft@arm.com>
709 Nigel Stephens <nigel.stephens@arm.com>
710 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
711 Richard Earnshaw <rearnsha@arm.com>
712 Sofiane Naci <sofiane.naci@arm.com>
713 Tejas Belagod <tejas.belagod@arm.com>
714 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 715
716 * aarch64.h: New file.
717
35d0a169 7182012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 719 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 720
721 * mips.h (mips_opcode): Add the exclusions field.
722 (OPCODE_IS_MEMBER): Remove macro.
723 (cpu_is_member): New inline function.
724 (opcode_is_member): Likewise.
725
03f66e8a 7262012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 727 Catherine Moore <clm@codesourcery.com>
728 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 729
730 * mips.h: Document microMIPS DSP ASE usage.
731 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
732 microMIPS DSP ASE support.
733 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
734 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
735 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
736 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
737 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
738 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
739 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
740
9d7b4c23
MR		 7412012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
742
743 * mips.h: Fix a typo in description.
744
76e879f8
NC		 7452012-06-07 Georg-Johann Lay <avr@gjlay.de>
746
747 * avr.h: (AVR_ISA_XCH): New define.
748 (AVR_ISA_XMEGA): Use it.
749 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
750
6927f982
NC		 7512012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
752
753 * m68hc11.h: Add XGate definitions.
754 (struct m68hc11_opcode): Add xg_mask field.
755
b9c361e0
JL		 7562012-05-14 Catherine Moore <clm@codesourcery.com>
757 Maciej W. Rozycki <macro@codesourcery.com>
758 Rhonda Wittels <rhonda@codesourcery.com>
759
6927f982 760 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 761 (PPC_OP_SA): New macro.
762 (PPC_OP_SE_VLE): New macro.
763 (PPC_OP): Use a variable shift amount.
764 (powerpc_operand): Update comments.
765 (PPC_OPSHIFT_INV): New macro.
766 (PPC_OPERAND_CR): Replace with...
767 (PPC_OPERAND_CR_BIT): ...this and
768 (PPC_OPERAND_CR_REG): ...this.
769
770
f6c1a2d5
NC		 7712012-05-03 Sean Keys <skeys@ipdatasys.com>
772
773 * xgate.h: Header file for XGATE assembler.
774
ec668d69
DM		 7752012-04-27 David S. Miller <davem@davemloft.net>
776
6cda1326
DM		 777 * sparc.h: Document new arg code' )' for crypto RS3
778 immediates.
779
ec668d69
DM		 780 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
781 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
782 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
783 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
784 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
785 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
786 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
787 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
788 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
789 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
790 HWCAP_CBCOND, HWCAP_CRC32): New defines.
791
aea77599
AM		 7922012-03-10 Edmar Wienskoski <edmar@freescale.com>
793
794 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
795
1f42f8b3
AM		 7962012-02-27 Alan Modra <amodra@gmail.com>
797
798 * crx.h (cst4_map): Update declaration.
799
6f7be959
WL		 8002012-02-25 Walter Lee <walt@tilera.com>
801
802 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
803 TILEGX_OPC_LD_TLS.
804 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
805 TILEPRO_OPC_LW_TLS_SN.
806
42164a71
L		 8072012-02-08 H.J. Lu <hongjiu.lu@intel.com>
808
809 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
810 (XRELEASE_PREFIX_OPCODE): Likewise.
811
432233b3 8122011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 813 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 814
815 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
816 (INSN_OCTEON2): New macro.
817 (CPU_OCTEON2): New macro.
818 (OPCODE_IS_MEMBER): Add Octeon2.
819
dd6a37e7
AP		 8202011-11-29 Andrew Pinski <apinski@cavium.com>
821
822 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
823 (INSN_OCTEONP): New macro.
824 (CPU_OCTEONP): New macro.
825 (OPCODE_IS_MEMBER): Add Octeon+.
826 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
827
99c513f6
DD		 8282011-11-01 DJ Delorie <dj@redhat.com>
829
830 * rl78.h: New file.
831
26f85d7a
MR		 8322011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
833
834 * mips.h: Fix a typo in description.
835
9e8c70f9
DM		 8362011-09-21 David S. Miller <davem@davemloft.net>
837
838 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
839 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
840 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
841 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
842
dec0624d 8432011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 844 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 845
846 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
847 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
848 (INSN_ASE_MASK): Add the MCU bit.
849 (INSN_MCU): New macro.
850 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
851 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
852
2b0c8b40
MR		 8532011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
854
855 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
856 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
857 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
858 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
859 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
860 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
861 (INSN2_READ_GPR_MMN): Likewise.
862 (INSN2_READ_FPR_D): Change the bit used.
863 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
864 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
865 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
866 (INSN2_COND_BRANCH): Likewise.
867 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
868 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
869 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
870 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
871 (INSN2_MOD_GPR_MN): Likewise.
872
ea783ef3
DM		 8732011-08-05 David S. Miller <davem@davemloft.net>
874
875 * sparc.h: Document new format codes '4', '5', and '('.
876 (OPF_LOW4, RS3): New macros.
877
7c176fa8
MR		 8782011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
879
880 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
881 order of flags documented.
882
2309ddf2
MR		 8832011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
884
885 * mips.h: Clarify the description of microMIPS instruction
886 manipulation macros.
887 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
888
df58fc94 8892011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 890 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 891
892 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
893 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
894 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
895 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
896 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
897 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
898 (OP_MASK_RS3, OP_SH_RS3): Likewise.
899 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
900 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
901 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
902 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
903 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
904 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
905 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
906 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
907 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
908 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
909 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
910 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
911 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
912 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
913 (INSN_WRITE_GPR_S): New macro.
914 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
915 (INSN2_READ_FPR_D): Likewise.
916 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
917 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
918 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
919 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
920 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
921 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
922 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
923 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
924 (CPU_MICROMIPS): New macro.
925 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
926 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
927 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
928 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
929 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
930 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
931 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
932 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
933 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
934 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
935 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
936 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
937 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
938 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
939 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
940 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
941 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
942 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
943 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
944 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
945 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
946 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
947 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
948 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
949 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
950 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
951 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
952 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
953 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
954 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
955 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
956 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
957 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
958 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
959 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
960 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
961 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
962 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
963 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
964 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
965 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
966 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
967 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
968 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
969 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
970 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
971 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
972 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
973 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
974 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
975 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
976 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
977 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
978 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
979 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
980 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
981 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
982 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
983 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
984 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
985 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
986 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
987 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
988 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
989 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
990 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
991 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
992 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
993 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
994 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
995 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
996 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
997 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
998 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
999 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1000 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1001 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1002 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1003 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1004 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1005 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1006 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1007 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1008 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1009 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1010 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1011 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1012 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1013 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1014 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1015 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1016 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1017 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1018 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1019 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1020 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1021 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1022 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1023 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1024 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1025 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1026 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1027 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1028 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1029 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1030 (micromips_opcodes): New declaration.
1031 (bfd_micromips_num_opcodes): Likewise.
1032
bcd530a7
RS		 10332011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1034
1035 * mips.h (INSN_TRAP): Rename to...
1036 (INSN_NO_DELAY_SLOT): ... this.
1037 (INSN_SYNC): Remove macro.
1038
2dad5a91
EW		 10392011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1040
1041 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1042 a duplicate of AVR_ISA_SPM.
1043
5d73b1f1
NC		 10442011-07-01 Nick Clifton <nickc@redhat.com>
1045
1046 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1047
ef26d60e
MF		 10482011-06-18 Robin Getz <robin.getz@analog.com>
1049
1050 * bfin.h (is_macmod_signed): New func
1051
8fb8dca7
MF		 10522011-06-18 Mike Frysinger <vapier@gentoo.org>
1053
1054 * bfin.h (is_macmod_pmove): Add missing space before func args.
1055 (is_macmod_hmove): Likewise.
1056
aa137e4d
NC		 10572011-06-13 Walter Lee <walt@tilera.com>
1058
1059 * tilegx.h: New file.
1060 * tilepro.h: New file.
1061
3b2f0793
PB		 10622011-05-31 Paul Brook <paul@codesourcery.com>
1063
aa137e4d
NC		 1064 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1065
10662011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1067
1068 * s390.h: Replace S390_OPERAND_REG_EVEN with
1069 S390_OPERAND_REG_PAIR.
1070
10712011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1072
1073 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1074
ac7f631b
NC		 10752011-04-18 Julian Brown <julian@codesourcery.com>
1076
1077 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1078
84701018
NC		 10792011-04-11 Dan McDonald <dan@wellkeeper.com>
1080
1081 PR gas/12296
1082 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1083
8cc66334
EW		 10842011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1085
1086 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1087 New instruction set flags.
1088 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1089
3eebd5eb
MR		 10902011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1091
1092 * mips.h (M_PREF_AB): New enum value.
1093
26bb3ddd
MF		 10942011-02-12 Mike Frysinger <vapier@gentoo.org>
1095
89c0d58c
MR		 1096 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1097 M_IU): Define.
1098 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1099
dd76fcb8
MF		 11002011-02-11 Mike Frysinger <vapier@gentoo.org>
1101
1102 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1103
98d23bef
BS		 11042011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1105
1106 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1107 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1108
3c853d93
DA		 11092010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1110
1111 PR gas/11395
1112 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1113 "bb" entries.
1114
79676006
DA		 11152010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1116
1117 PR gas/11395
1118 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1119
1bec78e9
RS		 11202010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1121
1122 * mips.h: Update commentary after last commit.
1123
98675402
RS		 11242010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1125
1126 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1127 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1128 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1129
aa137e4d
NC		 11302010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1131
1132 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1133
435b94a4
RS		 11342010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1135
1136 * mips.h: Fix previous commit.
1137
d051516a
NC		 11382010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1139
1140 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1141 (INSN_LOONGSON_3A): Clear bit 31.
1142
251665fc
MGD		 11432010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1144
1145 PR gas/12198
1146 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1147 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1148 (ARM_ARCH_V6M_ONLY): New define.
1149
fd503541
NC		 11502010-11-11 Mingming Sun <mingm.sun@gmail.com>
1151
1152 * mips.h (INSN_LOONGSON_3A): Defined.
1153 (CPU_LOONGSON_3A): Defined.
1154 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1155
4469d2be
AM		 11562010-10-09 Matt Rice <ratmice@gmail.com>
1157
1158 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1159 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1160
90ec0d68
MGD		 11612010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1162
1163 * arm.h (ARM_EXT_VIRT): New define.
1164 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1165 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1166 Extensions.
1167
eea54501 11682010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1169
eea54501
MGD		 1170 * arm.h (ARM_AEXT_ADIV): New define.
1171 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1172
b2a5fbdc
MGD		 11732010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1174
1175 * arm.h (ARM_EXT_OS): New define.
1176 (ARM_AEXT_V6SM): Likewise.
1177 (ARM_ARCH_V6SM): Likewise.
1178
60e5ef9f
MGD		 11792010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1180
1181 * arm.h (ARM_EXT_MP): Add.
1182 (ARM_ARCH_V7A_MP): Likewise.
1183
73a63ccf
MF		 11842010-09-22 Mike Frysinger <vapier@gentoo.org>
1185
1186 * bfin.h: Declare pseudoChr structs/defines.
1187
ee99860a
MF		 11882010-09-21 Mike Frysinger <vapier@gentoo.org>
1189
1190 * bfin.h: Strip trailing whitespace.
1191
f9c7014e
DD		 11922010-07-29 DJ Delorie <dj@redhat.com>
1193
1194 * rx.h (RX_Operand_Type): Add TwoReg.
1195 (RX_Opcode_ID): Remove ediv and ediv2.
1196
93378652
DD		 11972010-07-27 DJ Delorie <dj@redhat.com>
1198
1199 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1200
1cd986c5
NC		 12012010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1202 Ina Pandit <ina.pandit@kpitcummins.com>
1203
1204 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1205 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1206 PROCESSOR_V850E2_ALL.
1207 Remove PROCESSOR_V850EA support.
1208 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1209 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1210 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1211 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1212 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1213 V850_OPERAND_PERCENT.
1214 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1215 V850_NOT_R0.
1216 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1217 and V850E_PUSH_POP
1218
9a2c7088
MR		 12192010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1220
1221 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1222 (MIPS16_INSN_BRANCH): Rename to...
1223 (MIPS16_INSN_COND_BRANCH): ... this.
1224
bdc70b4a
AM		 12252010-07-03 Alan Modra <amodra@gmail.com>
1226
1227 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1228 Renumber other PPC_OPCODE defines.
1229
f2bae120
AM		 12302010-07-03 Alan Modra <amodra@gmail.com>
1231
1232 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1233
360cfc9c
AM		 12342010-06-29 Alan Modra <amodra@gmail.com>
1235
1236 * maxq.h: Delete file.
1237
e01d869a
AM		 12382010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1239
1240 * ppc.h (PPC_OPCODE_E500): Define.
1241
f79e2745
CM		 12422010-05-26 Catherine Moore <clm@codesourcery.com>
1243
1244 * opcode/mips.h (INSN_MIPS16): Remove.
1245
2462afa1
JM		 12462010-04-21 Joseph Myers <joseph@codesourcery.com>
1247
1248 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1249
e4e42b45
NC		 12502010-04-15 Nick Clifton <nickc@redhat.com>
1251
1252 * alpha.h: Update copyright notice to use GPLv3.
1253 * arc.h: Likewise.
1254 * arm.h: Likewise.
1255 * avr.h: Likewise.
1256 * bfin.h: Likewise.
1257 * cgen.h: Likewise.
1258 * convex.h: Likewise.
1259 * cr16.h: Likewise.
1260 * cris.h: Likewise.
1261 * crx.h: Likewise.
1262 * d10v.h: Likewise.
1263 * d30v.h: Likewise.
1264 * dlx.h: Likewise.
1265 * h8300.h: Likewise.
1266 * hppa.h: Likewise.
1267 * i370.h: Likewise.
1268 * i386.h: Likewise.
1269 * i860.h: Likewise.
1270 * i960.h: Likewise.
1271 * ia64.h: Likewise.
1272 * m68hc11.h: Likewise.
1273 * m68k.h: Likewise.
1274 * m88k.h: Likewise.
1275 * maxq.h: Likewise.
1276 * mips.h: Likewise.
1277 * mmix.h: Likewise.
1278 * mn10200.h: Likewise.
1279 * mn10300.h: Likewise.
1280 * msp430.h: Likewise.
1281 * np1.h: Likewise.
1282 * ns32k.h: Likewise.
1283 * or32.h: Likewise.
1284 * pdp11.h: Likewise.
1285 * pj.h: Likewise.
1286 * pn.h: Likewise.
1287 * ppc.h: Likewise.
1288 * pyr.h: Likewise.
1289 * rx.h: Likewise.
1290 * s390.h: Likewise.
1291 * score-datadep.h: Likewise.
1292 * score-inst.h: Likewise.
1293 * sparc.h: Likewise.
1294 * spu-insns.h: Likewise.
1295 * spu.h: Likewise.
1296 * tic30.h: Likewise.
1297 * tic4x.h: Likewise.
1298 * tic54x.h: Likewise.
1299 * tic80.h: Likewise.
1300 * v850.h: Likewise.
1301 * vax.h: Likewise.
1302
40b36596
JM		 13032010-03-25 Joseph Myers <joseph@codesourcery.com>
1304
1305 * tic6x-control-registers.h, tic6x-insn-formats.h,
1306 tic6x-opcode-table.h, tic6x.h: New.
1307
c67a084a
NC		 13082010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1309
1310 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1311
466ef64f
AM		 13122010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1313
1314 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1315
1319d143
L		 13162010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1317
1318 * ia64.h (ia64_find_opcode): Remove argument name.
1319 (ia64_find_next_opcode): Likewise.
1320 (ia64_dis_opcode): Likewise.
1321 (ia64_free_opcode): Likewise.
1322 (ia64_find_dependency): Likewise.
1323
1fbb9298
DE		 13242009-11-22 Doug Evans <dje@sebabeach.org>
1325
1326 * cgen.h: Include bfd_stdint.h.
1327 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1328
ada65aa3
PB		 13292009-11-18 Paul Brook <paul@codesourcery.com>
1330
1331 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1332
9e3c6df6
PB		 13332009-11-17 Paul Brook <paul@codesourcery.com>
1334 Daniel Jacobowitz <dan@codesourcery.com>
1335
1336 * arm.h (ARM_EXT_V6_DSP): Define.
1337 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1338 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1339
0d734b5d
DD		 13402009-11-04 DJ Delorie <dj@redhat.com>
1341
1342 * rx.h (rx_decode_opcode) (mvtipl): Add.
1343 (mvtcp, mvfcp, opecp): Remove.
1344
62f3b8c8
PB		 13452009-11-02 Paul Brook <paul@codesourcery.com>
1346
1347 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1348 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1349 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1350 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1351 FPU_ARCH_NEON_VFP_V4): Define.
1352
ac1e9eca
DE		 13532009-10-23 Doug Evans <dje@sebabeach.org>
1354
1355 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1356 * cgen.h: Update. Improve multi-inclusion macro name.
1357
9fe54b1c
PB		 13582009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1359
1360 * ppc.h (PPC_OPCODE_476): Define.
1361
634b50f2
PB		 13622009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1363
1364 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1365
c7927a3c
NC		 13662009-09-29 DJ Delorie <dj@redhat.com>
1367
1368 * rx.h: New file.
1369
b961e85b
AM		 13702009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1371
1372 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1373
e0d602ec
BE		 13742009-09-21 Ben Elliston <bje@au.ibm.com>
1375
1376 * ppc.h (PPC_OPCODE_PPCA2): New.
1377
96d56e9f
NC		 13782009-09-05 Martin Thuresson <martin@mtme.org>
1379
1380 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1381
d3ce72d0
NC		 13822009-08-29 Martin Thuresson <martin@mtme.org>
1383
1384 * tic30.h (template): Rename type template to
1385 insn_template. Updated code to use new name.
1386 * tic54x.h (template): Rename type template to
1387 insn_template.
1388
824b28db
NH		 13892009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1390
1391 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1392
f865a31d
AG		 13932009-06-11 Anthony Green <green@moxielogic.com>
1394
1395 * moxie.h (MOXIE_F3_PCREL): Define.
1396 (moxie_form3_opc_info): Grow.
1397
0e7c7f11
AG		 13982009-06-06 Anthony Green <green@moxielogic.com>
1399
1400 * moxie.h (MOXIE_F1_M): Define.
1401
20135e4c
NC		 14022009-04-15 Anthony Green <green@moxielogic.com>
1403
1404 * moxie.h: Created.
1405
bcb012d3
DD		 14062009-04-06 DJ Delorie <dj@redhat.com>
1407
1408 * h8300.h: Add relaxation attributes to MOVA opcodes.
1409
69fe9ce5
AM		 14102009-03-10 Alan Modra <amodra@bigpond.net.au>
1411
1412 * ppc.h (ppc_parse_cpu): Declare.
1413
c3b7224a
NC		 14142009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1415
1416 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1417 and _IMM11 for mbitclr and mbitset.
1418 * score-datadep.h: Update dependency information.
1419
066be9f7
PB		 14202009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1421
1422 * ppc.h (PPC_OPCODE_POWER7): New.
1423
fedc618e
DE		 14242009-02-06 Doug Evans <dje@google.com>
1425
1426 * i386.h: Add comment regarding sse* insns and prefixes.
1427
52b6b6b9
JM		 14282009-02-03 Sandip Matte <sandip@rmicorp.com>
1429
1430 * mips.h (INSN_XLR): Define.
1431 (INSN_CHIP_MASK): Update.
1432 (CPU_XLR): Define.
1433 (OPCODE_IS_MEMBER): Update.
1434 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1435
35669430
DE		 14362009-01-28 Doug Evans <dje@google.com>
1437
1438 * opcode/i386.h: Add multiple inclusion protection.
1439 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1440 (EDI_REG_NUM): New macros.
1441 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1442 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1443 (REX_PREFIX_P): New macro.
35669430 1444
1cb0a767
PB		 14452009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1446
1447 * ppc.h (struct powerpc_opcode): New field "deprecated".
1448 (PPC_OPCODE_NOPOWER4): Delete.
1449
3aa3176b
TS		 14502008-11-28 Joshua Kinard <kumba@gentoo.org>
1451
1452 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1453 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1454
8e79c3df
CM		 14552008-11-18 Catherine Moore <clm@codesourcery.com>
1456
1457 * arm.h (FPU_NEON_FP16): New.
1458 (FPU_ARCH_NEON_FP16): New.
1459
de9a3e51
CF		 14602008-11-06 Chao-ying Fu <fu@mips.com>
1461
1462 * mips.h: Doucument '1' for 5-bit sync type.
1463
1ca35711
L		 14642008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1465
1466 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1467 IA64_RS_CR.
1468
9b4e5766
PB		 14692008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1470
1471 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1472
081ba1b3
AM		 14732008-07-30 Michael J. Eager <eager@eagercon.com>
1474
1475 * ppc.h (PPC_OPCODE_405): Define.
1476 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1477
fa452fa6
PB		 14782008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1479
1480 * ppc.h (ppc_cpu_t): New typedef.
1481 (struct powerpc_opcode <flags>): Use it.
1482 (struct powerpc_operand <insert, extract>): Likewise.
1483 (struct powerpc_macro <flags>): Likewise.
1484
bb35fb24
NC		 14852008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1486
1487 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1488 Update comment before MIPS16 field descriptors to mention MIPS16.
1489 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1490 BBIT.
1491 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1492 New bit masks and shift counts for cins and exts.
1493
dd3cbb7e
NC		 1494 * mips.h: Document new field descriptors +Q.
1495 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1496
d0799671
AN		 14972008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1498
9aff4b7a 1499 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1500 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1501
19a6653c
AM		 15022008-04-14 Edmar Wienskoski <edmar@freescale.com>
1503
1504 * ppc.h: (PPC_OPCODE_E500MC): New.
1505
c0f3af97
L		 15062008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1507
1508 * i386.h (MAX_OPERANDS): Set to 5.
1509 (MAX_MNEM_SIZE): Changed to 20.
1510
e210c36b
NC		 15112008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1512
1513 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1514
b1cc4aeb
PB		 15152008-03-09 Paul Brook <paul@codesourcery.com>
1516
1517 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1518
7e806470
PB		 15192008-03-04 Paul Brook <paul@codesourcery.com>
1520
1521 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1522 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1523 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1524
7b2185f9 15252008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1526 Nick Clifton <nickc@redhat.com>
1527
1528 PR 3134
1529 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1530 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1531 set.
af7329f0 1532
796d5313
NC		 15332008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1534
1535 * cr16.h (cr16_num_optab): Declared.
1536
d669d37f
NC		 15372008-02-14 Hakan Ardo <hakan@debian.org>
1538
1539 PR gas/2626
1540 * avr.h (AVR_ISA_2xxe): Define.
1541
e6429699
AN		 15422008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1543
1544 * mips.h: Update copyright.
1545 (INSN_CHIP_MASK): New macro.
1546 (INSN_OCTEON): New macro.
1547 (CPU_OCTEON): New macro.
1548 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1549
e210c36b
NC		 15502008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1551
1552 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1553
15542008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1555
1556 * avr.h (AVR_ISA_USB162): Add new opcode set.
1557 (AVR_ISA_AVR3): Likewise.
1558
350cc38d
MS		 15592007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1560
1561 * mips.h (INSN_LOONGSON_2E): New.
1562 (INSN_LOONGSON_2F): New.
1563 (CPU_LOONGSON_2E): New.
1564 (CPU_LOONGSON_2F): New.
1565 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1566
56950294
MS		 15672007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1568
1569 * mips.h (INSN_ISA*): Redefine certain values as an
1570 enumeration. Update comments.
1571 (mips_isa_table): New.
1572 (ISA_MIPS*): Redefine to match enumeration.
1573 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1574 values.
1575
c3d65c1c
BE		 15762007-08-08 Ben Elliston <bje@au.ibm.com>
1577
1578 * ppc.h (PPC_OPCODE_PPCPS): New.
1579
0fdaa005
L		 15802007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1581
1582 * m68k.h: Document j K & E.
1583
15842007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1585
1586 * cr16.h: New file for CR16 target.
1587
3896c469
AM		 15882007-05-02 Alan Modra <amodra@bigpond.net.au>
1589
1590 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1591
9a2e615a
NS		 15922007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1593
1594 * m68k.h (mcfisa_c): New.
1595 (mcfusp, mcf_mask): Adjust.
1596
b84bf58a
AM		 15972007-04-20 Alan Modra <amodra@bigpond.net.au>
1598
1599 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1600 (num_powerpc_operands): Declare.
1601 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1602 (PPC_OPERAND_PLUS1): Define.
1603
831480e9 16042007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1605
1606 * i386.h (REX_MODE64): Renamed to ...
1607 (REX_W): This.
1608 (REX_EXTX): Renamed to ...
1609 (REX_R): This.
1610 (REX_EXTY): Renamed to ...
1611 (REX_X): This.
1612 (REX_EXTZ): Renamed to ...
1613 (REX_B): This.
1614
0b1cf022
L		 16152007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1616
1617 * i386.h: Add entries from config/tc-i386.h and move tables
1618 to opcodes/i386-opc.h.
1619
d796c0ad
L		 16202007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1621
1622 * i386.h (FloatDR): Removed.
1623 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1624
30ac7323
AM		 16252007-03-01 Alan Modra <amodra@bigpond.net.au>
1626
1627 * spu-insns.h: Add soma double-float insns.
1628
8b082fb1 16292007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1630 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1631
1632 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1633 (INSN_DSPR2): Add flag for DSP R2 instructions.
1634 (M_BALIGN): New macro.
1635
4eed87de
AM		 16362007-02-14 Alan Modra <amodra@bigpond.net.au>
1637
1638 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1639 and Seg3ShortFrom with Shortform.
1640
fda592e8
L		 16412007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1642
1643 PR gas/4027
1644 * i386.h (i386_optab): Put the real "test" before the pseudo
1645 one.
1646
3bdcfdf4
KH		 16472007-01-08 Kazu Hirata <kazu@codesourcery.com>
1648
1649 * m68k.h (m68010up): OR fido_a.
1650
9840d27e
KH		 16512006-12-25 Kazu Hirata <kazu@codesourcery.com>
1652
1653 * m68k.h (fido_a): New.
1654
c629cdac
KH		 16552006-12-24 Kazu Hirata <kazu@codesourcery.com>
1656
1657 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1658 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1659 values.
1660
b7d9ef37
L		 16612006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1662
1663 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1664
b138abaa
NC		 16652006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1666
1667 * score-inst.h (enum score_insn_type): Add Insn_internal.
1668
e9f53129
AM		 16692006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1670 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1671 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1672 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1673 Alan Modra <amodra@bigpond.net.au>
1674
1675 * spu-insns.h: New file.
1676 * spu.h: New file.
1677
ede602d7
AM		 16782006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1679
1680 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1681
7918206c
MM		 16822006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1683
e4e42b45 1684 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1685 in amdfam10 architecture.
1686
ef05d495
L		 16872006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1688
1689 * i386.h: Replace CpuMNI with CpuSSSE3.
1690
2d447fca 16912006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1692 Joseph Myers <joseph@codesourcery.com>
1693 Ian Lance Taylor <ian@wasabisystems.com>
1694 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1695
1696 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1697
1c0d3aa6
NC		 16982006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1699
1700 * score-datadep.h: New file.
1701 * score-inst.h: New file.
1702
c2f0420e
L		 17032006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1704
1705 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1706 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1707 movdq2q and movq2dq.
1708
050dfa73
MM		 17092006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1710 Michael Meissner <michael.meissner@amd.com>
1711
1712 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1713
15965411
L		 17142006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1715
1716 * i386.h (i386_optab): Add "nop" with memory reference.
1717
46e883c5
L		 17182006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1719
1720 * i386.h (i386_optab): Update comment for 64bit NOP.
1721
9622b051
AM		 17222006-06-06 Ben Elliston <bje@au.ibm.com>
1723 Anton Blanchard <anton@samba.org>
1724
1725 * ppc.h (PPC_OPCODE_POWER6): Define.
1726 Adjust whitespace.
1727
a9e24354
TS		 17282006-06-05 Thiemo Seufer <ths@mips.com>
1729
e4e42b45 1730 * mips.h: Improve description of MT flags.
a9e24354 1731
a596001e
RS		 17322006-05-25 Richard Sandiford <richard@codesourcery.com>
1733
1734 * m68k.h (mcf_mask): Define.
1735
d43b4baf 17362006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1737 David Ung <davidu@mips.com>
d43b4baf
TS		 1738
1739 * mips.h (enum): Add macro M_CACHE_AB.
1740
39a7806d 17412006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1742 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1743 David Ung <davidu@mips.com>
1744
1745 * mips.h: Add INSN_SMARTMIPS define.
1746
9bcd4f99 17472006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1748 David Ung <davidu@mips.com>
9bcd4f99
TS		 1749
1750 * mips.h: Defines udi bits and masks. Add description of
1751 characters which may appear in the args field of udi
1752 instructions.
1753
ef0ee844
TS		 17542006-04-26 Thiemo Seufer <ths@networkno.de>
1755
1756 * mips.h: Improve comments describing the bitfield instruction
1757 fields.
1758
f7675147
L		 17592006-04-26 Julian Brown <julian@codesourcery.com>
1760
1761 * arm.h (FPU_VFP_EXT_V3): Define constant.
1762 (FPU_NEON_EXT_V1): Likewise.
1763 (FPU_VFP_HARD): Update.
1764 (FPU_VFP_V3): Define macro.
1765 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1766
ef0ee844 17672006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1768
1769 * avr.h (AVR_ISA_PWMx): New.
1770
2da12c60
NS		 17712006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1772
1773 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1774 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1775 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1776 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1777 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1778
0715c387
PB		 17792006-03-10 Paul Brook <paul@codesourcery.com>
1780
1781 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1782
34bdd094
DA		 17832006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1784
1785 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1786 first. Correct mask of bb "B" opcode.
1787
331d2d0d
L		 17882006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1789
1790 * i386.h (i386_optab): Support Intel Merom New Instructions.
1791
62b3e311
PB		 17922006-02-24 Paul Brook <paul@codesourcery.com>
1793
1794 * arm.h: Add V7 feature bits.
1795
59cf82fe
L		 17962006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1797
1798 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1799
e74cfd16
PB		 18002006-01-31 Paul Brook <paul@codesourcery.com>
1801 Richard Earnshaw <rearnsha@arm.com>
1802
1803 * arm.h: Use ARM_CPU_FEATURE.
1804 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1805 (arm_feature_set): Change to a structure.
1806 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1807 ARM_FEATURE): New macros.
1808
5b3f8a92
HPN		 18092005-12-07 Hans-Peter Nilsson <hp@axis.com>
1810
1811 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1812 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1813 (ADD_PC_INCR_OPCODE): Don't define.
1814
cb712a9e
L		 18152005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1816
1817 PR gas/1874
1818 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1819
0499d65b
TS		 18202005-11-14 David Ung <davidu@mips.com>
1821
1822 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1823 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1824 save/restore encoding of the args field.
1825
ea5ca089
DB		 18262005-10-28 Dave Brolley <brolley@redhat.com>
1827
1828 Contribute the following changes:
1829 2005-02-16 Dave Brolley <brolley@redhat.com>
1830
1831 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1832 cgen_isa_mask_* to cgen_bitset_*.
1833 * cgen.h: Likewise.
1834
16175d96
DB		 1835 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1836
1837 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1838 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1839 (CGEN_CPU_TABLE): Make isas a ponter.
1840
1841 2003-09-29 Dave Brolley <brolley@redhat.com>
1842
1843 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1844 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1845 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1846
1847 2002-12-13 Dave Brolley <brolley@redhat.com>
1848
1849 * cgen.h (symcat.h): #include it.
1850 (cgen-bitset.h): #include it.
1851 (CGEN_ATTR_VALUE_TYPE): Now a union.
1852 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1853 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1854 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1855 * cgen-bitset.h: New file.
1856
3c9b82ba
NC		 18572005-09-30 Catherine Moore <clm@cm00re.com>
1858
1859 * bfin.h: New file.
1860
6a2375c6
JB		 18612005-10-24 Jan Beulich <jbeulich@novell.com>
1862
1863 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1864 indirect operands.
1865
c06a12f8
DA		 18662005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1867
1868 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1869 Add FLAG_STRICT to pa10 ftest opcode.
1870
4d443107
DA		 18712005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1872
1873 * hppa.h (pa_opcodes): Remove lha entries.
1874
f0a3b40f
DA		 18752005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1876
1877 * hppa.h (FLAG_STRICT): Revise comment.
1878 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1879 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1880 entries for "fdc".
1881
e210c36b
NC		 18822005-09-30 Catherine Moore <clm@cm00re.com>
1883
1884 * bfin.h: New file.
1885
1b7e1362
DA		 18862005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1887
1888 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1889
089b39de
CF		 18902005-09-06 Chao-ying Fu <fu@mips.com>
1891
1892 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1893 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1894 define.
1895 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1896 (INSN_ASE_MASK): Update to include INSN_MT.
1897 (INSN_MT): New define for MT ASE.
1898
93c34b9b
CF		 18992005-08-25 Chao-ying Fu <fu@mips.com>
1900
1901 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1902 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1903 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1904 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1905 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1906 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1907 instructions.
1908 (INSN_DSP): New define for DSP ASE.
1909
848cf006
AM		 19102005-08-18 Alan Modra <amodra@bigpond.net.au>
1911
1912 * a29k.h: Delete.
1913
36ae0db3
DJ		 19142005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1915
1916 * ppc.h (PPC_OPCODE_E300): Define.
1917
8c929562
MS		 19182005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1919
1920 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1921
f7b8cccc
DA		 19222005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1923
1924 PR gas/336
1925 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1926 and pitlb.
1927
8b5328ac
JB		 19282005-07-27 Jan Beulich <jbeulich@novell.com>
1929
1930 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1931 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1932 Add movq-s as 64-bit variants of movd-s.
1933
f417d200
DA		 19342005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1935
18b3bdfc
DA		 1936 * hppa.h: Fix punctuation in comment.
1937
f417d200
DA		 1938 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1939 implicit space-register addressing. Set space-register bits on opcodes
1940 using implicit space-register addressing. Add various missing pa20
1941 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1942 space-register addressing. Use "fE" instead of "fe" in various
1943 fstw opcodes.
1944
9a145ce6
JB		 19452005-07-18 Jan Beulich <jbeulich@novell.com>
1946
1947 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1948
90700ea2
L		 19492007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1950
1951 * i386.h (i386_optab): Support Intel VMX Instructions.
1952
48f130a8
DA		 19532005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1954
1955 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1956
30123838
JB		 19572005-07-05 Jan Beulich <jbeulich@novell.com>
1958
1959 * i386.h (i386_optab): Add new insns.
1960
47b0e7ad
NC		 19612005-07-01 Nick Clifton <nickc@redhat.com>
1962
1963 * sparc.h: Add typedefs to structure declarations.
1964
b300c311
L		 19652005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1966
1967 PR 1013
1968 * i386.h (i386_optab): Update comments for 64bit addressing on
1969 mov. Allow 64bit addressing for mov and movq.
1970
2db495be
DA		 19712005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1972
1973 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1974 respectively, in various floating-point load and store patterns.
1975
caa05036
DA		 19762005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1977
1978 * hppa.h (FLAG_STRICT): Correct comment.
1979 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1980 PA 2.0 mneumonics when equivalent. Entries with cache control
1981 completers now require PA 1.1. Adjust whitespace.
1982
f4411256
AM		 19832005-05-19 Anton Blanchard <anton@samba.org>
1984
1985 * ppc.h (PPC_OPCODE_POWER5): Define.
1986
e172dbf8
NC		 19872005-05-10 Nick Clifton <nickc@redhat.com>
1988
1989 * Update the address and phone number of the FSF organization in
1990 the GPL notices in the following files:
1991 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1992 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1993 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1994 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1995 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1996 tic54x.h, tic80.h, v850.h, vax.h
1997
e44823cf
JB		 19982005-05-09 Jan Beulich <jbeulich@novell.com>
1999
2000 * i386.h (i386_optab): Add ht and hnt.
2001
791fe849
MK		 20022005-04-18 Mark Kettenis <kettenis@gnu.org>
2003
2004 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2005 Add xcrypt-ctr. Provide aliases without hyphens.
2006
faa7ef87
L		 20072005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2008
a63027e5
L		 2009 Moved from ../ChangeLog
2010
faa7ef87
L		 2011 2005-04-12 Paul Brook <paul@codesourcery.com>
2012 * m88k.h: Rename psr macros to avoid conflicts.
2013
2014 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2015 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2016 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2017 and ARM_ARCH_V6ZKT2.
2018
2019 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2020 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2021 Remove redundant instruction types.
2022 (struct argument): X_op - new field.
2023 (struct cst4_entry): Remove.
2024 (no_op_insn): Declare.
2025
2026 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2027 * crx.h (enum argtype): Rename types, remove unused types.
2028
2029 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2030 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2031 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2032 (enum operand_type): Rearrange operands, edit comments.
2033 replace us<N> with ui<N> for unsigned immediate.
2034 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2035 displacements (respectively).
2036 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2037 (instruction type): Add NO_TYPE_INS.
2038 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2039 (operand_entry): New field - 'flags'.
2040 (operand flags): New.
2041
2042 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2043 * crx.h (operand_type): Remove redundant types i3, i4,
2044 i5, i8, i12.
2045 Add new unsigned immediate types us3, us4, us5, us16.
2046
bc4bd9ab
MK		 20472005-04-12 Mark Kettenis <kettenis@gnu.org>
2048
2049 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2050 adjust them accordingly.
2051
373ff435
JB		 20522005-04-01 Jan Beulich <jbeulich@novell.com>
2053
2054 * i386.h (i386_optab): Add rdtscp.
2055
4cc91dba
L		 20562005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2057
2058 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 2059 between memory and segment register. Allow movq for moving between
2060 general-purpose register and segment register.
4cc91dba 2061
9ae09ff9
JB		 20622005-02-09 Jan Beulich <jbeulich@novell.com>
2063
2064 PR gas/707
2065 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2066 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2067 fnstsw.
2068
638e7a64
NS		 20692006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2070
2071 * m68k.h (m68008, m68ec030, m68882): Remove.
2072 (m68k_mask): New.
2073 (cpu_m68k, cpu_cf): New.
2074 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2075 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2076
90219bd0
AO		 20772005-01-25 Alexandre Oliva <aoliva@redhat.com>
2078
2079 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2080 * cgen.h (enum cgen_parse_operand_type): Add
2081 CGEN_PARSE_OPERAND_SYMBOLIC.
2082
239cb185
FF		 20832005-01-21 Fred Fish <fnf@specifixinc.com>
2084
2085 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2086 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2087 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2088
dc9a9f39
FF		 20892005-01-19 Fred Fish <fnf@specifixinc.com>
2090
2091 * mips.h (struct mips_opcode): Add new pinfo2 member.
2092 (INSN_ALIAS): New define for opcode table entries that are
2093 specific instances of another entry, such as 'move' for an 'or'
2094 with a zero operand.
2095 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2096 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2097
98e7aba8
ILT		 20982004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2099
2100 * mips.h (CPU_RM9000): Define.
2101 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2102
37edbb65
JB		 21032004-11-25 Jan Beulich <jbeulich@novell.com>
2104
2105 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2106 to/from test registers are illegal in 64-bit mode. Add missing
2107 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2108 (previously one had to explicitly encode a rex64 prefix). Re-enable
2109 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2110 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2111
21122004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2113
2114 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2115 available only with SSE2. Change the MMX additions introduced by SSE
2116 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2117 instructions by their now designated identifier (since combining i686
2118 and 3DNow! does not really imply 3DNow!A).
2119
f5c7edf4
AM		 21202004-11-19 Alan Modra <amodra@bigpond.net.au>
2121
2122 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2123 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2124
7499d566
NC		 21252004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2126 Vineet Sharma <vineets@noida.hcltech.com>
2127
2128 * maxq.h: New file: Disassembly information for the maxq port.
2129
bcb9eebe
L		 21302004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2131
2132 * i386.h (i386_optab): Put back "movzb".
2133
94bb3d38
HPN		 21342004-11-04 Hans-Peter Nilsson <hp@axis.com>
2135
2136 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2137 comments. Remove member cris_ver_sim. Add members
2138 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2139 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2140 (struct cris_support_reg, struct cris_cond15): New types.
2141 (cris_conds15): Declare.
2142 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2143 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2144 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2145 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2146 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2147 SIZE_FIELD_UNSIGNED.
2148
37edbb65 21492004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2150
2151 * i386.h (sldx_Suf): Remove.
2152 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2153 (q_FP): Define, implying no REX64.
2154 (x_FP, sl_FP): Imply FloatMF.
2155 (i386_optab): Split reg and mem forms of moving from segment registers
2156 so that the memory forms can ignore the 16-/32-bit operand size
2157 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2158 all non-floating-point instructions. Unite 32- and 64-bit forms of
2159 movsx, movzx, and movd. Adjust floating point operations for the above
2160 changes to the *FP macros. Add DefaultSize to floating point control
2161 insns operating on larger memory ranges. Remove left over comments
2162 hinting at certain insns being Intel-syntax ones where the ones
2163 actually meant are already gone.
2164
48c9f030
NC		 21652004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2166
2167 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2168 instruction type.
2169
0dd132b6
NC		 21702004-09-30 Paul Brook <paul@codesourcery.com>
2171
2172 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2173 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2174
23794b24
MM		 21752004-09-11 Theodore A. Roth <troth@openavr.org>
2176
2177 * avr.h: Add support for
2178 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2179
2a309db0
AM		 21802004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2181
2182 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2183
b18c562e
NC		 21842004-08-24 Dmitry Diky <diwil@spec.ru>
2185
2186 * msp430.h (msp430_opc): Add new instructions.
2187 (msp430_rcodes): Declare new instructions.
2188 (msp430_hcodes): Likewise..
2189
45d313cd
NC		 21902004-08-13 Nick Clifton <nickc@redhat.com>
2191
2192 PR/301
2193 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2194 processors.
2195
30d1c836
ML		 21962004-08-30 Michal Ludvig <mludvig@suse.cz>
2197
2198 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2199
9a45f1c2
L		 22002004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2201
2202 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2203
543613e9
NC		 22042004-07-21 Jan Beulich <jbeulich@novell.com>
2205
2206 * i386.h: Adjust instruction descriptions to better match the
2207 specification.
2208
b781e558
RE		 22092004-07-16 Richard Earnshaw <rearnsha@arm.com>
2210
2211 * arm.h: Remove all old content. Replace with architecture defines
2212 from gas/config/tc-arm.c.
2213
8577e690
AS		 22142004-07-09 Andreas Schwab <schwab@suse.de>
2215
2216 * m68k.h: Fix comment.
2217
1fe1f39c
NC		 22182004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2219
2220 * crx.h: New file.
2221
1d9f512f
AM		 22222004-06-24 Alan Modra <amodra@bigpond.net.au>
2223
2224 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2225
be8c092b
NC		 22262004-05-24 Peter Barada <peter@the-baradas.com>
2227
2228 * m68k.h: Add 'size' to m68k_opcode.
2229
6b6e92f4
NC		 22302004-05-05 Peter Barada <peter@the-baradas.com>
2231
2232 * m68k.h: Switch from ColdFire chip name to core variant.
2233
22342004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2235
2236 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2237 descriptions for new EMAC cases.
2238 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2239 handle Motorola MAC syntax.
2240 Allow disassembly of ColdFire V4e object files.
2241
fdd12ef3
AM		 22422004-03-16 Alan Modra <amodra@bigpond.net.au>
2243
2244 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2245
3922a64c
L		 22462004-03-12 Jakub Jelinek <jakub@redhat.com>
2247
2248 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2249
1f45d988
ML		 22502004-03-12 Michal Ludvig <mludvig@suse.cz>
2251
2252 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2253
0f10071e
ML		 22542004-03-12 Michal Ludvig <mludvig@suse.cz>
2255
2256 * i386.h (i386_optab): Added xstore/xcrypt insns.
2257
3255318a
NC		 22582004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2259
2260 * h8300.h (32bit ldc/stc): Add relaxing support.
2261
ca9a79a1 22622004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2263
ca9a79a1
NC		 2264 * h8300.h (BITOP): Pass MEMRELAX flag.
2265
875a0b14
NC		 22662004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2267
2268 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2269 except for the H8S.
252b5132 2270
c9e214e5 2271For older changes see ChangeLog-9103
252b5132 2272\f
b90efa5b 2273Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2274
2275Copying and distribution of this file, with or without modification,
2276are permitted in any medium without royalty provided the copyright
2277notice and this notice are preserved.
2278
252b5132 2279Local Variables:
c9e214e5
AM		 2280mode: change-log
2281left-margin: 8
2282fill-column: 74
252b5132
RH		 2283version-control: never
2284End:
GDB Binutils - Deliverables
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