[deliverable/binutils-gdb.git] / include / opcode / ChangeLog

2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* hppa.h (FLAG_STRICT): Correct comment.
	(pa_opcodes): Update load and store entries to allow both PA 1.X and
	PA 2.0 mneumonics when equivalent.  Entries with cache control
	completers now require PA 1.1.  Adjust whitespace.

2005-05-19  Anton Blanchard  <anton@samba.org>

	* ppc.h (PPC_OPCODE_POWER5): Define.

2005-05-10  Nick Clifton  <nickc@redhat.com>

	* Update the address and phone number of the FSF organization in
	the GPL notices in the following files:
	a29k.h,	alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
	crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
	i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
	mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
	pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
	tic54x.h, tic80.h, v850.h, vax.h

2005-05-09  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add ht and hnt.

2005-04-18  Mark Kettenis  <kettenis@gnu.org>

	* i386.h: Insert hyphens into selected VIA PadLock extensions.
	Add xcrypt-ctr.  Provide aliases without hyphens.

2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>

	Moved from ../ChangeLog

	2005-04-12  Paul Brook  <paul@codesourcery.com>
	* m88k.h: Rename psr macros to avoid conflicts.

	2005-03-12  Zack Weinberg  <zack@codesourcery.com>
	* arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
	Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
	and ARM_ARCH_V6ZKT2.

	2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
	* crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
	Remove redundant instruction types.
	(struct argument): X_op - new field.
	(struct cst4_entry): Remove.
	(no_op_insn): Declare.

	2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
	* crx.h (enum argtype): Rename types, remove unused types.

	2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
	* crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
	(enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
	(enum operand_type): Rearrange operands, edit comments.
	replace us<N> with ui<N> for unsigned immediate.
	replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
	displacements (respectively).
	replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
	(instruction type): Add NO_TYPE_INS.
	(instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
	(operand_entry): New field - 'flags'.
	(operand flags): New.

	2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
	* crx.h (operand_type): Remove redundant types i3, i4,
	i5, i8, i12.
	Add new unsigned immediate types us3, us4, us5, us16.

2005-04-12  Mark Kettenis  <kettenis@gnu.org>

	* i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
	adjust them accordingly.

2005-04-01  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add rdtscp.

2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Don't allow the `l' suffix for moving
	between memory and segment register. Allow movq for moving between
	general-purpose register and segment register.

2005-02-09  Jan Beulich  <jbeulich@novell.com>

	PR gas/707
	* i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
	FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
	fnstsw.

2005-01-25  Alexandre Oliva  <aoliva@redhat.com>

	2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
	* cgen.h (enum cgen_parse_operand_type): Add
	CGEN_PARSE_OPERAND_SYMBOLIC.

2005-01-21  Fred Fish  <fnf@specifixinc.com>

	* mips.h: Change INSN_ALIAS to INSN2_ALIAS.
	Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
	Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.

2005-01-19  Fred Fish  <fnf@specifixinc.com>

	* mips.h (struct mips_opcode): Add new pinfo2 member.
	(INSN_ALIAS): New define for opcode table entries that are
	specific instances of another entry, such as 'move' for an 'or'
	with a zero operand.
	(INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
	(INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.

2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>

	* mips.h (CPU_RM9000): Define.
	(OPCODE_IS_MEMBER): Handle CPU_RM9000.

2004-11-25 Jan Beulich  <jbeulich@novell.com>

	* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
	to/from test registers are illegal in 64-bit mode. Add missing
	NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
	(previously one had to explicitly encode a rex64 prefix). Re-enable
	lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
	support it there. Add cmpxchg16b as per Intel's 64-bit documentation.

2004-11-23 Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
	available only with SSE2. Change the MMX additions introduced by SSE
	and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
	instructions by their now designated identifier (since combining i686
	and 3DNow! does not really imply 3DNow!A).

2004-11-19  Alan Modra  <amodra@bigpond.net.au>

	* msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
	struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.

2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
	    Vineet Sharma      <vineets@noida.hcltech.com>

	* maxq.h: New file: Disassembly information for the maxq port.

2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Put back "movzb".

2004-11-04  Hans-Peter Nilsson  <hp@axis.com>

	* cris.h (enum cris_insn_version_usage): Tweak formatting and
	comments.  Remove member cris_ver_sim.  Add members
	cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
	cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
	(struct cris_support_reg, struct cris_cond15): New types.
	(cris_conds15): Declare.
	(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
	(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
	(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
	(NOP_Z_BITS): Define in terms of NOP_OPCODE.
	(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
	SIZE_FIELD_UNSIGNED.

2004-11-04 Jan Beulich  <jbeulich@novell.com>

	* i386.h (sldx_Suf): Remove.
	(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
	(q_FP): Define, implying no REX64.
	(x_FP, sl_FP): Imply FloatMF.
	(i386_optab): Split reg and mem forms of moving from segment registers
	so that the memory forms can ignore the 16-/32-bit operand size
	distinction. Adjust a few others for Intel mode. Remove *FP uses from
	all non-floating-point instructions. Unite 32- and 64-bit forms of
	movsx, movzx, and movd. Adjust floating point operations for the above
	changes to the *FP macros. Add DefaultSize to floating point control
	insns operating on larger memory ranges. Remove left over comments
	hinting at certain insns being Intel-syntax ones where the ones
	actually meant are already gone.

2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>

	* crx.h: Add COPS_REG_INS - Coprocessor Special register
	instruction type.

2004-09-30  Paul Brook  <paul@codesourcery.com>

	* arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
	(ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.

2004-09-11  Theodore A. Roth  <troth@openavr.org>

	* avr.h: Add support for
	atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.

2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>

	* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.

2004-08-24  Dmitry Diky  <diwil@spec.ru>

	* msp430.h (msp430_opc): Add new instructions.
	(msp430_rcodes): Declare new instructions.
	(msp430_hcodes): Likewise..

2004-08-13  Nick Clifton  <nickc@redhat.com>

	PR/301
	* h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
	processors.

2004-08-30  Michal Ludvig  <mludvig@suse.cz>

	* i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.

2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.

2004-07-21  Jan Beulich  <jbeulich@novell.com>

	* i386.h: Adjust instruction descriptions to better match the
	specification.

2004-07-16  Richard Earnshaw  <rearnsha@arm.com>

	* arm.h: Remove all old content.  Replace with architecture defines
	from gas/config/tc-arm.c.

2004-07-09  Andreas Schwab  <schwab@suse.de>

	* m68k.h: Fix comment.

2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>

	* crx.h: New file.

2004-06-24  Alan Modra  <amodra@bigpond.net.au>

	* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.

2004-05-24  Peter Barada  <peter@the-baradas.com>

	* m68k.h: Add 'size' to m68k_opcode.

2004-05-05  Peter Barada  <peter@the-baradas.com>

	* m68k.h: Switch from ColdFire chip name to core variant.

2004-04-22  Peter Barada  <peter@the-baradas.com>

	* m68k.h: Add mcfmac/mcfemac definitions.  Update operand
	descriptions for new EMAC cases.
	Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
	handle Motorola MAC syntax.
	Allow disassembly of ColdFire V4e object files.

2004-03-16  Alan Modra  <amodra@bigpond.net.au>

	* ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.

2004-03-12  Jakub Jelinek  <jakub@redhat.com>

	* i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.

2004-03-12  Michal Ludvig  <mludvig@suse.cz>

	* i386.h (i386_optab): Added xstore as an alias for xstorerng.

2004-03-12  Michal Ludvig  <mludvig@suse.cz>

	* i386.h (i386_optab): Added xstore/xcrypt insns.

2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>

	* h8300.h (32bit ldc/stc): Add relaxing support.

2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>

	* h8300.h (BITOP): Pass MEMRELAX flag.

2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>

	* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
	except for the H8S.

For older changes see ChangeLog-9103
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Commit	Line	Data
caa05036 DA	1	2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
	2
	3	* hppa.h (FLAG_STRICT): Correct comment.
	4	(pa_opcodes): Update load and store entries to allow both PA 1.X and
	5	PA 2.0 mneumonics when equivalent. Entries with cache control
	6	completers now require PA 1.1. Adjust whitespace.
	7
f4411256 AM	8	2005-05-19 Anton Blanchard <anton@samba.org>
	9
	10	* ppc.h (PPC_OPCODE_POWER5): Define.
	11
e172dbf8 NC	12	2005-05-10 Nick Clifton <nickc@redhat.com>
	13
	14	* Update the address and phone number of the FSF organization in
	15	the GPL notices in the following files:
	16	a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
	17	crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
	18	i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
	19	mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
	20	pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
	21	tic54x.h, tic80.h, v850.h, vax.h
	22
e44823cf JB	23	2005-05-09 Jan Beulich <jbeulich@novell.com>
	24
	25	* i386.h (i386_optab): Add ht and hnt.
	26
791fe849 MK	27	2005-04-18 Mark Kettenis <kettenis@gnu.org>
	28
	29	* i386.h: Insert hyphens into selected VIA PadLock extensions.
	30	Add xcrypt-ctr. Provide aliases without hyphens.
	31
faa7ef87 L	32	2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
faa7ef87 L	33
a63027e5 L	34	Moved from ../ChangeLog
a63027e5 L	35
faa7ef87 L	36	2005-04-12 Paul Brook <paul@codesourcery.com>
	37	* m88k.h: Rename psr macros to avoid conflicts.
	38
	39	2005-03-12 Zack Weinberg <zack@codesourcery.com>
	40	* arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
	41	Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
	42	and ARM_ARCH_V6ZKT2.
	43
	44	2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
	45	* crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
	46	Remove redundant instruction types.
	47	(struct argument): X_op - new field.
	48	(struct cst4_entry): Remove.
	49	(no_op_insn): Declare.
	50
	51	2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
	52	* crx.h (enum argtype): Rename types, remove unused types.
	53
	54	2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
	55	* crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
	56	(enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
	57	(enum operand_type): Rearrange operands, edit comments.
	58	replace us<N> with ui<N> for unsigned immediate.
	59	replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
	60	displacements (respectively).
	61	replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
	62	(instruction type): Add NO_TYPE_INS.
	63	(instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
	64	(operand_entry): New field - 'flags'.
	65	(operand flags): New.
	66
	67	2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
	68	* crx.h (operand_type): Remove redundant types i3, i4,
	69	i5, i8, i12.
	70	Add new unsigned immediate types us3, us4, us5, us16.
	71
bc4bd9ab MK	72	2005-04-12 Mark Kettenis <kettenis@gnu.org>
	73
	74	* i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
	75	adjust them accordingly.
	76
373ff435 JB	77	2005-04-01 Jan Beulich <jbeulich@novell.com>
	78
	79	* i386.h (i386_optab): Add rdtscp.
	80
4cc91dba L	81	2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
	82
	83	* i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca AS	84	between memory and segment register. Allow movq for moving between
418a8fca AS	85	general-purpose register and segment register.
4cc91dba	86
9ae09ff9 JB	87	2005-02-09 Jan Beulich <jbeulich@novell.com>
	88
	89	PR gas/707
	90	* i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
	91	FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
	92	fnstsw.
	93
90219bd0 AO	94	2005-01-25 Alexandre Oliva <aoliva@redhat.com>
	95
	96	2004-11-10 Alexandre Oliva <aoliva@redhat.com>
	97	* cgen.h (enum cgen_parse_operand_type): Add
	98	CGEN_PARSE_OPERAND_SYMBOLIC.
	99
239cb185 FF	100	2005-01-21 Fred Fish <fnf@specifixinc.com>
	101
	102	* mips.h: Change INSN_ALIAS to INSN2_ALIAS.
	103	Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
	104	Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
	105
dc9a9f39 FF	106	2005-01-19 Fred Fish <fnf@specifixinc.com>
	107
	108	* mips.h (struct mips_opcode): Add new pinfo2 member.
	109	(INSN_ALIAS): New define for opcode table entries that are
	110	specific instances of another entry, such as 'move' for an 'or'
	111	with a zero operand.
	112	(INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
	113	(INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
	114
98e7aba8 ILT	115	2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
	116
	117	* mips.h (CPU_RM9000): Define.
	118	(OPCODE_IS_MEMBER): Handle CPU_RM9000.
	119
37edbb65 JB	120	2004-11-25 Jan Beulich <jbeulich@novell.com>
	121
	122	* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
	123	to/from test registers are illegal in 64-bit mode. Add missing
	124	NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
	125	(previously one had to explicitly encode a rex64 prefix). Re-enable
	126	lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
	127	support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
	128
	129	2004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e JB	130
	131	* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
	132	available only with SSE2. Change the MMX additions introduced by SSE
	133	and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
	134	instructions by their now designated identifier (since combining i686
	135	and 3DNow! does not really imply 3DNow!A).
	136
f5c7edf4 AM	137	2004-11-19 Alan Modra <amodra@bigpond.net.au>
	138
	139	* msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
	140	struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
	141
7499d566 NC	142	2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
	143	Vineet Sharma <vineets@noida.hcltech.com>
	144
	145	* maxq.h: New file: Disassembly information for the maxq port.
	146
bcb9eebe L	147	2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
	148
	149	* i386.h (i386_optab): Put back "movzb".
	150
94bb3d38 HPN	151	2004-11-04 Hans-Peter Nilsson <hp@axis.com>
	152
	153	* cris.h (enum cris_insn_version_usage): Tweak formatting and
	154	comments. Remove member cris_ver_sim. Add members
	155	cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
	156	cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
	157	(struct cris_support_reg, struct cris_cond15): New types.
	158	(cris_conds15): Declare.
	159	(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
	160	(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
	161	(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
	162	(NOP_Z_BITS): Define in terms of NOP_OPCODE.
	163	(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
	164	SIZE_FIELD_UNSIGNED.
	165
37edbb65	166	2004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a JB	167
	168	* i386.h (sldx_Suf): Remove.
	169	(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
	170	(q_FP): Define, implying no REX64.
	171	(x_FP, sl_FP): Imply FloatMF.
	172	(i386_optab): Split reg and mem forms of moving from segment registers
	173	so that the memory forms can ignore the 16-/32-bit operand size
	174	distinction. Adjust a few others for Intel mode. Remove *FP uses from
	175	all non-floating-point instructions. Unite 32- and 64-bit forms of
	176	movsx, movzx, and movd. Adjust floating point operations for the above
	177	changes to the *FP macros. Add DefaultSize to floating point control
	178	insns operating on larger memory ranges. Remove left over comments
	179	hinting at certain insns being Intel-syntax ones where the ones
	180	actually meant are already gone.
	181
48c9f030 NC	182	2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
	183
	184	* crx.h: Add COPS_REG_INS - Coprocessor Special register
	185	instruction type.
	186
0dd132b6 NC	187	2004-09-30 Paul Brook <paul@codesourcery.com>
	188
	189	* arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
	190	(ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
	191
23794b24 MM	192	2004-09-11 Theodore A. Roth <troth@openavr.org>
	193
	194	* avr.h: Add support for
	195	atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
	196
2a309db0 AM	197	2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
	198
	199	* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
	200
b18c562e NC	201	2004-08-24 Dmitry Diky <diwil@spec.ru>
	202
	203	* msp430.h (msp430_opc): Add new instructions.
	204	(msp430_rcodes): Declare new instructions.
	205	(msp430_hcodes): Likewise..
	206
45d313cd NC	207	2004-08-13 Nick Clifton <nickc@redhat.com>
	208
	209	PR/301
	210	* h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
	211	processors.
	212
30d1c836 ML	213	2004-08-30 Michal Ludvig <mludvig@suse.cz>
	214
	215	* i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
	216
9a45f1c2 L	217	2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
	218
	219	* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
	220
543613e9 NC	221	2004-07-21 Jan Beulich <jbeulich@novell.com>
	222
	223	* i386.h: Adjust instruction descriptions to better match the
	224	specification.
	225
b781e558 RE	226	2004-07-16 Richard Earnshaw <rearnsha@arm.com>
	227
	228	* arm.h: Remove all old content. Replace with architecture defines
	229	from gas/config/tc-arm.c.
	230
8577e690 AS	231	2004-07-09 Andreas Schwab <schwab@suse.de>
	232
	233	* m68k.h: Fix comment.
	234
1fe1f39c NC	235	2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
	236
	237	* crx.h: New file.
	238
1d9f512f AM	239	2004-06-24 Alan Modra <amodra@bigpond.net.au>
	240
	241	* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
	242
be8c092b NC	243	2004-05-24 Peter Barada <peter@the-baradas.com>
	244
	245	* m68k.h: Add 'size' to m68k_opcode.
	246
6b6e92f4 NC	247	2004-05-05 Peter Barada <peter@the-baradas.com>
	248
	249	* m68k.h: Switch from ColdFire chip name to core variant.
	250
	251	2004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b NC	252
	253	* m68k.h: Add mcfmac/mcfemac definitions. Update operand
	254	descriptions for new EMAC cases.
	255	Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
	256	handle Motorola MAC syntax.
	257	Allow disassembly of ColdFire V4e object files.
	258
fdd12ef3 AM	259	2004-03-16 Alan Modra <amodra@bigpond.net.au>
	260
	261	* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
	262
3922a64c L	263	2004-03-12 Jakub Jelinek <jakub@redhat.com>
	264
	265	* i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
	266
1f45d988 ML	267	2004-03-12 Michal Ludvig <mludvig@suse.cz>
	268
	269	* i386.h (i386_optab): Added xstore as an alias for xstorerng.
	270
0f10071e ML	271	2004-03-12 Michal Ludvig <mludvig@suse.cz>
	272
	273	* i386.h (i386_optab): Added xstore/xcrypt insns.
	274
3255318a NC	275	2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
	276
	277	* h8300.h (32bit ldc/stc): Add relaxing support.
	278
ca9a79a1	279	2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3	280
ca9a79a1 NC	281	* h8300.h (BITOP): Pass MEMRELAX flag.
ca9a79a1 NC	282
875a0b14 NC	283	2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
	284
	285	* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
	286	except for the H8S.
252b5132	287
c9e214e5	288	For older changes see ChangeLog-9103
252b5132 RH	289	\f
252b5132 RH	290	Local Variables:
c9e214e5 AM	291	mode: change-log
	292	left-margin: 8
	293	fill-column: 74
252b5132 RH	294	version-control: never
252b5132 RH	295	End: