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[AArch64][libopcode] Add support for PAN architecture extension
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
f21cce2c
MW		 12015-06-01 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64.h (AARCH64_FEATURE_PAN): New.
4 (aarch64_sys_reg_supported_p): Declare.
5 (aarch64_pstatefield_supported_p): Declare.
6
0952813b
DD		 72015-04-30 DJ Delorie <dj@redhat.com>
8
9 * rl78.h (RL78_Dis_Isa): New.
10 (rl78_decode_opcode): Add ISA parameter.
11
823d2571
TG		 122015-03-24 Terry Guo <terry.guo@arm.com>
13
14 * arm.h (arm_feature_set): Extended to provide more available bits.
15 (ARM_ANY): Updated to follow above new definition.
16 (ARM_CPU_HAS_FEATURE): Likewise.
17 (ARM_CPU_IS_ANY): Likewise.
18 (ARM_MERGE_FEATURE_SETS): Likewise.
19 (ARM_CLEAR_FEATURE): Likewise.
20 (ARM_FEATURE): Likewise.
21 (ARM_FEATURE_COPY): New macro.
22 (ARM_FEATURE_EQUAL): Likewise.
23 (ARM_FEATURE_ZERO): Likewise.
24 (ARM_FEATURE_CORE_EQUAL): Likewise.
25 (ARM_FEATURE_LOW): Likewise.
26 (ARM_FEATURE_CORE_LOW): Likewise.
27 (ARM_FEATURE_CORE_COPROC): Likewise.
28
f63c1776
PA		 292015-02-19 Pedro Alves <palves@redhat.com>
30
31 * cgen.h [__cplusplus]: Wrap in extern "C".
32 * msp430-decode.h [__cplusplus]: Likewise.
33 * nios2.h [__cplusplus]: Likewise.
34 * rl78.h [__cplusplus]: Likewise.
35 * rx.h [__cplusplus]: Likewise.
36 * tilegx.h [__cplusplus]: Likewise.
37
3f8107ab
AM		 382015-01-28 James Bowman <james.bowman@ftdichip.com>
39
40 * ft32.h: New file.
41
1e2e8c52
AK		 422015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
43
44 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
45
b90efa5b
AM		 462015-01-01 Alan Modra <amodra@gmail.com>
47
48 Update year range in copyright notice of all files.
49
bffb6004
AG		 502014-12-27 Anthony Green <green@moxielogic.com>
51
52 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
53 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
54
1945cfa5
EB		 552014-12-06 Eric Botcazou <ebotcazou@adacore.com>
56
57 * visium.h: New file.
58
d306ce58
SL		 592014-11-28 Sandra Loosemore <sandra@codesourcery.com>
60
61 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
62 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
63 (NIOS2_INSN_OPTARG): Renumber.
64
b4714c7c
SL		 652014-11-06 Sandra Loosemore <sandra@codesourcery.com>
66
67 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
68 declaration. Fix obsolete comment.
69
96ba4233
SL		 702014-10-23 Sandra Loosemore <sandra@codesourcery.com>
71
72 * nios2.h (enum iw_format_type): New.
73 (struct nios2_opcode): Update comments. Add size and format fields.
74 (NIOS2_INSN_OPTARG): New.
75 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
76 (struct nios2_reg): Add regtype field.
77 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
78 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
79 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
80 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
81 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
82 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
83 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
84 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
85 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
86 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
87 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
88 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
89 (OP_MASK_OP, OP_SH_OP): Delete.
90 (OP_MASK_IOP, OP_SH_IOP): Delete.
91 (OP_MASK_IRD, OP_SH_IRD): Delete.
92 (OP_MASK_IRT, OP_SH_IRT): Delete.
93 (OP_MASK_IRS, OP_SH_IRS): Delete.
94 (OP_MASK_ROP, OP_SH_ROP): Delete.
95 (OP_MASK_RRD, OP_SH_RRD): Delete.
96 (OP_MASK_RRT, OP_SH_RRT): Delete.
97 (OP_MASK_RRS, OP_SH_RRS): Delete.
98 (OP_MASK_JOP, OP_SH_JOP): Delete.
99 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
100 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
101 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
102 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
103 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
104 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
105 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
106 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
107 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
108 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
109 (OP_MASK_<insn>, OP_MASK): Delete.
110 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
111 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
112 Include nios2r1.h to define new instruction opcode constants
113 and accessors.
114 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
115 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
116 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
117 (NUMOPCODES, NUMREGISTERS): Delete.
118 * nios2r1.h: New file.
119
0b6be415
JM		 1202014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
121
122 * sparc.h (HWCAP2_VIS3B): Documentation improved.
123
3d68f91c
JM		 1242014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
125
126 * sparc.h (sparc_opcode): new field `hwcaps2'.
127 (HWCAP2_FJATHPLUS): New define.
128 (HWCAP2_VIS3B): Likewise.
129 (HWCAP2_ADP): Likewise.
130 (HWCAP2_SPARC5): Likewise.
131 (HWCAP2_MWAIT): Likewise.
132 (HWCAP2_XMPMUL): Likewise.
133 (HWCAP2_XMONT): Likewise.
134 (HWCAP2_NSEC): Likewise.
135 (HWCAP2_FJATHHPC): Likewise.
136 (HWCAP2_FJDES): Likewise.
137 (HWCAP2_FJAES): Likewise.
138 Document the new operand kind `{', corresponding to the mcdper
139 ancillary state register.
140 Document the new operand kind }, which represents frsd floating
141 point registers (double precision) which must be the same than
142 frs1 in its containing instruction.
143
40c7a7cb
KLC		 1442014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
145
146 * nds32.h: Add new opcode declaration.
147
7361da2c
AB		 1482014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
149 Matthew Fortune <matthew.fortune@imgtec.com>
150
151 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
152 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
153 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
154 +I, +O, +R, +:, +\, +", +;
155 (mips_check_prev_operand): New struct.
156 (INSN2_FORBIDDEN_SLOT): New define.
157 (INSN_ISA32R6): New define.
158 (INSN_ISA64R6): New define.
159 (INSN_UPTO32R6): New define.
160 (INSN_UPTO64R6): New define.
161 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
162 (ISA_MIPS32R6): New define.
163 (ISA_MIPS64R6): New define.
164 (CPU_MIPS32R6): New define.
165 (CPU_MIPS64R6): New define.
166 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
167
ee804238
JW		 1682014-09-03 Jiong Wang <jiong.wang@arm.com>
169
170 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
171 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
172 (aarch64_insn_class): Add lse_atomic.
173 (F_LSE_SZ): New field added.
174 (opcode_has_special_coder): Recognize F_LSE_SZ.
175
5575639b
MR		 1762014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
177
178 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
179 over to `+J'.
180
43885403
MF		 1812014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
182
183 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
184 (INSN_LOAD_COPROC): New define.
185 (INSN_COPROC_MOVE_DELAY): Rename to...
186 (INSN_COPROC_MOVE): New define.
187
f36e8886
BS		 1882014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
189 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
190 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
191 Soundararajan <Sounderarajan.D@atmel.com>
192
193 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
194 (AVR_ISA_2xxxa): Define ISA without LPM.
195 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
196 Add doc for contraint used in 16 bit lds/sts.
197 Adjust ISA group for icall, ijmp, pop and push.
198 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
199
00b32ff2
NC		 2002014-05-19 Nick Clifton <nickc@redhat.com>
201
202 * msp430.h (struct msp430_operand_s): Add vshift field.
203
ae52f483
AB		 2042014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
205
206 * mips.h (INSN_ISA_MASK): Updated.
207 (INSN_ISA32R3): New define.
208 (INSN_ISA32R5): New define.
209 (INSN_ISA64R3): New define.
210 (INSN_ISA64R5): New define.
211 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
212 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
213 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
214 mips64r5.
215 (INSN_UPTO32R3): New define.
216 (INSN_UPTO32R5): New define.
217 (INSN_UPTO64R3): New define.
218 (INSN_UPTO64R5): New define.
219 (ISA_MIPS32R3): New define.
220 (ISA_MIPS32R5): New define.
221 (ISA_MIPS64R3): New define.
222 (ISA_MIPS64R5): New define.
223 (CPU_MIPS32R3): New define.
224 (CPU_MIPS32R5): New define.
225 (CPU_MIPS64R3): New define.
226 (CPU_MIPS64R5): New define.
227
3efe9ec5
RS		 2282014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
229
230 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
231
73589c9d
CS		 2322014-04-22 Christian Svensson <blue@cmd.nu>
233
234 * or32.h: Delete.
235
4b95cf5c
AM		 2362014-03-05 Alan Modra <amodra@gmail.com>
237
238 Update copyright years.
239
e269fea7
AB		 2402013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
241
242 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
243 microMIPS.
244
35c08157
KLC		 2452013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
246 Wei-Cheng Wang <cole945@gmail.com>
247
248 * nds32.h: New file for Andes NDS32.
249
594d8fa8
MF		 2502013-12-07 Mike Frysinger <vapier@gentoo.org>
251
252 * bfin.h: Remove +x file mode.
253
87b8eed7
YZ		 2542013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
255
256 * aarch64.h (aarch64_pstatefields): Change element type to
257 aarch64_sys_reg.
258
c9fb6e58
YZ		 2592013-11-18 Renlin Li <Renlin.Li@arm.com>
260
261 * arm.h (ARM_AEXT_V7VE): New define.
262 (ARM_ARCH_V7VE): New define.
263 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
264
a203d9b7
YZ		 2652013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
266
267 Revert
268
269 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
270
271 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
272 (aarch64_sys_reg_writeonly_p): Ditto.
273
75468c93
YZ		 2742013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
275
276 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
277 (aarch64_sys_reg_writeonly_p): Ditto.
278
49eec193
YZ		 2792013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
280
281 * aarch64.h (aarch64_sys_reg): New typedef.
282 (aarch64_sys_regs): Change to define with the new type.
283 (aarch64_sys_reg_deprecated_p): Declare.
284
68a64283
YZ		 2852013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
286
287 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
288 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
289
387a82f1
CF		 2902013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
291
292 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
293 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
294 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
295 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
296 For MIPS, update extension character sequences after +.
297 (ASE_MSA): New define.
298 (ASE_MSA64): New define.
299 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
300 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
301 For microMIPS, update extension character sequences after +.
302
9aff4b7a
NC		 3032013-08-23 Yuri Chornoivan <yurchor@ukr.net>
304
305 PR binutils/15834
306 * i960.h: Fix typos.
307
e423441d
RS		 3082013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
309
310 * mips.h: Remove references to "+I" and imm2_expr.
311
5e0dc5ba
RS		 3122013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
313
314 * mips.h (M_DEXT, M_DINS): Delete.
315
0f35dbc4
RS		 3162013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
317
318 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
319 (mips_optional_operand_p): New function.
320
14daeee3
RS		 3212013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
322 Richard Sandiford <rdsandiford@googlemail.com>
323
324 * mips.h: Document new VU0 operand characters.
325 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
326 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
327 (OP_REG_R5900_ACC): New mips_reg_operand_types.
328 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
329 (mips_vu0_channel_mask): Declare.
330
3ccad066
RS		 3312013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
332
333 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
334 (mips_int_operand_min, mips_int_operand_max): New functions.
335 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
336
fc76e730
RS		 3372013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
338
339 * mips.h (mips_decode_reg_operand): New function.
340 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
341 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
342 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
343 New macros.
344 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
345 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
346 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
347 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
348 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
349 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
350 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
351 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
352 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
353 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
354 macros to cover the gaps.
355 (INSN2_MOD_SP): Replace with...
356 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
357 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
358 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
359 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
360 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
361 Delete.
362
26545944
RS		 3632013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
364
365 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
366 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
367 (MIPS16_INSN_COND_BRANCH): Delete.
368
7e8b059b
L		 3692013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
370 Kirill Yukhin <kirill.yukhin@intel.com>
371 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
372
373 * i386.h (BND_PREFIX_OPCODE): New.
374
c3c07478
RS		 3752013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
376
377 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
378 OP_SAVE_RESTORE_LIST.
379 (decode_mips16_operand): Declare.
380
ab902481
RS		 3812013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
382
383 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
384 (mips_operand, mips_int_operand, mips_mapped_int_operand)
385 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
386 (mips_pcrel_operand): New structures.
387 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
388 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
389 (decode_mips_operand, decode_micromips_operand): Declare.
390
cc537e56
RS		 3912013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
392
393 * mips.h: Document MIPS16 "I" opcode.
394
f2ae14a1
RS		 3952013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
396
397 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
398 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
399 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
400 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
401 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
402 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
403 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
404 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
405 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
406 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
407 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
408 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
409 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
410 Rename to...
411 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
412 (M_USD_AB): ...these.
413
5c324c16
RS		 4142013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
415
416 * mips.h: Remove documentation of "[" and "]". Update documentation
417 of "k" and the MDMX formats.
418
23e69e47
RS		 4192013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
420
421 * mips.h: Update documentation of "+s" and "+S".
422
27c5c572
RS		 4232013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
424
425 * mips.h: Document "+i".
426
e76ff5ab
RS		 4272013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
428
429 * mips.h: Remove "mi" documentation. Update "mh" documentation.
430 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
431 Delete.
432 (INSN2_WRITE_GPR_MHI): Rename to...
433 (INSN2_WRITE_GPR_MH): ...this.
434
fa7616a4
RS		 4352013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
436
437 * mips.h: Remove documentation of "+D" and "+T".
438
18870af7
RS		 4392013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
440
441 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
442 Use "source" rather than "destination" for microMIPS "G".
443
833794fc
MR		 4442013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
445
446 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
447 values.
448
c3678916
RS		 4492013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
450
451 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
452
7f3c4072
CM		 4532013-06-17 Catherine Moore <clm@codesourcery.com>
454 Maciej W. Rozycki <macro@codesourcery.com>
455 Chao-Ying Fu <fu@mips.com>
456
457 * mips.h (OP_SH_EVAOFFSET): Define.
458 (OP_MASK_EVAOFFSET): Define.
459 (INSN_ASE_MASK): Delete.
460 (ASE_EVA): Define.
461 (M_CACHEE_AB, M_CACHEE_OB): New.
462 (M_LBE_OB, M_LBE_AB): New.
463 (M_LBUE_OB, M_LBUE_AB): New.
464 (M_LHE_OB, M_LHE_AB): New.
465 (M_LHUE_OB, M_LHUE_AB): New.
466 (M_LLE_AB, M_LLE_OB): New.
467 (M_LWE_OB, M_LWE_AB): New.
468 (M_LWLE_AB, M_LWLE_OB): New.
469 (M_LWRE_AB, M_LWRE_OB): New.
470 (M_PREFE_AB, M_PREFE_OB): New.
471 (M_SCE_AB, M_SCE_OB): New.
472 (M_SBE_OB, M_SBE_AB): New.
473 (M_SHE_OB, M_SHE_AB): New.
474 (M_SWE_OB, M_SWE_AB): New.
475 (M_SWLE_AB, M_SWLE_OB): New.
476 (M_SWRE_AB, M_SWRE_OB): New.
477 (MICROMIPSOP_SH_EVAOFFSET): Define.
478 (MICROMIPSOP_MASK_EVAOFFSET): Define.
479
0c8fe7cf
SL		 4802013-06-12 Sandra Loosemore <sandra@codesourcery.com>
481
482 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
483
c77c0862
RS		 4842013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
485
486 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
487
b015e599
AP		 4882013-05-09 Andrew Pinski <apinski@cavium.com>
489
490 * mips.h (OP_MASK_CODE10): Correct definition.
491 (OP_SH_CODE10): Likewise.
492 Add a comment that "+J" is used now for OP_*CODE10.
493 (INSN_ASE_MASK): Update.
494 (INSN_VIRT): New macro.
495 (INSN_VIRT64): New macro
496
13761a11
NC		 4972013-05-02 Nick Clifton <nickc@redhat.com>
498
499 * msp430.h: Add patterns for MSP430X instructions.
500
0afd1215
DM		 5012013-04-06 David S. Miller <davem@davemloft.net>
502
503 * sparc.h (F_PREFERRED): Define.
504 (F_PREF_ALIAS): Define.
505
41702d50
NC		 5062013-04-03 Nick Clifton <nickc@redhat.com>
507
508 * v850.h (V850_INVERSE_PCREL): Define.
509
e21e1a51
NC		 5102013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
511
512 PR binutils/15068
513 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
514
51dcdd4d
NC		 5152013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
516
517 PR binutils/15068
518 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
519 Add 16-bit opcodes.
520 * tic6xc-opcode-table.h: Add 16-bit insns.
521 * tic6x.h: Add support for 16-bit insns.
522
81f5558e
NC		 5232013-03-21 Michael Schewe <michael.schewe@gmx.net>
524
525 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
526 and mov.b/w/l Rs,@(d:32,ERd).
527
165546ad
NC		 5282013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
529
530 PR gas/15082
531 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
532 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
533 tic6x_operand_xregpair operand coding type.
534 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
535 opcode field, usu ORXREGD1324 for the src2 operand and remove the
536 TIC6X_FLAG_NO_CROSS.
537
795b8e6b
NC		 5382013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
539
540 PR gas/15095
541 * tic6x.h (enum tic6x_coding_method): Add
542 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
543 separately the msb and lsb of a register pair. This is needed to
544 encode the opcodes in the same way as TI assembler does.
545 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
546 and rsqrdp opcodes to use the new field coding types.
547
dd5181d5
KT		 5482013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
549
550 * arm.h (CRC_EXT_ARMV8): New constant.
551 (ARCH_CRC_ARMV8): New macro.
552
e60bb1dd
YZ		 5532013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
554
555 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
556
36591ba1
SL		 5572013-02-06 Sandra Loosemore <sandra@codesourcery.com>
558 Andrew Jenner <andrew@codesourcery.com>
559
560 Based on patches from Altera Corporation.
561
562 * nios2.h: New file.
563
e30181a5
YZ		 5642013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
565
566 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
567
0c9573f4
NC		 5682013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
569
570 PR gas/15069
571 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
572
981dc7f1
NC		 5732013-01-24 Nick Clifton <nickc@redhat.com>
574
575 * v850.h: Add e3v5 support.
576
f5555712
YZ		 5772013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
578
579 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
580
5817ffd1
PB		 5812013-01-10 Peter Bergner <bergner@vnet.ibm.com>
582
583 * ppc.h (PPC_OPCODE_POWER8): New define.
584 (PPC_OPCODE_HTM): Likewise.
585
a3c62988
NC		 5862013-01-10 Will Newton <will.newton@imgtec.com>
587
588 * metag.h: New file.
589
73335eae
NC		 5902013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
591
592 * cr16.h (make_instruction): Rename to cr16_make_instruction.
593 (match_opcode): Rename to cr16_match_opcode.
594
e407c74b
NC		 5952013-01-04 Juergen Urban <JuergenUrban@gmx.de>
596
597 * mips.h: Add support for r5900 instructions including lq and sq.
598
bab4becb
NC		 5992013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
600
601 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
602 (make_instruction,match_opcode): Added function prototypes.
603 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
604
776fc418
AM		 6052012-11-23 Alan Modra <amodra@gmail.com>
606
607 * ppc.h (ppc_parse_cpu): Update prototype.
608
f05682d4
DA		 6092012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
610
611 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
612 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
613
cfc72779
AK		 6142012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
615
616 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
617
b3e14eda
L		 6182012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
619
620 * ia64.h (ia64_opnd): Add new operand types.
621
2c63854f
DM		 6222012-08-21 David S. Miller <davem@davemloft.net>
623
624 * sparc.h (F3F4): New macro.
625
a06ea964 6262012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 627 Laurent Desnogues <laurent.desnogues@arm.com>
628 Jim MacArthur <jim.macarthur@arm.com>
629 Marcus Shawcroft <marcus.shawcroft@arm.com>
630 Nigel Stephens <nigel.stephens@arm.com>
631 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
632 Richard Earnshaw <rearnsha@arm.com>
633 Sofiane Naci <sofiane.naci@arm.com>
634 Tejas Belagod <tejas.belagod@arm.com>
635 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 636
637 * aarch64.h: New file.
638
35d0a169 6392012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 640 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 641
642 * mips.h (mips_opcode): Add the exclusions field.
643 (OPCODE_IS_MEMBER): Remove macro.
644 (cpu_is_member): New inline function.
645 (opcode_is_member): Likewise.
646
03f66e8a 6472012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 648 Catherine Moore <clm@codesourcery.com>
649 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 650
651 * mips.h: Document microMIPS DSP ASE usage.
652 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
653 microMIPS DSP ASE support.
654 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
655 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
656 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
657 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
658 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
659 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
660 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
661
9d7b4c23
MR		 6622012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
663
664 * mips.h: Fix a typo in description.
665
76e879f8
NC		 6662012-06-07 Georg-Johann Lay <avr@gjlay.de>
667
668 * avr.h: (AVR_ISA_XCH): New define.
669 (AVR_ISA_XMEGA): Use it.
670 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
671
6927f982
NC		 6722012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
673
674 * m68hc11.h: Add XGate definitions.
675 (struct m68hc11_opcode): Add xg_mask field.
676
b9c361e0
JL		 6772012-05-14 Catherine Moore <clm@codesourcery.com>
678 Maciej W. Rozycki <macro@codesourcery.com>
679 Rhonda Wittels <rhonda@codesourcery.com>
680
6927f982 681 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 682 (PPC_OP_SA): New macro.
683 (PPC_OP_SE_VLE): New macro.
684 (PPC_OP): Use a variable shift amount.
685 (powerpc_operand): Update comments.
686 (PPC_OPSHIFT_INV): New macro.
687 (PPC_OPERAND_CR): Replace with...
688 (PPC_OPERAND_CR_BIT): ...this and
689 (PPC_OPERAND_CR_REG): ...this.
690
691
f6c1a2d5
NC		 6922012-05-03 Sean Keys <skeys@ipdatasys.com>
693
694 * xgate.h: Header file for XGATE assembler.
695
ec668d69
DM		 6962012-04-27 David S. Miller <davem@davemloft.net>
697
6cda1326
DM		 698 * sparc.h: Document new arg code' )' for crypto RS3
699 immediates.
700
ec668d69
DM		 701 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
702 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
703 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
704 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
705 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
706 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
707 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
708 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
709 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
710 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
711 HWCAP_CBCOND, HWCAP_CRC32): New defines.
712
aea77599
AM		 7132012-03-10 Edmar Wienskoski <edmar@freescale.com>
714
715 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
716
1f42f8b3
AM		 7172012-02-27 Alan Modra <amodra@gmail.com>
718
719 * crx.h (cst4_map): Update declaration.
720
6f7be959
WL		 7212012-02-25 Walter Lee <walt@tilera.com>
722
723 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
724 TILEGX_OPC_LD_TLS.
725 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
726 TILEPRO_OPC_LW_TLS_SN.
727
42164a71
L		 7282012-02-08 H.J. Lu <hongjiu.lu@intel.com>
729
730 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
731 (XRELEASE_PREFIX_OPCODE): Likewise.
732
432233b3 7332011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 734 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 735
736 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
737 (INSN_OCTEON2): New macro.
738 (CPU_OCTEON2): New macro.
739 (OPCODE_IS_MEMBER): Add Octeon2.
740
dd6a37e7
AP		 7412011-11-29 Andrew Pinski <apinski@cavium.com>
742
743 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
744 (INSN_OCTEONP): New macro.
745 (CPU_OCTEONP): New macro.
746 (OPCODE_IS_MEMBER): Add Octeon+.
747 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
748
99c513f6
DD		 7492011-11-01 DJ Delorie <dj@redhat.com>
750
751 * rl78.h: New file.
752
26f85d7a
MR		 7532011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
754
755 * mips.h: Fix a typo in description.
756
9e8c70f9
DM		 7572011-09-21 David S. Miller <davem@davemloft.net>
758
759 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
760 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
761 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
762 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
763
dec0624d 7642011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 765 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 766
767 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
768 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
769 (INSN_ASE_MASK): Add the MCU bit.
770 (INSN_MCU): New macro.
771 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
772 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
773
2b0c8b40
MR		 7742011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
775
776 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
777 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
778 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
779 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
780 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
781 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
782 (INSN2_READ_GPR_MMN): Likewise.
783 (INSN2_READ_FPR_D): Change the bit used.
784 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
785 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
786 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
787 (INSN2_COND_BRANCH): Likewise.
788 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
789 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
790 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
791 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
792 (INSN2_MOD_GPR_MN): Likewise.
793
ea783ef3
DM		 7942011-08-05 David S. Miller <davem@davemloft.net>
795
796 * sparc.h: Document new format codes '4', '5', and '('.
797 (OPF_LOW4, RS3): New macros.
798
7c176fa8
MR		 7992011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
800
801 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
802 order of flags documented.
803
2309ddf2
MR		 8042011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
805
806 * mips.h: Clarify the description of microMIPS instruction
807 manipulation macros.
808 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
809
df58fc94 8102011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 811 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 812
813 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
814 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
815 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
816 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
817 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
818 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
819 (OP_MASK_RS3, OP_SH_RS3): Likewise.
820 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
821 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
822 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
823 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
824 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
825 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
826 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
827 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
828 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
829 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
830 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
831 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
832 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
833 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
834 (INSN_WRITE_GPR_S): New macro.
835 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
836 (INSN2_READ_FPR_D): Likewise.
837 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
838 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
839 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
840 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
841 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
842 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
843 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
844 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
845 (CPU_MICROMIPS): New macro.
846 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
847 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
848 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
849 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
850 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
851 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
852 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
853 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
854 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
855 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
856 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
857 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
858 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
859 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
860 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
861 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
862 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
863 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
864 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
865 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
866 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
867 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
868 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
869 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
870 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
871 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
872 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
873 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
874 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
875 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
876 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
877 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
878 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
879 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
880 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
881 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
882 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
883 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
884 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
885 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
886 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
887 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
888 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
889 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
890 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
891 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
892 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
893 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
894 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
895 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
896 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
897 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
898 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
899 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
900 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
901 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
902 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
903 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
904 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
905 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
906 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
907 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
908 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
909 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
910 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
911 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
912 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
913 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
914 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
915 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
916 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
917 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
918 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
919 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
920 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
921 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
922 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
923 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
924 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
925 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
926 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
927 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
928 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
929 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
930 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
931 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
932 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
933 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
934 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
935 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
936 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
937 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
938 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
939 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
940 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
941 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
942 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
943 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
944 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
945 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
946 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
947 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
948 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
949 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
950 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
951 (micromips_opcodes): New declaration.
952 (bfd_micromips_num_opcodes): Likewise.
953
bcd530a7
RS		 9542011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
955
956 * mips.h (INSN_TRAP): Rename to...
957 (INSN_NO_DELAY_SLOT): ... this.
958 (INSN_SYNC): Remove macro.
959
2dad5a91
EW		 9602011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
961
962 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
963 a duplicate of AVR_ISA_SPM.
964
5d73b1f1
NC		 9652011-07-01 Nick Clifton <nickc@redhat.com>
966
967 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
968
ef26d60e
MF		 9692011-06-18 Robin Getz <robin.getz@analog.com>
970
971 * bfin.h (is_macmod_signed): New func
972
8fb8dca7
MF		 9732011-06-18 Mike Frysinger <vapier@gentoo.org>
974
975 * bfin.h (is_macmod_pmove): Add missing space before func args.
976 (is_macmod_hmove): Likewise.
977
aa137e4d
NC		 9782011-06-13 Walter Lee <walt@tilera.com>
979
980 * tilegx.h: New file.
981 * tilepro.h: New file.
982
3b2f0793
PB		 9832011-05-31 Paul Brook <paul@codesourcery.com>
984
aa137e4d
NC		 985 * arm.h (ARM_ARCH_V7R_IDIV): Define.
986
9872011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
988
989 * s390.h: Replace S390_OPERAND_REG_EVEN with
990 S390_OPERAND_REG_PAIR.
991
9922011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
993
994 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 995
ac7f631b
NC		 9962011-04-18 Julian Brown <julian@codesourcery.com>
997
998 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
999
84701018
NC		 10002011-04-11 Dan McDonald <dan@wellkeeper.com>
1001
1002 PR gas/12296
1003 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1004
8cc66334
EW		 10052011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1006
1007 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1008 New instruction set flags.
1009 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1010
3eebd5eb
MR		 10112011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1012
1013 * mips.h (M_PREF_AB): New enum value.
1014
26bb3ddd
MF		 10152011-02-12 Mike Frysinger <vapier@gentoo.org>
1016
89c0d58c
MR		 1017 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1018 M_IU): Define.
1019 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1020
dd76fcb8
MF		 10212011-02-11 Mike Frysinger <vapier@gentoo.org>
1022
1023 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1024
98d23bef
BS		 10252011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1026
1027 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1028 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1029
3c853d93
DA		 10302010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1031
1032 PR gas/11395
1033 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1034 "bb" entries.
1035
79676006
DA		 10362010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1037
1038 PR gas/11395
1039 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1040
1bec78e9
RS		 10412010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1042
1043 * mips.h: Update commentary after last commit.
1044
98675402
RS		 10452010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1046
1047 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1048 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1049 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1050
aa137e4d
NC		 10512010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1052
1053 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1054
435b94a4
RS		 10552010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1056
1057 * mips.h: Fix previous commit.
1058
d051516a
NC		 10592010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1060
1061 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1062 (INSN_LOONGSON_3A): Clear bit 31.
1063
251665fc
MGD		 10642010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1065
1066 PR gas/12198
1067 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1068 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1069 (ARM_ARCH_V6M_ONLY): New define.
1070
fd503541
NC		 10712010-11-11 Mingming Sun <mingm.sun@gmail.com>
1072
1073 * mips.h (INSN_LOONGSON_3A): Defined.
1074 (CPU_LOONGSON_3A): Defined.
1075 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1076
4469d2be
AM		 10772010-10-09 Matt Rice <ratmice@gmail.com>
1078
1079 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1080 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1081
90ec0d68
MGD		 10822010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1083
1084 * arm.h (ARM_EXT_VIRT): New define.
1085 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1086 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1087 Extensions.
1088
eea54501 10892010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1090
eea54501
MGD		 1091 * arm.h (ARM_AEXT_ADIV): New define.
1092 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1093
b2a5fbdc
MGD		 10942010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1095
1096 * arm.h (ARM_EXT_OS): New define.
1097 (ARM_AEXT_V6SM): Likewise.
1098 (ARM_ARCH_V6SM): Likewise.
1099
60e5ef9f
MGD		 11002010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1101
1102 * arm.h (ARM_EXT_MP): Add.
1103 (ARM_ARCH_V7A_MP): Likewise.
1104
73a63ccf
MF		 11052010-09-22 Mike Frysinger <vapier@gentoo.org>
1106
1107 * bfin.h: Declare pseudoChr structs/defines.
1108
ee99860a
MF		 11092010-09-21 Mike Frysinger <vapier@gentoo.org>
1110
1111 * bfin.h: Strip trailing whitespace.
1112
f9c7014e
DD		 11132010-07-29 DJ Delorie <dj@redhat.com>
1114
1115 * rx.h (RX_Operand_Type): Add TwoReg.
1116 (RX_Opcode_ID): Remove ediv and ediv2.
1117
93378652
DD		 11182010-07-27 DJ Delorie <dj@redhat.com>
1119
1120 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1121
1cd986c5
NC		 11222010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1123 Ina Pandit <ina.pandit@kpitcummins.com>
1124
1125 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1126 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1127 PROCESSOR_V850E2_ALL.
1128 Remove PROCESSOR_V850EA support.
1129 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1130 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1131 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1132 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1133 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1134 V850_OPERAND_PERCENT.
1135 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1136 V850_NOT_R0.
1137 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1138 and V850E_PUSH_POP
1139
9a2c7088
MR		 11402010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1141
1142 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1143 (MIPS16_INSN_BRANCH): Rename to...
1144 (MIPS16_INSN_COND_BRANCH): ... this.
1145
bdc70b4a
AM		 11462010-07-03 Alan Modra <amodra@gmail.com>
1147
1148 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1149 Renumber other PPC_OPCODE defines.
1150
f2bae120
AM		 11512010-07-03 Alan Modra <amodra@gmail.com>
1152
1153 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1154
360cfc9c
AM		 11552010-06-29 Alan Modra <amodra@gmail.com>
1156
1157 * maxq.h: Delete file.
1158
e01d869a
AM		 11592010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1160
1161 * ppc.h (PPC_OPCODE_E500): Define.
1162
f79e2745
CM		 11632010-05-26 Catherine Moore <clm@codesourcery.com>
1164
1165 * opcode/mips.h (INSN_MIPS16): Remove.
1166
2462afa1
JM		 11672010-04-21 Joseph Myers <joseph@codesourcery.com>
1168
1169 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1170
e4e42b45
NC		 11712010-04-15 Nick Clifton <nickc@redhat.com>
1172
1173 * alpha.h: Update copyright notice to use GPLv3.
1174 * arc.h: Likewise.
1175 * arm.h: Likewise.
1176 * avr.h: Likewise.
1177 * bfin.h: Likewise.
1178 * cgen.h: Likewise.
1179 * convex.h: Likewise.
1180 * cr16.h: Likewise.
1181 * cris.h: Likewise.
1182 * crx.h: Likewise.
1183 * d10v.h: Likewise.
1184 * d30v.h: Likewise.
1185 * dlx.h: Likewise.
1186 * h8300.h: Likewise.
1187 * hppa.h: Likewise.
1188 * i370.h: Likewise.
1189 * i386.h: Likewise.
1190 * i860.h: Likewise.
1191 * i960.h: Likewise.
1192 * ia64.h: Likewise.
1193 * m68hc11.h: Likewise.
1194 * m68k.h: Likewise.
1195 * m88k.h: Likewise.
1196 * maxq.h: Likewise.
1197 * mips.h: Likewise.
1198 * mmix.h: Likewise.
1199 * mn10200.h: Likewise.
1200 * mn10300.h: Likewise.
1201 * msp430.h: Likewise.
1202 * np1.h: Likewise.
1203 * ns32k.h: Likewise.
1204 * or32.h: Likewise.
1205 * pdp11.h: Likewise.
1206 * pj.h: Likewise.
1207 * pn.h: Likewise.
1208 * ppc.h: Likewise.
1209 * pyr.h: Likewise.
1210 * rx.h: Likewise.
1211 * s390.h: Likewise.
1212 * score-datadep.h: Likewise.
1213 * score-inst.h: Likewise.
1214 * sparc.h: Likewise.
1215 * spu-insns.h: Likewise.
1216 * spu.h: Likewise.
1217 * tic30.h: Likewise.
1218 * tic4x.h: Likewise.
1219 * tic54x.h: Likewise.
1220 * tic80.h: Likewise.
1221 * v850.h: Likewise.
1222 * vax.h: Likewise.
1223
40b36596
JM		 12242010-03-25 Joseph Myers <joseph@codesourcery.com>
1225
1226 * tic6x-control-registers.h, tic6x-insn-formats.h,
1227 tic6x-opcode-table.h, tic6x.h: New.
1228
c67a084a
NC		 12292010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1230
1231 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1232
466ef64f
AM		 12332010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1234
1235 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1236
1319d143
L		 12372010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1238
1239 * ia64.h (ia64_find_opcode): Remove argument name.
1240 (ia64_find_next_opcode): Likewise.
1241 (ia64_dis_opcode): Likewise.
1242 (ia64_free_opcode): Likewise.
1243 (ia64_find_dependency): Likewise.
1244
1fbb9298
DE		 12452009-11-22 Doug Evans <dje@sebabeach.org>
1246
1247 * cgen.h: Include bfd_stdint.h.
1248 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1249
ada65aa3
PB		 12502009-11-18 Paul Brook <paul@codesourcery.com>
1251
1252 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1253
9e3c6df6
PB		 12542009-11-17 Paul Brook <paul@codesourcery.com>
1255 Daniel Jacobowitz <dan@codesourcery.com>
1256
1257 * arm.h (ARM_EXT_V6_DSP): Define.
1258 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1259 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1260
0d734b5d
DD		 12612009-11-04 DJ Delorie <dj@redhat.com>
1262
1263 * rx.h (rx_decode_opcode) (mvtipl): Add.
1264 (mvtcp, mvfcp, opecp): Remove.
1265
62f3b8c8
PB		 12662009-11-02 Paul Brook <paul@codesourcery.com>
1267
1268 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1269 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1270 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1271 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1272 FPU_ARCH_NEON_VFP_V4): Define.
1273
ac1e9eca
DE		 12742009-10-23 Doug Evans <dje@sebabeach.org>
1275
1276 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1277 * cgen.h: Update. Improve multi-inclusion macro name.
1278
9fe54b1c
PB		 12792009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1280
1281 * ppc.h (PPC_OPCODE_476): Define.
1282
634b50f2
PB		 12832009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1284
1285 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1286
c7927a3c
NC		 12872009-09-29 DJ Delorie <dj@redhat.com>
1288
1289 * rx.h: New file.
1290
b961e85b
AM		 12912009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1292
1293 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1294
e0d602ec
BE		 12952009-09-21 Ben Elliston <bje@au.ibm.com>
1296
1297 * ppc.h (PPC_OPCODE_PPCA2): New.
1298
96d56e9f
NC		 12992009-09-05 Martin Thuresson <martin@mtme.org>
1300
1301 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1302
d3ce72d0
NC		 13032009-08-29 Martin Thuresson <martin@mtme.org>
1304
1305 * tic30.h (template): Rename type template to
1306 insn_template. Updated code to use new name.
1307 * tic54x.h (template): Rename type template to
1308 insn_template.
1309
824b28db
NH		 13102009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1311
1312 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1313
f865a31d
AG		 13142009-06-11 Anthony Green <green@moxielogic.com>
1315
1316 * moxie.h (MOXIE_F3_PCREL): Define.
1317 (moxie_form3_opc_info): Grow.
1318
0e7c7f11
AG		 13192009-06-06 Anthony Green <green@moxielogic.com>
1320
1321 * moxie.h (MOXIE_F1_M): Define.
1322
20135e4c
NC		 13232009-04-15 Anthony Green <green@moxielogic.com>
1324
1325 * moxie.h: Created.
1326
bcb012d3
DD		 13272009-04-06 DJ Delorie <dj@redhat.com>
1328
1329 * h8300.h: Add relaxation attributes to MOVA opcodes.
1330
69fe9ce5
AM		 13312009-03-10 Alan Modra <amodra@bigpond.net.au>
1332
1333 * ppc.h (ppc_parse_cpu): Declare.
1334
c3b7224a
NC		 13352009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1336
1337 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1338 and _IMM11 for mbitclr and mbitset.
1339 * score-datadep.h: Update dependency information.
1340
066be9f7
PB		 13412009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1342
1343 * ppc.h (PPC_OPCODE_POWER7): New.
1344
fedc618e
DE		 13452009-02-06 Doug Evans <dje@google.com>
1346
1347 * i386.h: Add comment regarding sse* insns and prefixes.
1348
52b6b6b9
JM		 13492009-02-03 Sandip Matte <sandip@rmicorp.com>
1350
1351 * mips.h (INSN_XLR): Define.
1352 (INSN_CHIP_MASK): Update.
1353 (CPU_XLR): Define.
1354 (OPCODE_IS_MEMBER): Update.
1355 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1356
35669430
DE		 13572009-01-28 Doug Evans <dje@google.com>
1358
1359 * opcode/i386.h: Add multiple inclusion protection.
1360 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1361 (EDI_REG_NUM): New macros.
1362 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1363 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1364 (REX_PREFIX_P): New macro.
35669430 1365
1cb0a767
PB		 13662009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1367
1368 * ppc.h (struct powerpc_opcode): New field "deprecated".
1369 (PPC_OPCODE_NOPOWER4): Delete.
1370
3aa3176b
TS		 13712008-11-28 Joshua Kinard <kumba@gentoo.org>
1372
1373 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1374 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1375
8e79c3df
CM		 13762008-11-18 Catherine Moore <clm@codesourcery.com>
1377
1378 * arm.h (FPU_NEON_FP16): New.
1379 (FPU_ARCH_NEON_FP16): New.
1380
de9a3e51
CF		 13812008-11-06 Chao-ying Fu <fu@mips.com>
1382
1383 * mips.h: Doucument '1' for 5-bit sync type.
1384
1ca35711
L		 13852008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1386
1387 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1388 IA64_RS_CR.
1389
9b4e5766
PB		 13902008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1391
1392 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1393
081ba1b3
AM		 13942008-07-30 Michael J. Eager <eager@eagercon.com>
1395
1396 * ppc.h (PPC_OPCODE_405): Define.
1397 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1398
fa452fa6
PB		 13992008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1400
1401 * ppc.h (ppc_cpu_t): New typedef.
1402 (struct powerpc_opcode <flags>): Use it.
1403 (struct powerpc_operand <insert, extract>): Likewise.
1404 (struct powerpc_macro <flags>): Likewise.
1405
bb35fb24
NC		 14062008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1407
1408 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1409 Update comment before MIPS16 field descriptors to mention MIPS16.
1410 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1411 BBIT.
1412 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1413 New bit masks and shift counts for cins and exts.
1414
dd3cbb7e
NC		 1415 * mips.h: Document new field descriptors +Q.
1416 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1417
d0799671
AN		 14182008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1419
9aff4b7a 1420 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1421 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1422
19a6653c
AM		 14232008-04-14 Edmar Wienskoski <edmar@freescale.com>
1424
1425 * ppc.h: (PPC_OPCODE_E500MC): New.
1426
c0f3af97
L		 14272008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1428
1429 * i386.h (MAX_OPERANDS): Set to 5.
1430 (MAX_MNEM_SIZE): Changed to 20.
1431
e210c36b
NC		 14322008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1433
1434 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1435
b1cc4aeb
PB		 14362008-03-09 Paul Brook <paul@codesourcery.com>
1437
1438 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1439
7e806470
PB		 14402008-03-04 Paul Brook <paul@codesourcery.com>
1441
1442 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1443 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1444 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1445
7b2185f9 14462008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1447 Nick Clifton <nickc@redhat.com>
1448
1449 PR 3134
1450 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1451 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1452 set.
af7329f0 1453
796d5313
NC		 14542008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1455
1456 * cr16.h (cr16_num_optab): Declared.
1457
d669d37f
NC		 14582008-02-14 Hakan Ardo <hakan@debian.org>
1459
1460 PR gas/2626
1461 * avr.h (AVR_ISA_2xxe): Define.
1462
e6429699
AN		 14632008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1464
1465 * mips.h: Update copyright.
1466 (INSN_CHIP_MASK): New macro.
1467 (INSN_OCTEON): New macro.
1468 (CPU_OCTEON): New macro.
1469 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1470
e210c36b
NC		 14712008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1472
1473 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1474
14752008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1476
1477 * avr.h (AVR_ISA_USB162): Add new opcode set.
1478 (AVR_ISA_AVR3): Likewise.
1479
350cc38d
MS		 14802007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1481
1482 * mips.h (INSN_LOONGSON_2E): New.
1483 (INSN_LOONGSON_2F): New.
1484 (CPU_LOONGSON_2E): New.
1485 (CPU_LOONGSON_2F): New.
1486 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1487
56950294
MS		 14882007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1489
1490 * mips.h (INSN_ISA*): Redefine certain values as an
1491 enumeration. Update comments.
1492 (mips_isa_table): New.
1493 (ISA_MIPS*): Redefine to match enumeration.
1494 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1495 values.
1496
c3d65c1c
BE		 14972007-08-08 Ben Elliston <bje@au.ibm.com>
1498
1499 * ppc.h (PPC_OPCODE_PPCPS): New.
1500
0fdaa005
L		 15012007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1502
1503 * m68k.h: Document j K & E.
1504
15052007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1506
1507 * cr16.h: New file for CR16 target.
1508
3896c469
AM		 15092007-05-02 Alan Modra <amodra@bigpond.net.au>
1510
1511 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1512
9a2e615a
NS		 15132007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1514
1515 * m68k.h (mcfisa_c): New.
1516 (mcfusp, mcf_mask): Adjust.
1517
b84bf58a
AM		 15182007-04-20 Alan Modra <amodra@bigpond.net.au>
1519
1520 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1521 (num_powerpc_operands): Declare.
1522 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1523 (PPC_OPERAND_PLUS1): Define.
1524
831480e9 15252007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1526
1527 * i386.h (REX_MODE64): Renamed to ...
1528 (REX_W): This.
1529 (REX_EXTX): Renamed to ...
1530 (REX_R): This.
1531 (REX_EXTY): Renamed to ...
1532 (REX_X): This.
1533 (REX_EXTZ): Renamed to ...
1534 (REX_B): This.
1535
0b1cf022
L		 15362007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1537
1538 * i386.h: Add entries from config/tc-i386.h and move tables
1539 to opcodes/i386-opc.h.
1540
d796c0ad
L		 15412007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1542
1543 * i386.h (FloatDR): Removed.
1544 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1545
30ac7323
AM		 15462007-03-01 Alan Modra <amodra@bigpond.net.au>
1547
1548 * spu-insns.h: Add soma double-float insns.
1549
8b082fb1 15502007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1551 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1552
1553 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1554 (INSN_DSPR2): Add flag for DSP R2 instructions.
1555 (M_BALIGN): New macro.
1556
4eed87de
AM		 15572007-02-14 Alan Modra <amodra@bigpond.net.au>
1558
1559 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1560 and Seg3ShortFrom with Shortform.
1561
fda592e8
L		 15622007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1563
1564 PR gas/4027
1565 * i386.h (i386_optab): Put the real "test" before the pseudo
1566 one.
1567
3bdcfdf4
KH		 15682007-01-08 Kazu Hirata <kazu@codesourcery.com>
1569
1570 * m68k.h (m68010up): OR fido_a.
1571
9840d27e
KH		 15722006-12-25 Kazu Hirata <kazu@codesourcery.com>
1573
1574 * m68k.h (fido_a): New.
1575
c629cdac
KH		 15762006-12-24 Kazu Hirata <kazu@codesourcery.com>
1577
1578 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1579 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1580 values.
1581
b7d9ef37
L		 15822006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1583
1584 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1585
b138abaa
NC		 15862006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1587
1588 * score-inst.h (enum score_insn_type): Add Insn_internal.
1589
e9f53129
AM		 15902006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1591 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1592 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1593 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1594 Alan Modra <amodra@bigpond.net.au>
1595
1596 * spu-insns.h: New file.
1597 * spu.h: New file.
1598
ede602d7
AM		 15992006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1600
1601 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1602
7918206c
MM		 16032006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1604
e4e42b45 1605 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1606 in amdfam10 architecture.
1607
ef05d495
L		 16082006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1609
1610 * i386.h: Replace CpuMNI with CpuSSSE3.
1611
2d447fca 16122006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1613 Joseph Myers <joseph@codesourcery.com>
1614 Ian Lance Taylor <ian@wasabisystems.com>
1615 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1616
1617 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1618
1c0d3aa6
NC		 16192006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1620
1621 * score-datadep.h: New file.
1622 * score-inst.h: New file.
1623
c2f0420e
L		 16242006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1625
1626 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1627 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1628 movdq2q and movq2dq.
1629
050dfa73
MM		 16302006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1631 Michael Meissner <michael.meissner@amd.com>
1632
1633 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1634
15965411
L		 16352006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1636
1637 * i386.h (i386_optab): Add "nop" with memory reference.
1638
46e883c5
L		 16392006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1640
1641 * i386.h (i386_optab): Update comment for 64bit NOP.
1642
9622b051
AM		 16432006-06-06 Ben Elliston <bje@au.ibm.com>
1644 Anton Blanchard <anton@samba.org>
1645
1646 * ppc.h (PPC_OPCODE_POWER6): Define.
1647 Adjust whitespace.
1648
a9e24354
TS		 16492006-06-05 Thiemo Seufer <ths@mips.com>
1650
e4e42b45 1651 * mips.h: Improve description of MT flags.
a9e24354 1652
a596001e
RS		 16532006-05-25 Richard Sandiford <richard@codesourcery.com>
1654
1655 * m68k.h (mcf_mask): Define.
1656
d43b4baf 16572006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1658 David Ung <davidu@mips.com>
d43b4baf
TS		 1659
1660 * mips.h (enum): Add macro M_CACHE_AB.
1661
39a7806d 16622006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1663 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1664 David Ung <davidu@mips.com>
1665
1666 * mips.h: Add INSN_SMARTMIPS define.
1667
9bcd4f99 16682006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1669 David Ung <davidu@mips.com>
9bcd4f99
TS		 1670
1671 * mips.h: Defines udi bits and masks. Add description of
1672 characters which may appear in the args field of udi
1673 instructions.
1674
ef0ee844
TS		 16752006-04-26 Thiemo Seufer <ths@networkno.de>
1676
1677 * mips.h: Improve comments describing the bitfield instruction
1678 fields.
1679
f7675147
L		 16802006-04-26 Julian Brown <julian@codesourcery.com>
1681
1682 * arm.h (FPU_VFP_EXT_V3): Define constant.
1683 (FPU_NEON_EXT_V1): Likewise.
1684 (FPU_VFP_HARD): Update.
1685 (FPU_VFP_V3): Define macro.
1686 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1687
ef0ee844 16882006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1689
1690 * avr.h (AVR_ISA_PWMx): New.
1691
2da12c60
NS		 16922006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1693
1694 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1695 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1696 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1697 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1698 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1699
0715c387
PB		 17002006-03-10 Paul Brook <paul@codesourcery.com>
1701
1702 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1703
34bdd094
DA		 17042006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1705
1706 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1707 first. Correct mask of bb "B" opcode.
1708
331d2d0d
L		 17092006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1710
1711 * i386.h (i386_optab): Support Intel Merom New Instructions.
1712
62b3e311
PB		 17132006-02-24 Paul Brook <paul@codesourcery.com>
1714
1715 * arm.h: Add V7 feature bits.
1716
59cf82fe
L		 17172006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1718
1719 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1720
e74cfd16
PB		 17212006-01-31 Paul Brook <paul@codesourcery.com>
1722 Richard Earnshaw <rearnsha@arm.com>
1723
1724 * arm.h: Use ARM_CPU_FEATURE.
1725 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1726 (arm_feature_set): Change to a structure.
1727 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1728 ARM_FEATURE): New macros.
1729
5b3f8a92
HPN		 17302005-12-07 Hans-Peter Nilsson <hp@axis.com>
1731
1732 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1733 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1734 (ADD_PC_INCR_OPCODE): Don't define.
1735
cb712a9e
L		 17362005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1737
1738 PR gas/1874
1739 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1740
0499d65b
TS		 17412005-11-14 David Ung <davidu@mips.com>
1742
1743 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1744 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1745 save/restore encoding of the args field.
1746
ea5ca089
DB		 17472005-10-28 Dave Brolley <brolley@redhat.com>
1748
1749 Contribute the following changes:
1750 2005-02-16 Dave Brolley <brolley@redhat.com>
1751
1752 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1753 cgen_isa_mask_* to cgen_bitset_*.
1754 * cgen.h: Likewise.
1755
16175d96
DB		 1756 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1757
1758 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1759 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1760 (CGEN_CPU_TABLE): Make isas a ponter.
1761
1762 2003-09-29 Dave Brolley <brolley@redhat.com>
1763
1764 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1765 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1766 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1767
1768 2002-12-13 Dave Brolley <brolley@redhat.com>
1769
1770 * cgen.h (symcat.h): #include it.
1771 (cgen-bitset.h): #include it.
1772 (CGEN_ATTR_VALUE_TYPE): Now a union.
1773 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1774 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1775 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1776 * cgen-bitset.h: New file.
1777
3c9b82ba
NC		 17782005-09-30 Catherine Moore <clm@cm00re.com>
1779
1780 * bfin.h: New file.
1781
6a2375c6
JB		 17822005-10-24 Jan Beulich <jbeulich@novell.com>
1783
1784 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1785 indirect operands.
1786
c06a12f8
DA		 17872005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1788
1789 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1790 Add FLAG_STRICT to pa10 ftest opcode.
1791
4d443107
DA		 17922005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1793
1794 * hppa.h (pa_opcodes): Remove lha entries.
1795
f0a3b40f
DA		 17962005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1797
1798 * hppa.h (FLAG_STRICT): Revise comment.
1799 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1800 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1801 entries for "fdc".
1802
e210c36b
NC		 18032005-09-30 Catherine Moore <clm@cm00re.com>
1804
1805 * bfin.h: New file.
1806
1b7e1362
DA		 18072005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1808
1809 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1810
089b39de
CF		 18112005-09-06 Chao-ying Fu <fu@mips.com>
1812
1813 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1814 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1815 define.
1816 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1817 (INSN_ASE_MASK): Update to include INSN_MT.
1818 (INSN_MT): New define for MT ASE.
1819
93c34b9b
CF		 18202005-08-25 Chao-ying Fu <fu@mips.com>
1821
1822 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1823 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1824 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1825 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1826 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1827 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1828 instructions.
1829 (INSN_DSP): New define for DSP ASE.
1830
848cf006
AM		 18312005-08-18 Alan Modra <amodra@bigpond.net.au>
1832
1833 * a29k.h: Delete.
1834
36ae0db3
DJ		 18352005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1836
1837 * ppc.h (PPC_OPCODE_E300): Define.
1838
8c929562
MS		 18392005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1840
1841 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1842
f7b8cccc
DA		 18432005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1844
1845 PR gas/336
1846 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1847 and pitlb.
1848
8b5328ac
JB		 18492005-07-27 Jan Beulich <jbeulich@novell.com>
1850
1851 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1852 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1853 Add movq-s as 64-bit variants of movd-s.
1854
f417d200
DA		 18552005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1856
18b3bdfc
DA		 1857 * hppa.h: Fix punctuation in comment.
1858
f417d200
DA		 1859 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1860 implicit space-register addressing. Set space-register bits on opcodes
1861 using implicit space-register addressing. Add various missing pa20
1862 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1863 space-register addressing. Use "fE" instead of "fe" in various
1864 fstw opcodes.
1865
9a145ce6
JB		 18662005-07-18 Jan Beulich <jbeulich@novell.com>
1867
1868 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1869
90700ea2
L		 18702007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1871
1872 * i386.h (i386_optab): Support Intel VMX Instructions.
1873
48f130a8
DA		 18742005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1875
1876 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1877
30123838
JB		 18782005-07-05 Jan Beulich <jbeulich@novell.com>
1879
1880 * i386.h (i386_optab): Add new insns.
1881
47b0e7ad
NC		 18822005-07-01 Nick Clifton <nickc@redhat.com>
1883
1884 * sparc.h: Add typedefs to structure declarations.
1885
b300c311
L		 18862005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1887
1888 PR 1013
1889 * i386.h (i386_optab): Update comments for 64bit addressing on
1890 mov. Allow 64bit addressing for mov and movq.
1891
2db495be
DA		 18922005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1893
1894 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1895 respectively, in various floating-point load and store patterns.
1896
caa05036
DA		 18972005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1898
1899 * hppa.h (FLAG_STRICT): Correct comment.
1900 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1901 PA 2.0 mneumonics when equivalent. Entries with cache control
1902 completers now require PA 1.1. Adjust whitespace.
1903
f4411256
AM		 19042005-05-19 Anton Blanchard <anton@samba.org>
1905
1906 * ppc.h (PPC_OPCODE_POWER5): Define.
1907
e172dbf8
NC		 19082005-05-10 Nick Clifton <nickc@redhat.com>
1909
1910 * Update the address and phone number of the FSF organization in
1911 the GPL notices in the following files:
1912 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1913 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1914 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1915 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1916 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1917 tic54x.h, tic80.h, v850.h, vax.h
1918
e44823cf
JB		 19192005-05-09 Jan Beulich <jbeulich@novell.com>
1920
1921 * i386.h (i386_optab): Add ht and hnt.
1922
791fe849
MK		 19232005-04-18 Mark Kettenis <kettenis@gnu.org>
1924
1925 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1926 Add xcrypt-ctr. Provide aliases without hyphens.
1927
faa7ef87
L		 19282005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1929
a63027e5
L		 1930 Moved from ../ChangeLog
1931
faa7ef87
L		 1932 2005-04-12 Paul Brook <paul@codesourcery.com>
1933 * m88k.h: Rename psr macros to avoid conflicts.
1934
1935 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1936 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1937 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1938 and ARM_ARCH_V6ZKT2.
1939
1940 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1941 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1942 Remove redundant instruction types.
1943 (struct argument): X_op - new field.
1944 (struct cst4_entry): Remove.
1945 (no_op_insn): Declare.
1946
1947 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1948 * crx.h (enum argtype): Rename types, remove unused types.
1949
1950 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1951 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1952 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1953 (enum operand_type): Rearrange operands, edit comments.
1954 replace us<N> with ui<N> for unsigned immediate.
1955 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1956 displacements (respectively).
1957 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1958 (instruction type): Add NO_TYPE_INS.
1959 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1960 (operand_entry): New field - 'flags'.
1961 (operand flags): New.
1962
1963 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1964 * crx.h (operand_type): Remove redundant types i3, i4,
1965 i5, i8, i12.
1966 Add new unsigned immediate types us3, us4, us5, us16.
1967
bc4bd9ab
MK		 19682005-04-12 Mark Kettenis <kettenis@gnu.org>
1969
1970 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1971 adjust them accordingly.
1972
373ff435
JB		 19732005-04-01 Jan Beulich <jbeulich@novell.com>
1974
1975 * i386.h (i386_optab): Add rdtscp.
1976
4cc91dba
L		 19772005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1978
1979 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 1980 between memory and segment register. Allow movq for moving between
1981 general-purpose register and segment register.
4cc91dba 1982
9ae09ff9
JB		 19832005-02-09 Jan Beulich <jbeulich@novell.com>
1984
1985 PR gas/707
1986 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1987 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1988 fnstsw.
1989
638e7a64
NS		 19902006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1991
1992 * m68k.h (m68008, m68ec030, m68882): Remove.
1993 (m68k_mask): New.
1994 (cpu_m68k, cpu_cf): New.
1995 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1996 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1997
90219bd0
AO		 19982005-01-25 Alexandre Oliva <aoliva@redhat.com>
1999
2000 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2001 * cgen.h (enum cgen_parse_operand_type): Add
2002 CGEN_PARSE_OPERAND_SYMBOLIC.
2003
239cb185
FF		 20042005-01-21 Fred Fish <fnf@specifixinc.com>
2005
2006 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2007 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2008 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2009
dc9a9f39
FF		 20102005-01-19 Fred Fish <fnf@specifixinc.com>
2011
2012 * mips.h (struct mips_opcode): Add new pinfo2 member.
2013 (INSN_ALIAS): New define for opcode table entries that are
2014 specific instances of another entry, such as 'move' for an 'or'
2015 with a zero operand.
2016 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2017 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2018
98e7aba8
ILT		 20192004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2020
2021 * mips.h (CPU_RM9000): Define.
2022 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2023
37edbb65
JB		 20242004-11-25 Jan Beulich <jbeulich@novell.com>
2025
2026 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2027 to/from test registers are illegal in 64-bit mode. Add missing
2028 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2029 (previously one had to explicitly encode a rex64 prefix). Re-enable
2030 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2031 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2032
20332004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2034
2035 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2036 available only with SSE2. Change the MMX additions introduced by SSE
2037 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2038 instructions by their now designated identifier (since combining i686
2039 and 3DNow! does not really imply 3DNow!A).
2040
f5c7edf4
AM		 20412004-11-19 Alan Modra <amodra@bigpond.net.au>
2042
2043 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2044 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2045
7499d566
NC		 20462004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2047 Vineet Sharma <vineets@noida.hcltech.com>
2048
2049 * maxq.h: New file: Disassembly information for the maxq port.
2050
bcb9eebe
L		 20512004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2052
2053 * i386.h (i386_optab): Put back "movzb".
2054
94bb3d38
HPN		 20552004-11-04 Hans-Peter Nilsson <hp@axis.com>
2056
2057 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2058 comments. Remove member cris_ver_sim. Add members
2059 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2060 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2061 (struct cris_support_reg, struct cris_cond15): New types.
2062 (cris_conds15): Declare.
2063 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2064 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2065 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2066 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2067 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2068 SIZE_FIELD_UNSIGNED.
2069
37edbb65 20702004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2071
2072 * i386.h (sldx_Suf): Remove.
2073 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2074 (q_FP): Define, implying no REX64.
2075 (x_FP, sl_FP): Imply FloatMF.
2076 (i386_optab): Split reg and mem forms of moving from segment registers
2077 so that the memory forms can ignore the 16-/32-bit operand size
2078 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2079 all non-floating-point instructions. Unite 32- and 64-bit forms of
2080 movsx, movzx, and movd. Adjust floating point operations for the above
2081 changes to the *FP macros. Add DefaultSize to floating point control
2082 insns operating on larger memory ranges. Remove left over comments
2083 hinting at certain insns being Intel-syntax ones where the ones
2084 actually meant are already gone.
2085
48c9f030
NC		 20862004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2087
2088 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2089 instruction type.
2090
0dd132b6
NC		 20912004-09-30 Paul Brook <paul@codesourcery.com>
2092
2093 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2094 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2095
23794b24
MM		 20962004-09-11 Theodore A. Roth <troth@openavr.org>
2097
2098 * avr.h: Add support for
2099 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2100
2a309db0
AM		 21012004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2102
2103 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2104
b18c562e
NC		 21052004-08-24 Dmitry Diky <diwil@spec.ru>
2106
2107 * msp430.h (msp430_opc): Add new instructions.
2108 (msp430_rcodes): Declare new instructions.
2109 (msp430_hcodes): Likewise..
2110
45d313cd
NC		 21112004-08-13 Nick Clifton <nickc@redhat.com>
2112
2113 PR/301
2114 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2115 processors.
2116
30d1c836
ML		 21172004-08-30 Michal Ludvig <mludvig@suse.cz>
2118
2119 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2120
9a45f1c2
L		 21212004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2122
2123 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2124
543613e9
NC		 21252004-07-21 Jan Beulich <jbeulich@novell.com>
2126
2127 * i386.h: Adjust instruction descriptions to better match the
2128 specification.
2129
b781e558
RE		 21302004-07-16 Richard Earnshaw <rearnsha@arm.com>
2131
2132 * arm.h: Remove all old content. Replace with architecture defines
2133 from gas/config/tc-arm.c.
2134
8577e690
AS		 21352004-07-09 Andreas Schwab <schwab@suse.de>
2136
2137 * m68k.h: Fix comment.
2138
1fe1f39c
NC		 21392004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2140
2141 * crx.h: New file.
2142
1d9f512f
AM		 21432004-06-24 Alan Modra <amodra@bigpond.net.au>
2144
2145 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2146
be8c092b
NC		 21472004-05-24 Peter Barada <peter@the-baradas.com>
2148
2149 * m68k.h: Add 'size' to m68k_opcode.
2150
6b6e92f4
NC		 21512004-05-05 Peter Barada <peter@the-baradas.com>
2152
2153 * m68k.h: Switch from ColdFire chip name to core variant.
2154
21552004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2156
2157 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2158 descriptions for new EMAC cases.
2159 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2160 handle Motorola MAC syntax.
2161 Allow disassembly of ColdFire V4e object files.
2162
fdd12ef3
AM		 21632004-03-16 Alan Modra <amodra@bigpond.net.au>
2164
2165 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2166
3922a64c
L		 21672004-03-12 Jakub Jelinek <jakub@redhat.com>
2168
2169 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2170
1f45d988
ML		 21712004-03-12 Michal Ludvig <mludvig@suse.cz>
2172
2173 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2174
0f10071e
ML		 21752004-03-12 Michal Ludvig <mludvig@suse.cz>
2176
2177 * i386.h (i386_optab): Added xstore/xcrypt insns.
2178
3255318a
NC		 21792004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2180
2181 * h8300.h (32bit ldc/stc): Add relaxing support.
2182
ca9a79a1 21832004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2184
ca9a79a1
NC		 2185 * h8300.h (BITOP): Pass MEMRELAX flag.
2186
875a0b14
NC		 21872004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2188
2189 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2190 except for the H8S.
252b5132 2191
c9e214e5 2192For older changes see ChangeLog-9103
252b5132 2193\f
b90efa5b 2194Copyright (C) 2004-2015 Free Software Foundation, Inc.
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2196Copying and distribution of this file, with or without modification,
2197are permitted in any medium without royalty provided the copyright
2198notice and this notice are preserved.
2199
252b5132 2200Local Variables:
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2202left-margin: 8
2203fill-column: 74
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GDB Binutils - Deliverables
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