projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Fix an issue with "Rearrange MIPS INSN* masks" patch.
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
3efe9ec5
RS		 12014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
2
3 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
4
73589c9d
CS		 52014-04-22 Christian Svensson <blue@cmd.nu>
6
7 * or32.h: Delete.
8
4b95cf5c
AM		 92014-03-05 Alan Modra <amodra@gmail.com>
10
11 Update copyright years.
12
e269fea7
AB		 132013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
14
15 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
16 microMIPS.
17
35c08157
KLC		 182013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
19 Wei-Cheng Wang <cole945@gmail.com>
20
21 * nds32.h: New file for Andes NDS32.
22
594d8fa8
MF		 232013-12-07 Mike Frysinger <vapier@gentoo.org>
24
25 * bfin.h: Remove +x file mode.
26
87b8eed7
YZ		 272013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
28
29 * aarch64.h (aarch64_pstatefields): Change element type to
30 aarch64_sys_reg.
31
c9fb6e58
YZ		 322013-11-18 Renlin Li <Renlin.Li@arm.com>
33
34 * arm.h (ARM_AEXT_V7VE): New define.
35 (ARM_ARCH_V7VE): New define.
36 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
37
a203d9b7
YZ		 382013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
39
40 Revert
41
42 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
43
44 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
45 (aarch64_sys_reg_writeonly_p): Ditto.
46
75468c93
YZ		 472013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
48
49 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
50 (aarch64_sys_reg_writeonly_p): Ditto.
51
49eec193
YZ		 522013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
53
54 * aarch64.h (aarch64_sys_reg): New typedef.
55 (aarch64_sys_regs): Change to define with the new type.
56 (aarch64_sys_reg_deprecated_p): Declare.
57
68a64283
YZ		 582013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
59
60 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
61 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
62
387a82f1
CF		 632013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
64
65 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
66 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
67 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
68 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
69 For MIPS, update extension character sequences after +.
70 (ASE_MSA): New define.
71 (ASE_MSA64): New define.
72 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
73 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
74 For microMIPS, update extension character sequences after +.
75
9aff4b7a
NC		 762013-08-23 Yuri Chornoivan <yurchor@ukr.net>
77
78 PR binutils/15834
79 * i960.h: Fix typos.
80
e423441d
RS		 812013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
82
83 * mips.h: Remove references to "+I" and imm2_expr.
84
5e0dc5ba
RS		 852013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
86
87 * mips.h (M_DEXT, M_DINS): Delete.
88
0f35dbc4
RS		 892013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
90
91 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
92 (mips_optional_operand_p): New function.
93
14daeee3
RS		 942013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
95 Richard Sandiford <rdsandiford@googlemail.com>
96
97 * mips.h: Document new VU0 operand characters.
98 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
99 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
100 (OP_REG_R5900_ACC): New mips_reg_operand_types.
101 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
102 (mips_vu0_channel_mask): Declare.
103
3ccad066
RS		 1042013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
105
106 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
107 (mips_int_operand_min, mips_int_operand_max): New functions.
108 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
109
fc76e730
RS		 1102013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
111
112 * mips.h (mips_decode_reg_operand): New function.
113 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
114 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
115 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
116 New macros.
117 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
118 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
119 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
120 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
121 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
122 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
123 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
124 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
125 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
126 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
127 macros to cover the gaps.
128 (INSN2_MOD_SP): Replace with...
129 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
130 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
131 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
132 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
133 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
134 Delete.
135
26545944
RS		 1362013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
137
138 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
139 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
140 (MIPS16_INSN_COND_BRANCH): Delete.
141
7e8b059b
L		 1422013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
143 Kirill Yukhin <kirill.yukhin@intel.com>
144 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
145
146 * i386.h (BND_PREFIX_OPCODE): New.
147
c3c07478
RS		 1482013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
149
150 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
151 OP_SAVE_RESTORE_LIST.
152 (decode_mips16_operand): Declare.
153
ab902481
RS		 1542013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
155
156 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
157 (mips_operand, mips_int_operand, mips_mapped_int_operand)
158 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
159 (mips_pcrel_operand): New structures.
160 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
161 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
162 (decode_mips_operand, decode_micromips_operand): Declare.
163
cc537e56
RS		 1642013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
165
166 * mips.h: Document MIPS16 "I" opcode.
167
f2ae14a1
RS		 1682013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
169
170 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
171 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
172 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
173 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
174 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
175 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
176 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
177 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
178 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
179 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
180 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
181 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
182 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
183 Rename to...
184 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
185 (M_USD_AB): ...these.
186
5c324c16
RS		 1872013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
188
189 * mips.h: Remove documentation of "[" and "]". Update documentation
190 of "k" and the MDMX formats.
191
23e69e47
RS		 1922013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
193
194 * mips.h: Update documentation of "+s" and "+S".
195
27c5c572
RS		 1962013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
197
198 * mips.h: Document "+i".
199
e76ff5ab
RS		 2002013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
201
202 * mips.h: Remove "mi" documentation. Update "mh" documentation.
203 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
204 Delete.
205 (INSN2_WRITE_GPR_MHI): Rename to...
206 (INSN2_WRITE_GPR_MH): ...this.
207
fa7616a4
RS		 2082013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
209
210 * mips.h: Remove documentation of "+D" and "+T".
211
18870af7
RS		 2122013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
213
214 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
215 Use "source" rather than "destination" for microMIPS "G".
216
833794fc
MR		 2172013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
218
219 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
220 values.
221
c3678916
RS		 2222013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
223
224 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
225
7f3c4072
CM		 2262013-06-17 Catherine Moore <clm@codesourcery.com>
227 Maciej W. Rozycki <macro@codesourcery.com>
228 Chao-Ying Fu <fu@mips.com>
229
230 * mips.h (OP_SH_EVAOFFSET): Define.
231 (OP_MASK_EVAOFFSET): Define.
232 (INSN_ASE_MASK): Delete.
233 (ASE_EVA): Define.
234 (M_CACHEE_AB, M_CACHEE_OB): New.
235 (M_LBE_OB, M_LBE_AB): New.
236 (M_LBUE_OB, M_LBUE_AB): New.
237 (M_LHE_OB, M_LHE_AB): New.
238 (M_LHUE_OB, M_LHUE_AB): New.
239 (M_LLE_AB, M_LLE_OB): New.
240 (M_LWE_OB, M_LWE_AB): New.
241 (M_LWLE_AB, M_LWLE_OB): New.
242 (M_LWRE_AB, M_LWRE_OB): New.
243 (M_PREFE_AB, M_PREFE_OB): New.
244 (M_SCE_AB, M_SCE_OB): New.
245 (M_SBE_OB, M_SBE_AB): New.
246 (M_SHE_OB, M_SHE_AB): New.
247 (M_SWE_OB, M_SWE_AB): New.
248 (M_SWLE_AB, M_SWLE_OB): New.
249 (M_SWRE_AB, M_SWRE_OB): New.
250 (MICROMIPSOP_SH_EVAOFFSET): Define.
251 (MICROMIPSOP_MASK_EVAOFFSET): Define.
252
0c8fe7cf
SL		 2532013-06-12 Sandra Loosemore <sandra@codesourcery.com>
254
255 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
256
c77c0862
RS		 2572013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
258
259 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
260
b015e599
AP		 2612013-05-09 Andrew Pinski <apinski@cavium.com>
262
263 * mips.h (OP_MASK_CODE10): Correct definition.
264 (OP_SH_CODE10): Likewise.
265 Add a comment that "+J" is used now for OP_*CODE10.
266 (INSN_ASE_MASK): Update.
267 (INSN_VIRT): New macro.
268 (INSN_VIRT64): New macro
269
13761a11
NC		 2702013-05-02 Nick Clifton <nickc@redhat.com>
271
272 * msp430.h: Add patterns for MSP430X instructions.
273
0afd1215
DM		 2742013-04-06 David S. Miller <davem@davemloft.net>
275
276 * sparc.h (F_PREFERRED): Define.
277 (F_PREF_ALIAS): Define.
278
41702d50
NC		 2792013-04-03 Nick Clifton <nickc@redhat.com>
280
281 * v850.h (V850_INVERSE_PCREL): Define.
282
e21e1a51
NC		 2832013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
284
285 PR binutils/15068
286 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
287
51dcdd4d
NC		 2882013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
289
290 PR binutils/15068
291 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
292 Add 16-bit opcodes.
293 * tic6xc-opcode-table.h: Add 16-bit insns.
294 * tic6x.h: Add support for 16-bit insns.
295
81f5558e
NC		 2962013-03-21 Michael Schewe <michael.schewe@gmx.net>
297
298 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
299 and mov.b/w/l Rs,@(d:32,ERd).
300
165546ad
NC		 3012013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
302
303 PR gas/15082
304 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
305 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
306 tic6x_operand_xregpair operand coding type.
307 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
308 opcode field, usu ORXREGD1324 for the src2 operand and remove the
309 TIC6X_FLAG_NO_CROSS.
310
795b8e6b
NC		 3112013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
312
313 PR gas/15095
314 * tic6x.h (enum tic6x_coding_method): Add
315 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
316 separately the msb and lsb of a register pair. This is needed to
317 encode the opcodes in the same way as TI assembler does.
318 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
319 and rsqrdp opcodes to use the new field coding types.
320
dd5181d5
KT		 3212013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
322
323 * arm.h (CRC_EXT_ARMV8): New constant.
324 (ARCH_CRC_ARMV8): New macro.
325
e60bb1dd
YZ		 3262013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
327
328 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
329
36591ba1
SL		 3302013-02-06 Sandra Loosemore <sandra@codesourcery.com>
331 Andrew Jenner <andrew@codesourcery.com>
332
333 Based on patches from Altera Corporation.
334
335 * nios2.h: New file.
336
e30181a5
YZ		 3372013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
338
339 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
340
0c9573f4
NC		 3412013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
342
343 PR gas/15069
344 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
345
981dc7f1
NC		 3462013-01-24 Nick Clifton <nickc@redhat.com>
347
348 * v850.h: Add e3v5 support.
349
f5555712
YZ		 3502013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
351
352 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
353
5817ffd1
PB		 3542013-01-10 Peter Bergner <bergner@vnet.ibm.com>
355
356 * ppc.h (PPC_OPCODE_POWER8): New define.
357 (PPC_OPCODE_HTM): Likewise.
358
a3c62988
NC		 3592013-01-10 Will Newton <will.newton@imgtec.com>
360
361 * metag.h: New file.
362
73335eae
NC		 3632013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
364
365 * cr16.h (make_instruction): Rename to cr16_make_instruction.
366 (match_opcode): Rename to cr16_match_opcode.
367
e407c74b
NC		 3682013-01-04 Juergen Urban <JuergenUrban@gmx.de>
369
370 * mips.h: Add support for r5900 instructions including lq and sq.
371
bab4becb
NC		 3722013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
373
374 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
375 (make_instruction,match_opcode): Added function prototypes.
376 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
377
776fc418
AM		 3782012-11-23 Alan Modra <amodra@gmail.com>
379
380 * ppc.h (ppc_parse_cpu): Update prototype.
381
f05682d4
DA		 3822012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
383
384 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
385 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
386
cfc72779
AK		 3872012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
388
389 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
390
b3e14eda
L		 3912012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
392
393 * ia64.h (ia64_opnd): Add new operand types.
394
2c63854f
DM		 3952012-08-21 David S. Miller <davem@davemloft.net>
396
397 * sparc.h (F3F4): New macro.
398
a06ea964 3992012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 400 Laurent Desnogues <laurent.desnogues@arm.com>
401 Jim MacArthur <jim.macarthur@arm.com>
402 Marcus Shawcroft <marcus.shawcroft@arm.com>
403 Nigel Stephens <nigel.stephens@arm.com>
404 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
405 Richard Earnshaw <rearnsha@arm.com>
406 Sofiane Naci <sofiane.naci@arm.com>
407 Tejas Belagod <tejas.belagod@arm.com>
408 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 409
410 * aarch64.h: New file.
411
35d0a169 4122012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 413 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 414
415 * mips.h (mips_opcode): Add the exclusions field.
416 (OPCODE_IS_MEMBER): Remove macro.
417 (cpu_is_member): New inline function.
418 (opcode_is_member): Likewise.
419
03f66e8a 4202012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 421 Catherine Moore <clm@codesourcery.com>
422 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 423
424 * mips.h: Document microMIPS DSP ASE usage.
425 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
426 microMIPS DSP ASE support.
427 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
428 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
429 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
430 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
431 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
432 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
433 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
434
9d7b4c23
MR		 4352012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
436
437 * mips.h: Fix a typo in description.
438
76e879f8
NC		 4392012-06-07 Georg-Johann Lay <avr@gjlay.de>
440
441 * avr.h: (AVR_ISA_XCH): New define.
442 (AVR_ISA_XMEGA): Use it.
443 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
444
6927f982
NC		 4452012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
446
447 * m68hc11.h: Add XGate definitions.
448 (struct m68hc11_opcode): Add xg_mask field.
449
b9c361e0
JL		 4502012-05-14 Catherine Moore <clm@codesourcery.com>
451 Maciej W. Rozycki <macro@codesourcery.com>
452 Rhonda Wittels <rhonda@codesourcery.com>
453
6927f982 454 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 455 (PPC_OP_SA): New macro.
456 (PPC_OP_SE_VLE): New macro.
457 (PPC_OP): Use a variable shift amount.
458 (powerpc_operand): Update comments.
459 (PPC_OPSHIFT_INV): New macro.
460 (PPC_OPERAND_CR): Replace with...
461 (PPC_OPERAND_CR_BIT): ...this and
462 (PPC_OPERAND_CR_REG): ...this.
463
464
f6c1a2d5
NC		 4652012-05-03 Sean Keys <skeys@ipdatasys.com>
466
467 * xgate.h: Header file for XGATE assembler.
468
ec668d69
DM		 4692012-04-27 David S. Miller <davem@davemloft.net>
470
6cda1326
DM		 471 * sparc.h: Document new arg code' )' for crypto RS3
472 immediates.
473
ec668d69
DM		 474 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
475 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
476 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
477 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
478 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
479 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
480 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
481 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
482 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
483 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
484 HWCAP_CBCOND, HWCAP_CRC32): New defines.
485
aea77599
AM		 4862012-03-10 Edmar Wienskoski <edmar@freescale.com>
487
488 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
489
1f42f8b3
AM		 4902012-02-27 Alan Modra <amodra@gmail.com>
491
492 * crx.h (cst4_map): Update declaration.
493
6f7be959
WL		 4942012-02-25 Walter Lee <walt@tilera.com>
495
496 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
497 TILEGX_OPC_LD_TLS.
498 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
499 TILEPRO_OPC_LW_TLS_SN.
500
42164a71
L		 5012012-02-08 H.J. Lu <hongjiu.lu@intel.com>
502
503 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
504 (XRELEASE_PREFIX_OPCODE): Likewise.
505
432233b3 5062011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 507 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 508
509 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
510 (INSN_OCTEON2): New macro.
511 (CPU_OCTEON2): New macro.
512 (OPCODE_IS_MEMBER): Add Octeon2.
513
dd6a37e7
AP		 5142011-11-29 Andrew Pinski <apinski@cavium.com>
515
516 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
517 (INSN_OCTEONP): New macro.
518 (CPU_OCTEONP): New macro.
519 (OPCODE_IS_MEMBER): Add Octeon+.
520 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
521
99c513f6
DD		 5222011-11-01 DJ Delorie <dj@redhat.com>
523
524 * rl78.h: New file.
525
26f85d7a
MR		 5262011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
527
528 * mips.h: Fix a typo in description.
529
9e8c70f9
DM		 5302011-09-21 David S. Miller <davem@davemloft.net>
531
532 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
533 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
534 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
535 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
536
dec0624d 5372011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 538 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 539
540 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
541 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
542 (INSN_ASE_MASK): Add the MCU bit.
543 (INSN_MCU): New macro.
544 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
545 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
546
2b0c8b40
MR		 5472011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
548
549 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
550 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
551 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
552 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
553 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
554 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
555 (INSN2_READ_GPR_MMN): Likewise.
556 (INSN2_READ_FPR_D): Change the bit used.
557 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
558 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
559 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
560 (INSN2_COND_BRANCH): Likewise.
561 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
562 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
563 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
564 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
565 (INSN2_MOD_GPR_MN): Likewise.
566
ea783ef3
DM		 5672011-08-05 David S. Miller <davem@davemloft.net>
568
569 * sparc.h: Document new format codes '4', '5', and '('.
570 (OPF_LOW4, RS3): New macros.
571
7c176fa8
MR		 5722011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
573
574 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
575 order of flags documented.
576
2309ddf2
MR		 5772011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
578
579 * mips.h: Clarify the description of microMIPS instruction
580 manipulation macros.
581 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
582
df58fc94 5832011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 584 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 585
586 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
587 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
588 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
589 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
590 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
591 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
592 (OP_MASK_RS3, OP_SH_RS3): Likewise.
593 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
594 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
595 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
596 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
597 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
598 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
599 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
600 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
601 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
602 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
603 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
604 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
605 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
606 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
607 (INSN_WRITE_GPR_S): New macro.
608 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
609 (INSN2_READ_FPR_D): Likewise.
610 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
611 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
612 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
613 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
614 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
615 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
616 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
617 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
618 (CPU_MICROMIPS): New macro.
619 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
620 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
621 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
622 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
623 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
624 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
625 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
626 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
627 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
628 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
629 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
630 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
631 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
632 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
633 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
634 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
635 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
636 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
637 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
638 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
639 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
640 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
641 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
642 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
643 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
644 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
645 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
646 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
647 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
648 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
649 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
650 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
651 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
652 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
653 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
654 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
655 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
656 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
657 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
658 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
659 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
660 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
661 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
662 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
663 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
664 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
665 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
666 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
667 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
668 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
669 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
670 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
671 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
672 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
673 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
674 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
675 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
676 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
677 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
678 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
679 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
680 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
681 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
682 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
683 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
684 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
685 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
686 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
687 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
688 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
689 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
690 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
691 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
692 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
693 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
694 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
695 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
696 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
697 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
698 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
699 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
700 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
701 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
702 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
703 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
704 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
705 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
706 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
707 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
708 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
709 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
710 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
711 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
712 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
713 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
714 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
715 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
716 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
717 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
718 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
719 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
720 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
721 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
722 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
723 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
724 (micromips_opcodes): New declaration.
725 (bfd_micromips_num_opcodes): Likewise.
726
bcd530a7
RS		 7272011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
728
729 * mips.h (INSN_TRAP): Rename to...
730 (INSN_NO_DELAY_SLOT): ... this.
731 (INSN_SYNC): Remove macro.
732
2dad5a91
EW		 7332011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
734
735 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
736 a duplicate of AVR_ISA_SPM.
737
5d73b1f1
NC		 7382011-07-01 Nick Clifton <nickc@redhat.com>
739
740 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
741
ef26d60e
MF		 7422011-06-18 Robin Getz <robin.getz@analog.com>
743
744 * bfin.h (is_macmod_signed): New func
745
8fb8dca7
MF		 7462011-06-18 Mike Frysinger <vapier@gentoo.org>
747
748 * bfin.h (is_macmod_pmove): Add missing space before func args.
749 (is_macmod_hmove): Likewise.
750
aa137e4d
NC		 7512011-06-13 Walter Lee <walt@tilera.com>
752
753 * tilegx.h: New file.
754 * tilepro.h: New file.
755
3b2f0793
PB		 7562011-05-31 Paul Brook <paul@codesourcery.com>
757
aa137e4d
NC		 758 * arm.h (ARM_ARCH_V7R_IDIV): Define.
759
7602011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
761
762 * s390.h: Replace S390_OPERAND_REG_EVEN with
763 S390_OPERAND_REG_PAIR.
764
7652011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
766
767 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 768
ac7f631b
NC		 7692011-04-18 Julian Brown <julian@codesourcery.com>
770
771 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
772
84701018
NC		 7732011-04-11 Dan McDonald <dan@wellkeeper.com>
774
775 PR gas/12296
776 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
777
8cc66334
EW		 7782011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
779
780 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
781 New instruction set flags.
782 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
783
3eebd5eb
MR		 7842011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
785
786 * mips.h (M_PREF_AB): New enum value.
787
26bb3ddd
MF		 7882011-02-12 Mike Frysinger <vapier@gentoo.org>
789
89c0d58c
MR		 790 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
791 M_IU): Define.
792 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 793
dd76fcb8
MF		 7942011-02-11 Mike Frysinger <vapier@gentoo.org>
795
796 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
797
98d23bef
BS		 7982011-02-04 Bernd Schmidt <bernds@codesourcery.com>
799
800 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
801 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
802
3c853d93
DA		 8032010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
804
805 PR gas/11395
806 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
807 "bb" entries.
808
79676006
DA		 8092010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
810
811 PR gas/11395
812 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
813
1bec78e9
RS		 8142010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
815
816 * mips.h: Update commentary after last commit.
817
98675402
RS		 8182010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
819
820 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
821 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
822 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
823
aa137e4d
NC		 8242010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
825
826 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
827
435b94a4
RS		 8282010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
829
830 * mips.h: Fix previous commit.
831
d051516a
NC		 8322010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
833
834 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
835 (INSN_LOONGSON_3A): Clear bit 31.
836
251665fc
MGD		 8372010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
838
839 PR gas/12198
840 * arm.h (ARM_AEXT_V6M_ONLY): New define.
841 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
842 (ARM_ARCH_V6M_ONLY): New define.
843
fd503541
NC		 8442010-11-11 Mingming Sun <mingm.sun@gmail.com>
845
846 * mips.h (INSN_LOONGSON_3A): Defined.
847 (CPU_LOONGSON_3A): Defined.
848 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
849
4469d2be
AM		 8502010-10-09 Matt Rice <ratmice@gmail.com>
851
852 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
853 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
854
90ec0d68
MGD		 8552010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
856
857 * arm.h (ARM_EXT_VIRT): New define.
858 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
859 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
860 Extensions.
861
eea54501 8622010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 863
eea54501
MGD		 864 * arm.h (ARM_AEXT_ADIV): New define.
865 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
866
b2a5fbdc
MGD		 8672010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
868
869 * arm.h (ARM_EXT_OS): New define.
870 (ARM_AEXT_V6SM): Likewise.
871 (ARM_ARCH_V6SM): Likewise.
872
60e5ef9f
MGD		 8732010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
874
875 * arm.h (ARM_EXT_MP): Add.
876 (ARM_ARCH_V7A_MP): Likewise.
877
73a63ccf
MF		 8782010-09-22 Mike Frysinger <vapier@gentoo.org>
879
880 * bfin.h: Declare pseudoChr structs/defines.
881
ee99860a
MF		 8822010-09-21 Mike Frysinger <vapier@gentoo.org>
883
884 * bfin.h: Strip trailing whitespace.
885
f9c7014e
DD		 8862010-07-29 DJ Delorie <dj@redhat.com>
887
888 * rx.h (RX_Operand_Type): Add TwoReg.
889 (RX_Opcode_ID): Remove ediv and ediv2.
890
93378652
DD		 8912010-07-27 DJ Delorie <dj@redhat.com>
892
893 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
894
1cd986c5
NC		 8952010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
896 Ina Pandit <ina.pandit@kpitcummins.com>
897
898 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
899 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
900 PROCESSOR_V850E2_ALL.
901 Remove PROCESSOR_V850EA support.
902 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
903 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
904 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
905 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
906 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
907 V850_OPERAND_PERCENT.
908 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
909 V850_NOT_R0.
910 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
911 and V850E_PUSH_POP
912
9a2c7088
MR		 9132010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
914
915 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
916 (MIPS16_INSN_BRANCH): Rename to...
917 (MIPS16_INSN_COND_BRANCH): ... this.
918
bdc70b4a
AM		 9192010-07-03 Alan Modra <amodra@gmail.com>
920
921 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
922 Renumber other PPC_OPCODE defines.
923
f2bae120
AM		 9242010-07-03 Alan Modra <amodra@gmail.com>
925
926 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
927
360cfc9c
AM		 9282010-06-29 Alan Modra <amodra@gmail.com>
929
930 * maxq.h: Delete file.
931
e01d869a
AM		 9322010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
933
934 * ppc.h (PPC_OPCODE_E500): Define.
935
f79e2745
CM		 9362010-05-26 Catherine Moore <clm@codesourcery.com>
937
938 * opcode/mips.h (INSN_MIPS16): Remove.
939
2462afa1
JM		 9402010-04-21 Joseph Myers <joseph@codesourcery.com>
941
942 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
943
e4e42b45
NC		 9442010-04-15 Nick Clifton <nickc@redhat.com>
945
946 * alpha.h: Update copyright notice to use GPLv3.
947 * arc.h: Likewise.
948 * arm.h: Likewise.
949 * avr.h: Likewise.
950 * bfin.h: Likewise.
951 * cgen.h: Likewise.
952 * convex.h: Likewise.
953 * cr16.h: Likewise.
954 * cris.h: Likewise.
955 * crx.h: Likewise.
956 * d10v.h: Likewise.
957 * d30v.h: Likewise.
958 * dlx.h: Likewise.
959 * h8300.h: Likewise.
960 * hppa.h: Likewise.
961 * i370.h: Likewise.
962 * i386.h: Likewise.
963 * i860.h: Likewise.
964 * i960.h: Likewise.
965 * ia64.h: Likewise.
966 * m68hc11.h: Likewise.
967 * m68k.h: Likewise.
968 * m88k.h: Likewise.
969 * maxq.h: Likewise.
970 * mips.h: Likewise.
971 * mmix.h: Likewise.
972 * mn10200.h: Likewise.
973 * mn10300.h: Likewise.
974 * msp430.h: Likewise.
975 * np1.h: Likewise.
976 * ns32k.h: Likewise.
977 * or32.h: Likewise.
978 * pdp11.h: Likewise.
979 * pj.h: Likewise.
980 * pn.h: Likewise.
981 * ppc.h: Likewise.
982 * pyr.h: Likewise.
983 * rx.h: Likewise.
984 * s390.h: Likewise.
985 * score-datadep.h: Likewise.
986 * score-inst.h: Likewise.
987 * sparc.h: Likewise.
988 * spu-insns.h: Likewise.
989 * spu.h: Likewise.
990 * tic30.h: Likewise.
991 * tic4x.h: Likewise.
992 * tic54x.h: Likewise.
993 * tic80.h: Likewise.
994 * v850.h: Likewise.
995 * vax.h: Likewise.
996
40b36596
JM		 9972010-03-25 Joseph Myers <joseph@codesourcery.com>
998
999 * tic6x-control-registers.h, tic6x-insn-formats.h,
1000 tic6x-opcode-table.h, tic6x.h: New.
1001
c67a084a
NC		 10022010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1003
1004 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1005
466ef64f
AM		 10062010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1007
1008 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1009
1319d143
L		 10102010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1011
1012 * ia64.h (ia64_find_opcode): Remove argument name.
1013 (ia64_find_next_opcode): Likewise.
1014 (ia64_dis_opcode): Likewise.
1015 (ia64_free_opcode): Likewise.
1016 (ia64_find_dependency): Likewise.
1017
1fbb9298
DE		 10182009-11-22 Doug Evans <dje@sebabeach.org>
1019
1020 * cgen.h: Include bfd_stdint.h.
1021 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1022
ada65aa3
PB		 10232009-11-18 Paul Brook <paul@codesourcery.com>
1024
1025 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1026
9e3c6df6
PB		 10272009-11-17 Paul Brook <paul@codesourcery.com>
1028 Daniel Jacobowitz <dan@codesourcery.com>
1029
1030 * arm.h (ARM_EXT_V6_DSP): Define.
1031 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1032 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1033
0d734b5d
DD		 10342009-11-04 DJ Delorie <dj@redhat.com>
1035
1036 * rx.h (rx_decode_opcode) (mvtipl): Add.
1037 (mvtcp, mvfcp, opecp): Remove.
1038
62f3b8c8
PB		 10392009-11-02 Paul Brook <paul@codesourcery.com>
1040
1041 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1042 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1043 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1044 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1045 FPU_ARCH_NEON_VFP_V4): Define.
1046
ac1e9eca
DE		 10472009-10-23 Doug Evans <dje@sebabeach.org>
1048
1049 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1050 * cgen.h: Update. Improve multi-inclusion macro name.
1051
9fe54b1c
PB		 10522009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1053
1054 * ppc.h (PPC_OPCODE_476): Define.
1055
634b50f2
PB		 10562009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1057
1058 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1059
c7927a3c
NC		 10602009-09-29 DJ Delorie <dj@redhat.com>
1061
1062 * rx.h: New file.
1063
b961e85b
AM		 10642009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1065
1066 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1067
e0d602ec
BE		 10682009-09-21 Ben Elliston <bje@au.ibm.com>
1069
1070 * ppc.h (PPC_OPCODE_PPCA2): New.
1071
96d56e9f
NC		 10722009-09-05 Martin Thuresson <martin@mtme.org>
1073
1074 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1075
d3ce72d0
NC		 10762009-08-29 Martin Thuresson <martin@mtme.org>
1077
1078 * tic30.h (template): Rename type template to
1079 insn_template. Updated code to use new name.
1080 * tic54x.h (template): Rename type template to
1081 insn_template.
1082
824b28db
NH		 10832009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1084
1085 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1086
f865a31d
AG		 10872009-06-11 Anthony Green <green@moxielogic.com>
1088
1089 * moxie.h (MOXIE_F3_PCREL): Define.
1090 (moxie_form3_opc_info): Grow.
1091
0e7c7f11
AG		 10922009-06-06 Anthony Green <green@moxielogic.com>
1093
1094 * moxie.h (MOXIE_F1_M): Define.
1095
20135e4c
NC		 10962009-04-15 Anthony Green <green@moxielogic.com>
1097
1098 * moxie.h: Created.
1099
bcb012d3
DD		 11002009-04-06 DJ Delorie <dj@redhat.com>
1101
1102 * h8300.h: Add relaxation attributes to MOVA opcodes.
1103
69fe9ce5
AM		 11042009-03-10 Alan Modra <amodra@bigpond.net.au>
1105
1106 * ppc.h (ppc_parse_cpu): Declare.
1107
c3b7224a
NC		 11082009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1109
1110 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1111 and _IMM11 for mbitclr and mbitset.
1112 * score-datadep.h: Update dependency information.
1113
066be9f7
PB		 11142009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1115
1116 * ppc.h (PPC_OPCODE_POWER7): New.
1117
fedc618e
DE		 11182009-02-06 Doug Evans <dje@google.com>
1119
1120 * i386.h: Add comment regarding sse* insns and prefixes.
1121
52b6b6b9
JM		 11222009-02-03 Sandip Matte <sandip@rmicorp.com>
1123
1124 * mips.h (INSN_XLR): Define.
1125 (INSN_CHIP_MASK): Update.
1126 (CPU_XLR): Define.
1127 (OPCODE_IS_MEMBER): Update.
1128 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1129
35669430
DE		 11302009-01-28 Doug Evans <dje@google.com>
1131
1132 * opcode/i386.h: Add multiple inclusion protection.
1133 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1134 (EDI_REG_NUM): New macros.
1135 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1136 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1137 (REX_PREFIX_P): New macro.
35669430 1138
1cb0a767
PB		 11392009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1140
1141 * ppc.h (struct powerpc_opcode): New field "deprecated".
1142 (PPC_OPCODE_NOPOWER4): Delete.
1143
3aa3176b
TS		 11442008-11-28 Joshua Kinard <kumba@gentoo.org>
1145
1146 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1147 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1148
8e79c3df
CM		 11492008-11-18 Catherine Moore <clm@codesourcery.com>
1150
1151 * arm.h (FPU_NEON_FP16): New.
1152 (FPU_ARCH_NEON_FP16): New.
1153
de9a3e51
CF		 11542008-11-06 Chao-ying Fu <fu@mips.com>
1155
1156 * mips.h: Doucument '1' for 5-bit sync type.
1157
1ca35711
L		 11582008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1159
1160 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1161 IA64_RS_CR.
1162
9b4e5766
PB		 11632008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1164
1165 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1166
081ba1b3
AM		 11672008-07-30 Michael J. Eager <eager@eagercon.com>
1168
1169 * ppc.h (PPC_OPCODE_405): Define.
1170 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1171
fa452fa6
PB		 11722008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1173
1174 * ppc.h (ppc_cpu_t): New typedef.
1175 (struct powerpc_opcode <flags>): Use it.
1176 (struct powerpc_operand <insert, extract>): Likewise.
1177 (struct powerpc_macro <flags>): Likewise.
1178
bb35fb24
NC		 11792008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1180
1181 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1182 Update comment before MIPS16 field descriptors to mention MIPS16.
1183 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1184 BBIT.
1185 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1186 New bit masks and shift counts for cins and exts.
1187
dd3cbb7e
NC		 1188 * mips.h: Document new field descriptors +Q.
1189 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1190
d0799671
AN		 11912008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1192
9aff4b7a 1193 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1194 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1195
19a6653c
AM		 11962008-04-14 Edmar Wienskoski <edmar@freescale.com>
1197
1198 * ppc.h: (PPC_OPCODE_E500MC): New.
1199
c0f3af97
L		 12002008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1201
1202 * i386.h (MAX_OPERANDS): Set to 5.
1203 (MAX_MNEM_SIZE): Changed to 20.
1204
e210c36b
NC		 12052008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1206
1207 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1208
b1cc4aeb
PB		 12092008-03-09 Paul Brook <paul@codesourcery.com>
1210
1211 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1212
7e806470
PB		 12132008-03-04 Paul Brook <paul@codesourcery.com>
1214
1215 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1216 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1217 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1218
7b2185f9 12192008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1220 Nick Clifton <nickc@redhat.com>
1221
1222 PR 3134
1223 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1224 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1225 set.
af7329f0 1226
796d5313
NC		 12272008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1228
1229 * cr16.h (cr16_num_optab): Declared.
1230
d669d37f
NC		 12312008-02-14 Hakan Ardo <hakan@debian.org>
1232
1233 PR gas/2626
1234 * avr.h (AVR_ISA_2xxe): Define.
1235
e6429699
AN		 12362008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1237
1238 * mips.h: Update copyright.
1239 (INSN_CHIP_MASK): New macro.
1240 (INSN_OCTEON): New macro.
1241 (CPU_OCTEON): New macro.
1242 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1243
e210c36b
NC		 12442008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1245
1246 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1247
12482008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1249
1250 * avr.h (AVR_ISA_USB162): Add new opcode set.
1251 (AVR_ISA_AVR3): Likewise.
1252
350cc38d
MS		 12532007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1254
1255 * mips.h (INSN_LOONGSON_2E): New.
1256 (INSN_LOONGSON_2F): New.
1257 (CPU_LOONGSON_2E): New.
1258 (CPU_LOONGSON_2F): New.
1259 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1260
56950294
MS		 12612007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1262
1263 * mips.h (INSN_ISA*): Redefine certain values as an
1264 enumeration. Update comments.
1265 (mips_isa_table): New.
1266 (ISA_MIPS*): Redefine to match enumeration.
1267 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1268 values.
1269
c3d65c1c
BE		 12702007-08-08 Ben Elliston <bje@au.ibm.com>
1271
1272 * ppc.h (PPC_OPCODE_PPCPS): New.
1273
0fdaa005
L		 12742007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1275
1276 * m68k.h: Document j K & E.
1277
12782007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1279
1280 * cr16.h: New file for CR16 target.
1281
3896c469
AM		 12822007-05-02 Alan Modra <amodra@bigpond.net.au>
1283
1284 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1285
9a2e615a
NS		 12862007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1287
1288 * m68k.h (mcfisa_c): New.
1289 (mcfusp, mcf_mask): Adjust.
1290
b84bf58a
AM		 12912007-04-20 Alan Modra <amodra@bigpond.net.au>
1292
1293 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1294 (num_powerpc_operands): Declare.
1295 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1296 (PPC_OPERAND_PLUS1): Define.
1297
831480e9 12982007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1299
1300 * i386.h (REX_MODE64): Renamed to ...
1301 (REX_W): This.
1302 (REX_EXTX): Renamed to ...
1303 (REX_R): This.
1304 (REX_EXTY): Renamed to ...
1305 (REX_X): This.
1306 (REX_EXTZ): Renamed to ...
1307 (REX_B): This.
1308
0b1cf022
L		 13092007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1310
1311 * i386.h: Add entries from config/tc-i386.h and move tables
1312 to opcodes/i386-opc.h.
1313
d796c0ad
L		 13142007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1315
1316 * i386.h (FloatDR): Removed.
1317 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1318
30ac7323
AM		 13192007-03-01 Alan Modra <amodra@bigpond.net.au>
1320
1321 * spu-insns.h: Add soma double-float insns.
1322
8b082fb1 13232007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1324 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1325
1326 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1327 (INSN_DSPR2): Add flag for DSP R2 instructions.
1328 (M_BALIGN): New macro.
1329
4eed87de
AM		 13302007-02-14 Alan Modra <amodra@bigpond.net.au>
1331
1332 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1333 and Seg3ShortFrom with Shortform.
1334
fda592e8
L		 13352007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1336
1337 PR gas/4027
1338 * i386.h (i386_optab): Put the real "test" before the pseudo
1339 one.
1340
3bdcfdf4
KH		 13412007-01-08 Kazu Hirata <kazu@codesourcery.com>
1342
1343 * m68k.h (m68010up): OR fido_a.
1344
9840d27e
KH		 13452006-12-25 Kazu Hirata <kazu@codesourcery.com>
1346
1347 * m68k.h (fido_a): New.
1348
c629cdac
KH		 13492006-12-24 Kazu Hirata <kazu@codesourcery.com>
1350
1351 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1352 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1353 values.
1354
b7d9ef37
L		 13552006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1356
1357 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1358
b138abaa
NC		 13592006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1360
1361 * score-inst.h (enum score_insn_type): Add Insn_internal.
1362
e9f53129
AM		 13632006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1364 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1365 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1366 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1367 Alan Modra <amodra@bigpond.net.au>
1368
1369 * spu-insns.h: New file.
1370 * spu.h: New file.
1371
ede602d7
AM		 13722006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1373
1374 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1375
7918206c
MM		 13762006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1377
e4e42b45 1378 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1379 in amdfam10 architecture.
1380
ef05d495
L		 13812006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1382
1383 * i386.h: Replace CpuMNI with CpuSSSE3.
1384
2d447fca 13852006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1386 Joseph Myers <joseph@codesourcery.com>
1387 Ian Lance Taylor <ian@wasabisystems.com>
1388 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1389
1390 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1391
1c0d3aa6
NC		 13922006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1393
1394 * score-datadep.h: New file.
1395 * score-inst.h: New file.
1396
c2f0420e
L		 13972006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1398
1399 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1400 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1401 movdq2q and movq2dq.
1402
050dfa73
MM		 14032006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1404 Michael Meissner <michael.meissner@amd.com>
1405
1406 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1407
15965411
L		 14082006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1409
1410 * i386.h (i386_optab): Add "nop" with memory reference.
1411
46e883c5
L		 14122006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1413
1414 * i386.h (i386_optab): Update comment for 64bit NOP.
1415
9622b051
AM		 14162006-06-06 Ben Elliston <bje@au.ibm.com>
1417 Anton Blanchard <anton@samba.org>
1418
1419 * ppc.h (PPC_OPCODE_POWER6): Define.
1420 Adjust whitespace.
1421
a9e24354
TS		 14222006-06-05 Thiemo Seufer <ths@mips.com>
1423
e4e42b45 1424 * mips.h: Improve description of MT flags.
a9e24354 1425
a596001e
RS		 14262006-05-25 Richard Sandiford <richard@codesourcery.com>
1427
1428 * m68k.h (mcf_mask): Define.
1429
d43b4baf 14302006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1431 David Ung <davidu@mips.com>
d43b4baf
TS		 1432
1433 * mips.h (enum): Add macro M_CACHE_AB.
1434
39a7806d 14352006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1436 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1437 David Ung <davidu@mips.com>
1438
1439 * mips.h: Add INSN_SMARTMIPS define.
1440
9bcd4f99 14412006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1442 David Ung <davidu@mips.com>
9bcd4f99
TS		 1443
1444 * mips.h: Defines udi bits and masks. Add description of
1445 characters which may appear in the args field of udi
1446 instructions.
1447
ef0ee844
TS		 14482006-04-26 Thiemo Seufer <ths@networkno.de>
1449
1450 * mips.h: Improve comments describing the bitfield instruction
1451 fields.
1452
f7675147
L		 14532006-04-26 Julian Brown <julian@codesourcery.com>
1454
1455 * arm.h (FPU_VFP_EXT_V3): Define constant.
1456 (FPU_NEON_EXT_V1): Likewise.
1457 (FPU_VFP_HARD): Update.
1458 (FPU_VFP_V3): Define macro.
1459 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1460
ef0ee844 14612006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1462
1463 * avr.h (AVR_ISA_PWMx): New.
1464
2da12c60
NS		 14652006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1466
1467 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1468 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1469 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1470 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1471 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1472
0715c387
PB		 14732006-03-10 Paul Brook <paul@codesourcery.com>
1474
1475 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1476
34bdd094
DA		 14772006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1478
1479 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1480 first. Correct mask of bb "B" opcode.
1481
331d2d0d
L		 14822006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1483
1484 * i386.h (i386_optab): Support Intel Merom New Instructions.
1485
62b3e311
PB		 14862006-02-24 Paul Brook <paul@codesourcery.com>
1487
1488 * arm.h: Add V7 feature bits.
1489
59cf82fe
L		 14902006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1491
1492 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1493
e74cfd16
PB		 14942006-01-31 Paul Brook <paul@codesourcery.com>
1495 Richard Earnshaw <rearnsha@arm.com>
1496
1497 * arm.h: Use ARM_CPU_FEATURE.
1498 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1499 (arm_feature_set): Change to a structure.
1500 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1501 ARM_FEATURE): New macros.
1502
5b3f8a92
HPN		 15032005-12-07 Hans-Peter Nilsson <hp@axis.com>
1504
1505 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1506 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1507 (ADD_PC_INCR_OPCODE): Don't define.
1508
cb712a9e
L		 15092005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1510
1511 PR gas/1874
1512 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1513
0499d65b
TS		 15142005-11-14 David Ung <davidu@mips.com>
1515
1516 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1517 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1518 save/restore encoding of the args field.
1519
ea5ca089
DB		 15202005-10-28 Dave Brolley <brolley@redhat.com>
1521
1522 Contribute the following changes:
1523 2005-02-16 Dave Brolley <brolley@redhat.com>
1524
1525 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1526 cgen_isa_mask_* to cgen_bitset_*.
1527 * cgen.h: Likewise.
1528
16175d96
DB		 1529 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1530
1531 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1532 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1533 (CGEN_CPU_TABLE): Make isas a ponter.
1534
1535 2003-09-29 Dave Brolley <brolley@redhat.com>
1536
1537 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1538 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1539 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1540
1541 2002-12-13 Dave Brolley <brolley@redhat.com>
1542
1543 * cgen.h (symcat.h): #include it.
1544 (cgen-bitset.h): #include it.
1545 (CGEN_ATTR_VALUE_TYPE): Now a union.
1546 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1547 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1548 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1549 * cgen-bitset.h: New file.
1550
3c9b82ba
NC		 15512005-09-30 Catherine Moore <clm@cm00re.com>
1552
1553 * bfin.h: New file.
1554
6a2375c6
JB		 15552005-10-24 Jan Beulich <jbeulich@novell.com>
1556
1557 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1558 indirect operands.
1559
c06a12f8
DA		 15602005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1561
1562 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1563 Add FLAG_STRICT to pa10 ftest opcode.
1564
4d443107
DA		 15652005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1566
1567 * hppa.h (pa_opcodes): Remove lha entries.
1568
f0a3b40f
DA		 15692005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1570
1571 * hppa.h (FLAG_STRICT): Revise comment.
1572 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1573 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1574 entries for "fdc".
1575
e210c36b
NC		 15762005-09-30 Catherine Moore <clm@cm00re.com>
1577
1578 * bfin.h: New file.
1579
1b7e1362
DA		 15802005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1581
1582 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1583
089b39de
CF		 15842005-09-06 Chao-ying Fu <fu@mips.com>
1585
1586 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1587 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1588 define.
1589 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1590 (INSN_ASE_MASK): Update to include INSN_MT.
1591 (INSN_MT): New define for MT ASE.
1592
93c34b9b
CF		 15932005-08-25 Chao-ying Fu <fu@mips.com>
1594
1595 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1596 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1597 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1598 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1599 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1600 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1601 instructions.
1602 (INSN_DSP): New define for DSP ASE.
1603
848cf006
AM		 16042005-08-18 Alan Modra <amodra@bigpond.net.au>
1605
1606 * a29k.h: Delete.
1607
36ae0db3
DJ		 16082005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1609
1610 * ppc.h (PPC_OPCODE_E300): Define.
1611
8c929562
MS		 16122005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1613
1614 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1615
f7b8cccc
DA		 16162005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1617
1618 PR gas/336
1619 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1620 and pitlb.
1621
8b5328ac
JB		 16222005-07-27 Jan Beulich <jbeulich@novell.com>
1623
1624 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1625 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1626 Add movq-s as 64-bit variants of movd-s.
1627
f417d200
DA		 16282005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1629
18b3bdfc
DA		 1630 * hppa.h: Fix punctuation in comment.
1631
f417d200
DA		 1632 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1633 implicit space-register addressing. Set space-register bits on opcodes
1634 using implicit space-register addressing. Add various missing pa20
1635 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1636 space-register addressing. Use "fE" instead of "fe" in various
1637 fstw opcodes.
1638
9a145ce6
JB		 16392005-07-18 Jan Beulich <jbeulich@novell.com>
1640
1641 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1642
90700ea2
L		 16432007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1644
1645 * i386.h (i386_optab): Support Intel VMX Instructions.
1646
48f130a8
DA		 16472005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1648
1649 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1650
30123838
JB		 16512005-07-05 Jan Beulich <jbeulich@novell.com>
1652
1653 * i386.h (i386_optab): Add new insns.
1654
47b0e7ad
NC		 16552005-07-01 Nick Clifton <nickc@redhat.com>
1656
1657 * sparc.h: Add typedefs to structure declarations.
1658
b300c311
L		 16592005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1660
1661 PR 1013
1662 * i386.h (i386_optab): Update comments for 64bit addressing on
1663 mov. Allow 64bit addressing for mov and movq.
1664
2db495be
DA		 16652005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1666
1667 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1668 respectively, in various floating-point load and store patterns.
1669
caa05036
DA		 16702005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1671
1672 * hppa.h (FLAG_STRICT): Correct comment.
1673 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1674 PA 2.0 mneumonics when equivalent. Entries with cache control
1675 completers now require PA 1.1. Adjust whitespace.
1676
f4411256
AM		 16772005-05-19 Anton Blanchard <anton@samba.org>
1678
1679 * ppc.h (PPC_OPCODE_POWER5): Define.
1680
e172dbf8
NC		 16812005-05-10 Nick Clifton <nickc@redhat.com>
1682
1683 * Update the address and phone number of the FSF organization in
1684 the GPL notices in the following files:
1685 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1686 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1687 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1688 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1689 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1690 tic54x.h, tic80.h, v850.h, vax.h
1691
e44823cf
JB		 16922005-05-09 Jan Beulich <jbeulich@novell.com>
1693
1694 * i386.h (i386_optab): Add ht and hnt.
1695
791fe849
MK		 16962005-04-18 Mark Kettenis <kettenis@gnu.org>
1697
1698 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1699 Add xcrypt-ctr. Provide aliases without hyphens.
1700
faa7ef87
L		 17012005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1702
a63027e5
L		 1703 Moved from ../ChangeLog
1704
faa7ef87
L		 1705 2005-04-12 Paul Brook <paul@codesourcery.com>
1706 * m88k.h: Rename psr macros to avoid conflicts.
1707
1708 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1709 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1710 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1711 and ARM_ARCH_V6ZKT2.
1712
1713 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1714 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1715 Remove redundant instruction types.
1716 (struct argument): X_op - new field.
1717 (struct cst4_entry): Remove.
1718 (no_op_insn): Declare.
1719
1720 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1721 * crx.h (enum argtype): Rename types, remove unused types.
1722
1723 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1724 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1725 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1726 (enum operand_type): Rearrange operands, edit comments.
1727 replace us<N> with ui<N> for unsigned immediate.
1728 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1729 displacements (respectively).
1730 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1731 (instruction type): Add NO_TYPE_INS.
1732 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1733 (operand_entry): New field - 'flags'.
1734 (operand flags): New.
1735
1736 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1737 * crx.h (operand_type): Remove redundant types i3, i4,
1738 i5, i8, i12.
1739 Add new unsigned immediate types us3, us4, us5, us16.
1740
bc4bd9ab
MK		 17412005-04-12 Mark Kettenis <kettenis@gnu.org>
1742
1743 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1744 adjust them accordingly.
1745
373ff435
JB		 17462005-04-01 Jan Beulich <jbeulich@novell.com>
1747
1748 * i386.h (i386_optab): Add rdtscp.
1749
4cc91dba
L		 17502005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1751
1752 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 1753 between memory and segment register. Allow movq for moving between
1754 general-purpose register and segment register.
4cc91dba 1755
9ae09ff9
JB		 17562005-02-09 Jan Beulich <jbeulich@novell.com>
1757
1758 PR gas/707
1759 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1760 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1761 fnstsw.
1762
638e7a64
NS		 17632006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1764
1765 * m68k.h (m68008, m68ec030, m68882): Remove.
1766 (m68k_mask): New.
1767 (cpu_m68k, cpu_cf): New.
1768 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1769 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1770
90219bd0
AO		 17712005-01-25 Alexandre Oliva <aoliva@redhat.com>
1772
1773 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1774 * cgen.h (enum cgen_parse_operand_type): Add
1775 CGEN_PARSE_OPERAND_SYMBOLIC.
1776
239cb185
FF		 17772005-01-21 Fred Fish <fnf@specifixinc.com>
1778
1779 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1780 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1781 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1782
dc9a9f39
FF		 17832005-01-19 Fred Fish <fnf@specifixinc.com>
1784
1785 * mips.h (struct mips_opcode): Add new pinfo2 member.
1786 (INSN_ALIAS): New define for opcode table entries that are
1787 specific instances of another entry, such as 'move' for an 'or'
1788 with a zero operand.
1789 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1790 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1791
98e7aba8
ILT		 17922004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1793
1794 * mips.h (CPU_RM9000): Define.
1795 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1796
37edbb65
JB		 17972004-11-25 Jan Beulich <jbeulich@novell.com>
1798
1799 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1800 to/from test registers are illegal in 64-bit mode. Add missing
1801 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1802 (previously one had to explicitly encode a rex64 prefix). Re-enable
1803 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1804 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1805
18062004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 1807
1808 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1809 available only with SSE2. Change the MMX additions introduced by SSE
1810 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1811 instructions by their now designated identifier (since combining i686
1812 and 3DNow! does not really imply 3DNow!A).
1813
f5c7edf4
AM		 18142004-11-19 Alan Modra <amodra@bigpond.net.au>
1815
1816 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1817 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1818
7499d566
NC		 18192004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1820 Vineet Sharma <vineets@noida.hcltech.com>
1821
1822 * maxq.h: New file: Disassembly information for the maxq port.
1823
bcb9eebe
L		 18242004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1825
1826 * i386.h (i386_optab): Put back "movzb".
1827
94bb3d38
HPN		 18282004-11-04 Hans-Peter Nilsson <hp@axis.com>
1829
1830 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1831 comments. Remove member cris_ver_sim. Add members
1832 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1833 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1834 (struct cris_support_reg, struct cris_cond15): New types.
1835 (cris_conds15): Declare.
1836 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1837 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1838 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1839 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1840 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1841 SIZE_FIELD_UNSIGNED.
1842
37edbb65 18432004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 1844
1845 * i386.h (sldx_Suf): Remove.
1846 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1847 (q_FP): Define, implying no REX64.
1848 (x_FP, sl_FP): Imply FloatMF.
1849 (i386_optab): Split reg and mem forms of moving from segment registers
1850 so that the memory forms can ignore the 16-/32-bit operand size
1851 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1852 all non-floating-point instructions. Unite 32- and 64-bit forms of
1853 movsx, movzx, and movd. Adjust floating point operations for the above
1854 changes to the *FP macros. Add DefaultSize to floating point control
1855 insns operating on larger memory ranges. Remove left over comments
1856 hinting at certain insns being Intel-syntax ones where the ones
1857 actually meant are already gone.
1858
48c9f030
NC		 18592004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1860
1861 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1862 instruction type.
1863
0dd132b6
NC		 18642004-09-30 Paul Brook <paul@codesourcery.com>
1865
1866 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1867 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1868
23794b24
MM		 18692004-09-11 Theodore A. Roth <troth@openavr.org>
1870
1871 * avr.h: Add support for
1872 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1873
2a309db0
AM		 18742004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1875
1876 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1877
b18c562e
NC		 18782004-08-24 Dmitry Diky <diwil@spec.ru>
1879
1880 * msp430.h (msp430_opc): Add new instructions.
1881 (msp430_rcodes): Declare new instructions.
1882 (msp430_hcodes): Likewise..
1883
45d313cd
NC		 18842004-08-13 Nick Clifton <nickc@redhat.com>
1885
1886 PR/301
1887 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1888 processors.
1889
30d1c836
ML		 18902004-08-30 Michal Ludvig <mludvig@suse.cz>
1891
1892 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1893
9a45f1c2
L		 18942004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1895
1896 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1897
543613e9
NC		 18982004-07-21 Jan Beulich <jbeulich@novell.com>
1899
1900 * i386.h: Adjust instruction descriptions to better match the
1901 specification.
1902
b781e558
RE		 19032004-07-16 Richard Earnshaw <rearnsha@arm.com>
1904
1905 * arm.h: Remove all old content. Replace with architecture defines
1906 from gas/config/tc-arm.c.
1907
8577e690
AS		 19082004-07-09 Andreas Schwab <schwab@suse.de>
1909
1910 * m68k.h: Fix comment.
1911
1fe1f39c
NC		 19122004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1913
1914 * crx.h: New file.
1915
1d9f512f
AM		 19162004-06-24 Alan Modra <amodra@bigpond.net.au>
1917
1918 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1919
be8c092b
NC		 19202004-05-24 Peter Barada <peter@the-baradas.com>
1921
1922 * m68k.h: Add 'size' to m68k_opcode.
1923
6b6e92f4
NC		 19242004-05-05 Peter Barada <peter@the-baradas.com>
1925
1926 * m68k.h: Switch from ColdFire chip name to core variant.
1927
19282004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 1929
1930 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1931 descriptions for new EMAC cases.
1932 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1933 handle Motorola MAC syntax.
1934 Allow disassembly of ColdFire V4e object files.
1935
fdd12ef3
AM		 19362004-03-16 Alan Modra <amodra@bigpond.net.au>
1937
1938 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1939
3922a64c
L		 19402004-03-12 Jakub Jelinek <jakub@redhat.com>
1941
1942 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1943
1f45d988
ML		 19442004-03-12 Michal Ludvig <mludvig@suse.cz>
1945
1946 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1947
0f10071e
ML		 19482004-03-12 Michal Ludvig <mludvig@suse.cz>
1949
1950 * i386.h (i386_optab): Added xstore/xcrypt insns.
1951
3255318a
NC		 19522004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1953
1954 * h8300.h (32bit ldc/stc): Add relaxing support.
1955
ca9a79a1 19562004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 1957
ca9a79a1
NC		 1958 * h8300.h (BITOP): Pass MEMRELAX flag.
1959
875a0b14
NC		 19602004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1961
1962 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1963 except for the H8S.
252b5132 1964
c9e214e5 1965For older changes see ChangeLog-9103
252b5132 1966\f
4b95cf5c 1967Copyright (C) 2004-2014 Free Software Foundation, Inc.
752937aa
NC		 1968
1969Copying and distribution of this file, with or without modification,
1970are permitted in any medium without royalty provided the copyright
1971notice and this notice are preserved.
1972
252b5132 1973Local Variables:
c9e214e5
AM		 1974mode: change-log
1975left-margin: 8
1976fill-column: 74
252b5132
RH		 1977version-control: never
1978End:
GDB Binutils - Deliverables
This page took 0.688551 seconds and 4 git commands to generate.