projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[BINUTILS, ARM] Add Armv8.5-A to select_arm_features and update macros.
[deliverable/binutils-gdb.git] / include / opcode / aarch64.h
CommitLineData
a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
219d1afa 3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
c0e7cef7
NC		 40#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
41#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
b6b9ca0c
TC		 42#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
43#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
44#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
a06ea964 45#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
acb787b0 46#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
1924ff75 47#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
a06ea964
NC		 48#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
49#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
50#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
e60bb1dd 51#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
ee804238 52#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
f21cce2c 53#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
290806fd 54#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
9e1f0fa7 55#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
250aafa4 56#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
af117b3c 57#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
c8a6db6f 58#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
73af8ed6 59#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
c0890d26 60#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
d74d4880 61#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
f482d304 62#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
65a55fbb 63#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
d0f7791c 64#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */
70d56181 65#define AARCH64_FEATURE_V8_5 0x2000000000ULL /* ARMv8.5 processors. */
a06ea964 66
13c60ad7
SD		 67/* Flag Manipulation insns. */
68#define AARCH64_FEATURE_FLAGMANIP 0x4000000000ULL
69/* FRINT[32,64][Z,X] insns. */
70#define AARCH64_FEATURE_FRINTTS 0x8000000000ULL
68dfbb92
SD		 71/* SB instruction. */
72#define AARCH64_FEATURE_SB 0x10000000000ULL
2ac435d4
SD		 73/* Execution and Data Prediction Restriction instructions. */
74#define AARCH64_FEATURE_PREDRES 0x20000000000ULL
3fd229a4
SD		 75/* DC CVADP. */
76#define AARCH64_FEATURE_CVADP 0x40000000000ULL
af4bcb4c
SD		 77/* Random Number instructions. */
78#define AARCH64_FEATURE_RNG 0x80000000000ULL
ff605452
SD		 79/* BTI instructions. */
80#define AARCH64_FEATURE_BTI 0x100000000000ULL
a97330e7
SD		 81/* SCXTNUM_ELx. */
82#define AARCH64_FEATURE_SCXTNUM 0x200000000000ULL
83/* ID_PFR2 instructions. */
84#define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL
104fefee
SD		 85/* SSBS mechanism enabled. */
86#define AARCH64_FEATURE_SSBS 0x800000000000ULL
a97330e7 87
13c60ad7 88
a06ea964
NC		 89/* Architectures are the sum of the base and extensions. */
90#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
91 AARCH64_FEATURE_FP \
92 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 93#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
94 AARCH64_FEATURE_CRC \
250aafa4 95 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 96 | AARCH64_FEATURE_LSE \
97 | AARCH64_FEATURE_PAN \
98 | AARCH64_FEATURE_LOR \
99 | AARCH64_FEATURE_RDMA)
1924ff75 100#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 101 AARCH64_FEATURE_V8_2 \
1924ff75
SN		 102 | AARCH64_FEATURE_RAS)
103#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
d74d4880 104 AARCH64_FEATURE_V8_3 \
f482d304
RS		 105 | AARCH64_FEATURE_RCPC \
106 | AARCH64_FEATURE_COMPNUM)
b6b9ca0c 107#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
981b557a 108 AARCH64_FEATURE_V8_4 \
d0f7791c
TC		 109 | AARCH64_FEATURE_DOTPROD \
110 | AARCH64_FEATURE_F16_FML)
70d56181 111#define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
13c60ad7
SD		 112 AARCH64_FEATURE_V8_5 \
113 | AARCH64_FEATURE_FLAGMANIP \
68dfbb92 114 | AARCH64_FEATURE_FRINTTS \
2ac435d4 115 | AARCH64_FEATURE_SB \
3fd229a4 116 | AARCH64_FEATURE_PREDRES \
ff605452 117 | AARCH64_FEATURE_CVADP \
a97330e7
SD		 118 | AARCH64_FEATURE_BTI \
119 | AARCH64_FEATURE_SCXTNUM \
104fefee
SD		 120 | AARCH64_FEATURE_ID_PFR2 \
121 | AARCH64_FEATURE_SSBS)
70d56181 122
88f0ea34 123
a06ea964
NC		 124#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
125#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
126
127/* CPU-specific features. */
21b81e67 128typedef unsigned long long aarch64_feature_set;
a06ea964 129
93d8990c
SN		 130#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
131 ((~(CPU) & (FEAT)) == 0)
132
133#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 134 (((CPU) & (FEAT)) != 0)
135
93d8990c
SN		 136#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
137 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
138
a06ea964
NC		 139#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
140 do \
141 { \
142 (TARG) = (F1) | (F2); \
143 } \
144 while (0)
145
146#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
147 do \
148 { \
149 (TARG) = (F1) &~ (F2); \
150 } \
151 while (0)
152
153#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
154
a06ea964
NC		 155enum aarch64_operand_class
156{
157 AARCH64_OPND_CLASS_NIL,
158 AARCH64_OPND_CLASS_INT_REG,
159 AARCH64_OPND_CLASS_MODIFIED_REG,
160 AARCH64_OPND_CLASS_FP_REG,
161 AARCH64_OPND_CLASS_SIMD_REG,
162 AARCH64_OPND_CLASS_SIMD_ELEMENT,
163 AARCH64_OPND_CLASS_SISD_REG,
164 AARCH64_OPND_CLASS_SIMD_REGLIST,
f11ad6bc
RS		 165 AARCH64_OPND_CLASS_SVE_REG,
166 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 167 AARCH64_OPND_CLASS_ADDRESS,
168 AARCH64_OPND_CLASS_IMMEDIATE,
169 AARCH64_OPND_CLASS_SYSTEM,
68a64283 170 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 171};
172
173/* Operand code that helps both parsing and coding.
174 Keep AARCH64_OPERANDS synced. */
175
176enum aarch64_opnd
177{
178 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
179
180 AARCH64_OPND_Rd, /* Integer register as destination. */
181 AARCH64_OPND_Rn, /* Integer register as source. */
182 AARCH64_OPND_Rm, /* Integer register as source. */
183 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
184 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
185 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
186 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
187 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
188
189 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
190 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 191 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 192 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 193 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
194 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
195
196 AARCH64_OPND_Fd, /* Floating-point Fd. */
197 AARCH64_OPND_Fn, /* Floating-point Fn. */
198 AARCH64_OPND_Fm, /* Floating-point Fm. */
199 AARCH64_OPND_Fa, /* Floating-point Fa. */
200 AARCH64_OPND_Ft, /* Floating-point Ft. */
201 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
202
203 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
204 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
205 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
206
f42f1a1d 207 AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
a06ea964
NC		 208 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
209 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
210 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
211 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
212 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
213 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
214 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
215 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
369c9167
TC		 216 AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
217 qualifier is S_H. */
a06ea964
NC		 218 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
219 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
220 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
221 structure to all lanes. */
222 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
223
a6a51754
RL		 224 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
225 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
a06ea964
NC		 226
227 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
f42f1a1d 228 AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */
a06ea964
NC		 229 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
230 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
231 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
232 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
233 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
234 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
235 (no encoding). */
236 AARCH64_OPND_IMM0, /* Immediate for #0. */
237 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
238 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
239 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
240 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
241 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
242 AARCH64_OPND_IMM, /* Immediate. */
f42f1a1d 243 AARCH64_OPND_IMM_2, /* Immediate. */
a06ea964
NC		 244 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
245 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
246 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
247 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
248 AARCH64_OPND_BIT_NUM, /* Immediate. */
249 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
250 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 251 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 252 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
253 each condition flag. */
254
255 AARCH64_OPND_LIMM, /* Logical Immediate. */
256 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
257 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
258 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
259 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
c2c4ff8d
SN		 260 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
261 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
262 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
a06ea964
NC		 263
264 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 265 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 266
267 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
268 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
269 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
270 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
271 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
272
273 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
274 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
275 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
276 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
277 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
278 negative or unaligned and there is
279 no writeback allowed. This operand code
280 is only used to support the programmer-
281 friendly feature of using LDR/STR as the
282 the mnemonic name for LDUR/STUR instructions
283 wherever there is no ambiguity. */
3f06e550 284 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
a06ea964
NC		 285 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
286 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
f42f1a1d 287 AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
a06ea964
NC		 288 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
289
290 AARCH64_OPND_SYSREG, /* System register operand. */
291 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
292 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
293 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
294 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
295 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
2ac435d4 296 AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
a06ea964
NC		 297 AARCH64_OPND_BARRIER, /* Barrier operand. */
298 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
299 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 300 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
ff605452 301 AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
f11ad6bc 302
582e12bf 303 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
98907a70
RS		 304 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
305 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
306 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
307 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
308 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
309 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 310 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
311 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
312 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
313 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
c8d59609 314 AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */
4df068de
RS		 315 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
316 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
317 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
318 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
319 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
320 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
321 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
322 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
323 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
324 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
325 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
326 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
327 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
328 Bit 14 controls S/U choice. */
329 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
330 Bit 22 controls S/U choice. */
331 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
332 Bit 14 controls S/U choice. */
333 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
334 Bit 22 controls S/U choice. */
335 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
336 Bit 14 controls S/U choice. */
337 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
338 Bit 22 controls S/U choice. */
339 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
340 Bit 14 controls S/U choice. */
341 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
342 Bit 22 controls S/U choice. */
343 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
344 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
345 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
346 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
347 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
348 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
349 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 350 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
351 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 352 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
353 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
354 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
355 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
582e12bf
RS		 356 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
357 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
e950b345
RS		 358 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
359 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
360 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 361 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 362 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 363 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 364 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
365 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
366 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
367 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
368 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
369 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
370 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
371 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 372 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
373 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 374 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
375 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
376 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
377 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
378 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
379 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
380 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
381 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
382 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
383 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
384 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
385 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 386 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
387 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
388 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
389 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 390 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
391 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
392 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
393 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
394 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
582e12bf
RS		 395 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
396 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
397 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
f11ad6bc
RS		 398 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
399 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
400 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
401 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
402 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
f42f1a1d 403 AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
a06ea964
NC		 404};
405
406/* Qualifier constrains an operand. It either specifies a variant of an
407 operand type or limits values available to an operand type.
408
409 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
410
411enum aarch64_opnd_qualifier
412{
413 /* Indicating no further qualification on an operand. */
414 AARCH64_OPND_QLF_NIL,
415
416 /* Qualifying an operand which is a general purpose (integer) register;
417 indicating the operand data size or a specific register. */
418 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
419 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
420 AARCH64_OPND_QLF_WSP, /* WSP. */
421 AARCH64_OPND_QLF_SP, /* SP. */
422
423 /* Qualifying an operand which is a floating-point register, a SIMD
424 vector element or a SIMD vector element list; indicating operand data
425 size or the size of each SIMD vector element in the case of a SIMD
426 vector element list.
427 These qualifiers are also used to qualify an address operand to
428 indicate the size of data element a load/store instruction is
429 accessing.
430 They are also used for the immediate shift operand in e.g. SSHR. Such
431 a use is only for the ease of operand encoding/decoding and qualifier
432 sequence matching; such a use should not be applied widely; use the value
433 constraint qualifiers for immediate operands wherever possible. */
434 AARCH64_OPND_QLF_S_B,
435 AARCH64_OPND_QLF_S_H,
436 AARCH64_OPND_QLF_S_S,
437 AARCH64_OPND_QLF_S_D,
438 AARCH64_OPND_QLF_S_Q,
00c2093f
TC		 439 /* This type qualifier has a special meaning in that it means that 4 x 1 byte
440 are selected by the instruction. Other than that it has no difference
441 with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical
442 reasons and is an exception from normal AArch64 disassembly scheme. */
443 AARCH64_OPND_QLF_S_4B,
a06ea964
NC		 444
445 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
446 register list; indicating register shape.
447 They are also used for the immediate shift operand in e.g. SSHR. Such
448 a use is only for the ease of operand encoding/decoding and qualifier
449 sequence matching; such a use should not be applied widely; use the value
450 constraint qualifiers for immediate operands wherever possible. */
a3b3345a 451 AARCH64_OPND_QLF_V_4B,
a06ea964
NC		 452 AARCH64_OPND_QLF_V_8B,
453 AARCH64_OPND_QLF_V_16B,
3067d3b9 454 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 455 AARCH64_OPND_QLF_V_4H,
456 AARCH64_OPND_QLF_V_8H,
457 AARCH64_OPND_QLF_V_2S,
458 AARCH64_OPND_QLF_V_4S,
459 AARCH64_OPND_QLF_V_1D,
460 AARCH64_OPND_QLF_V_2D,
461 AARCH64_OPND_QLF_V_1Q,
462
d50c751e
RS		 463 AARCH64_OPND_QLF_P_Z,
464 AARCH64_OPND_QLF_P_M,
465
a06ea964 466 /* Constraint on value. */
a6a51754 467 AARCH64_OPND_QLF_CR, /* CRn, CRm. */
a06ea964
NC		 468 AARCH64_OPND_QLF_imm_0_7,
469 AARCH64_OPND_QLF_imm_0_15,
470 AARCH64_OPND_QLF_imm_0_31,
471 AARCH64_OPND_QLF_imm_0_63,
472 AARCH64_OPND_QLF_imm_1_32,
473 AARCH64_OPND_QLF_imm_1_64,
474
475 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
476 or shift-ones. */
477 AARCH64_OPND_QLF_LSL,
478 AARCH64_OPND_QLF_MSL,
479
480 /* Special qualifier helping retrieve qualifier information during the
481 decoding time (currently not in use). */
482 AARCH64_OPND_QLF_RETRIEVE,
483};
484\f
485/* Instruction class. */
486
487enum aarch64_insn_class
488{
489 addsub_carry,
490 addsub_ext,
491 addsub_imm,
492 addsub_shift,
493 asimdall,
494 asimddiff,
495 asimdelem,
496 asimdext,
497 asimdimm,
498 asimdins,
499 asimdmisc,
500 asimdperm,
501 asimdsame,
502 asimdshf,
503 asimdtbl,
504 asisddiff,
505 asisdelem,
506 asisdlse,
507 asisdlsep,
508 asisdlso,
509 asisdlsop,
510 asisdmisc,
511 asisdone,
512 asisdpair,
513 asisdsame,
514 asisdshf,
515 bitfield,
516 branch_imm,
517 branch_reg,
518 compbranch,
519 condbranch,
520 condcmp_imm,
521 condcmp_reg,
522 condsel,
523 cryptoaes,
524 cryptosha2,
525 cryptosha3,
526 dp_1src,
527 dp_2src,
528 dp_3src,
529 exception,
530 extract,
531 float2fix,
532 float2int,
533 floatccmp,
534 floatcmp,
535 floatdp1,
536 floatdp2,
537 floatdp3,
538 floatimm,
539 floatsel,
540 ldst_immpost,
541 ldst_immpre,
542 ldst_imm9, /* immpost or immpre */
3f06e550 543 ldst_imm10, /* LDRAA/LDRAB */
a06ea964
NC		 544 ldst_pos,
545 ldst_regoff,
546 ldst_unpriv,
547 ldst_unscaled,
548 ldstexcl,
549 ldstnapair_offs,
550 ldstpair_off,
551 ldstpair_indexed,
552 loadlit,
553 log_imm,
554 log_shift,
ee804238 555 lse_atomic,
a06ea964
NC		 556 movewide,
557 pcreladdr,
558 ic_system,
116b6019
RS		 559 sve_cpy,
560 sve_index,
561 sve_limm,
562 sve_misc,
563 sve_movprfx,
564 sve_pred_zm,
565 sve_shift_pred,
566 sve_shift_unpred,
567 sve_size_bhs,
568 sve_size_bhsd,
569 sve_size_hsd,
570 sve_size_sd,
a06ea964 571 testbranch,
f42f1a1d
TC		 572 cryptosm3,
573 cryptosm4,
65a55fbb 574 dotproduct,
a06ea964
NC		 575};
576
577/* Opcode enumerators. */
578
579enum aarch64_op
580{
581 OP_NIL,
582 OP_STRB_POS,
583 OP_LDRB_POS,
584 OP_LDRSB_POS,
585 OP_STRH_POS,
586 OP_LDRH_POS,
587 OP_LDRSH_POS,
588 OP_STR_POS,
589 OP_LDR_POS,
590 OP_STRF_POS,
591 OP_LDRF_POS,
592 OP_LDRSW_POS,
593 OP_PRFM_POS,
594
595 OP_STURB,
596 OP_LDURB,
597 OP_LDURSB,
598 OP_STURH,
599 OP_LDURH,
600 OP_LDURSH,
601 OP_STUR,
602 OP_LDUR,
603 OP_STURV,
604 OP_LDURV,
605 OP_LDURSW,
606 OP_PRFUM,
607
608 OP_LDR_LIT,
609 OP_LDRV_LIT,
610 OP_LDRSW_LIT,
611 OP_PRFM_LIT,
612
613 OP_ADD,
614 OP_B,
615 OP_BL,
616
617 OP_MOVN,
618 OP_MOVZ,
619 OP_MOVK,
620
621 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
622 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
623 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
624
625 OP_MOV_V, /* MOV alias for moving vector register. */
626
627 OP_ASR_IMM,
628 OP_LSR_IMM,
629 OP_LSL_IMM,
630
631 OP_BIC,
632
633 OP_UBFX,
634 OP_BFXIL,
635 OP_SBFX,
636 OP_SBFIZ,
637 OP_BFI,
d685192a 638 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 639 OP_UBFIZ,
640 OP_UXTB,
641 OP_UXTH,
642 OP_UXTW,
643
a06ea964
NC		 644 OP_CINC,
645 OP_CINV,
646 OP_CNEG,
647 OP_CSET,
648 OP_CSETM,
649
650 OP_FCVT,
651 OP_FCVTN,
652 OP_FCVTN2,
653 OP_FCVTL,
654 OP_FCVTL2,
655 OP_FCVTXN_S, /* Scalar version. */
656
657 OP_ROR_IMM,
658
e30181a5
YZ		 659 OP_SXTL,
660 OP_SXTL2,
661 OP_UXTL,
662 OP_UXTL2,
663
c0890d26
RS		 664 OP_MOV_P_P,
665 OP_MOV_Z_P_Z,
666 OP_MOV_Z_V,
667 OP_MOV_Z_Z,
668 OP_MOV_Z_Zi,
669 OP_MOVM_P_P_P,
670 OP_MOVS_P_P,
671 OP_MOVZS_P_P_P,
672 OP_MOVZ_P_P_P,
673 OP_NOTS_P_P_P_Z,
674 OP_NOT_P_P_P_Z,
675
c2c4ff8d
SN		 676 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
677
a06ea964
NC		 678 OP_TOTAL_NUM, /* Pseudo. */
679};
680
1d482394
TC		 681/* Error types. */
682enum err_type
683{
684 ERR_OK,
685 ERR_UND,
686 ERR_UNP,
687 ERR_NYI,
a68f4cd2 688 ERR_VFI,
1d482394
TC		 689 ERR_NR_ENTRIES
690};
691
a06ea964
NC		 692/* Maximum number of operands an instruction can have. */
693#define AARCH64_MAX_OPND_NUM 6
694/* Maximum number of qualifier sequences an instruction can have. */
695#define AARCH64_MAX_QLF_SEQ_NUM 10
696/* Operand qualifier typedef; optimized for the size. */
697typedef unsigned char aarch64_opnd_qualifier_t;
698/* Operand qualifier sequence typedef. */
699typedef aarch64_opnd_qualifier_t \
700 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
701
702/* FIXME: improve the efficiency. */
703static inline bfd_boolean
704empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
705{
706 int i;
707 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
708 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
709 return FALSE;
710 return TRUE;
711}
712
7e84b55d
TC		 713/* Forward declare error reporting type. */
714typedef struct aarch64_operand_error aarch64_operand_error;
715/* Forward declare instruction sequence type. */
716typedef struct aarch64_instr_sequence aarch64_instr_sequence;
717/* Forward declare instruction definition. */
718typedef struct aarch64_inst aarch64_inst;
719
a06ea964
NC		 720/* This structure holds information for a particular opcode. */
721
722struct aarch64_opcode
723{
724 /* The name of the mnemonic. */
725 const char *name;
726
727 /* The opcode itself. Those bits which will be filled in with
728 operands are zeroes. */
729 aarch64_insn opcode;
730
731 /* The opcode mask. This is used by the disassembler. This is a
732 mask containing ones indicating those bits which must match the
733 opcode field, and zeroes indicating those bits which need not
734 match (and are presumably filled in by operands). */
735 aarch64_insn mask;
736
737 /* Instruction class. */
738 enum aarch64_insn_class iclass;
739
740 /* Enumerator identifier. */
741 enum aarch64_op op;
742
743 /* Which architecture variant provides this instruction. */
744 const aarch64_feature_set *avariant;
745
746 /* An array of operand codes. Each code is an index into the
747 operand table. They appear in the order which the operands must
748 appear in assembly code, and are terminated by a zero. */
749 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
750
751 /* A list of operand qualifier code sequence. Each operand qualifier
752 code qualifies the corresponding operand code. Each operand
753 qualifier sequence specifies a valid opcode variant and related
754 constraint on operands. */
755 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
756
757 /* Flags providing information about this instruction */
eae424ae
TC		 758 uint64_t flags;
759
760 /* Extra constraints on the instruction that the verifier checks. */
761 uint32_t constraints;
4bd13cde 762
0c608d6b
RS		 763 /* If nonzero, this operand and operand 0 are both registers and
764 are required to have the same register number. */
765 unsigned char tied_operand;
766
4bd13cde 767 /* If non-NULL, a function to verify that a given instruction is valid. */
755b748f
TC		 768 enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
769 bfd_vma, bfd_boolean, aarch64_operand_error *,
770 struct aarch64_instr_sequence *);
a06ea964
NC		 771};
772
773typedef struct aarch64_opcode aarch64_opcode;
774
775/* Table describing all the AArch64 opcodes. */
776extern aarch64_opcode aarch64_opcode_table[];
777
778/* Opcode flags. */
779#define F_ALIAS (1 << 0)
780#define F_HAS_ALIAS (1 << 1)
781/* Disassembly preference priority 1-3 (the larger the higher). If nothing
782 is specified, it is the priority 0 by default, i.e. the lowest priority. */
783#define F_P1 (1 << 2)
784#define F_P2 (2 << 2)
785#define F_P3 (3 << 2)
786/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
787#define F_COND (1 << 4)
788/* Instruction has the field of 'sf'. */
789#define F_SF (1 << 5)
790/* Instruction has the field of 'size:Q'. */
791#define F_SIZEQ (1 << 6)
792/* Floating-point instruction has the field of 'type'. */
793#define F_FPTYPE (1 << 7)
794/* AdvSIMD scalar instruction has the field of 'size'. */
795#define F_SSIZE (1 << 8)
796/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
797#define F_T (1 << 9)
798/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
799#define F_GPRSIZE_IN_Q (1 << 10)
800/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
801#define F_LDS_SIZE (1 << 11)
802/* Optional operand; assume maximum of 1 operand can be optional. */
803#define F_OPD0_OPT (1 << 12)
804#define F_OPD1_OPT (2 << 12)
805#define F_OPD2_OPT (3 << 12)
806#define F_OPD3_OPT (4 << 12)
807#define F_OPD4_OPT (5 << 12)
808/* Default value for the optional operand when omitted from the assembly. */
809#define F_DEFAULT(X) (((X) & 0x1f) << 15)
810/* Instruction that is an alias of another instruction needs to be
811 encoded/decoded by converting it to/from the real form, followed by
812 the encoding/decoding according to the rules of the real opcode.
813 This compares to the direct coding using the alias's information.
814 N.B. this flag requires F_ALIAS to be used together. */
815#define F_CONV (1 << 20)
816/* Use together with F_ALIAS to indicate an alias opcode is a programmer
817 friendly pseudo instruction available only in the assembly code (thus will
818 not show up in the disassembly). */
819#define F_PSEUDO (1 << 21)
820/* Instruction has miscellaneous encoding/decoding rules. */
821#define F_MISC (1 << 22)
822/* Instruction has the field of 'N'; used in conjunction with F_SF. */
823#define F_N (1 << 23)
824/* Opcode dependent field. */
825#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 826/* Instruction has the field of 'sz'. */
827#define F_LSE_SZ (1 << 27)
4989adac
RS		 828/* Require an exact qualifier match, even for NIL qualifiers. */
829#define F_STRICT (1ULL << 28)
f9830ec1
TC		 830/* This system instruction is used to read system registers. */
831#define F_SYS_READ (1ULL << 29)
832/* This system instruction is used to write system registers. */
833#define F_SYS_WRITE (1ULL << 30)
eae424ae
TC		 834/* This instruction has an extra constraint on it that imposes a requirement on
835 subsequent instructions. */
836#define F_SCAN (1ULL << 31)
837/* Next bit is 32. */
838
839/* Instruction constraints. */
840/* This instruction has a predication constraint on the instruction at PC+4. */
841#define C_SCAN_MOVPRFX (1U << 0)
842/* This instruction's operation width is determined by the operand with the
843 largest element size. */
844#define C_MAX_ELEM (1U << 1)
845/* Next bit is 2. */
a06ea964
NC		 846
847static inline bfd_boolean
848alias_opcode_p (const aarch64_opcode *opcode)
849{
850 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
851}
852
853static inline bfd_boolean
854opcode_has_alias (const aarch64_opcode *opcode)
855{
856 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
857}
858
859/* Priority for disassembling preference. */
860static inline int
861opcode_priority (const aarch64_opcode *opcode)
862{
863 return (opcode->flags >> 2) & 0x3;
864}
865
866static inline bfd_boolean
867pseudo_opcode_p (const aarch64_opcode *opcode)
868{
869 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
870}
871
872static inline bfd_boolean
873optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
874{
875 return (((opcode->flags >> 12) & 0x7) == idx + 1)
876 ? TRUE : FALSE;
877}
878
879static inline aarch64_insn
880get_optional_operand_default_value (const aarch64_opcode *opcode)
881{
882 return (opcode->flags >> 15) & 0x1f;
883}
884
885static inline unsigned int
886get_opcode_dependent_value (const aarch64_opcode *opcode)
887{
888 return (opcode->flags >> 24) & 0x7;
889}
890
891static inline bfd_boolean
892opcode_has_special_coder (const aarch64_opcode *opcode)
893{
ee804238 894 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 895 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
896 : FALSE;
897}
898\f
899struct aarch64_name_value_pair
900{
901 const char * name;
902 aarch64_insn value;
903};
904
905extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964
NC		 906extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
907extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 908extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 909
49eec193
YZ		 910typedef struct
911{
912 const char * name;
913 aarch64_insn value;
914 uint32_t flags;
915} aarch64_sys_reg;
916
917extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 918extern const aarch64_sys_reg aarch64_pstatefields [];
49eec193 919extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
f21cce2c
MW		 920extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
921 const aarch64_sys_reg *);
922extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
923 const aarch64_sys_reg *);
49eec193 924
a06ea964
NC		 925typedef struct
926{
875880c6 927 const char *name;
a06ea964 928 uint32_t value;
ea2deeec 929 uint32_t flags ;
a06ea964
NC		 930} aarch64_sys_ins_reg;
931
ea2deeec 932extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6
MW		 933extern bfd_boolean
934aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
935 const aarch64_sys_ins_reg *);
ea2deeec 936
a06ea964
NC		 937extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
938extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
939extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
940extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
2ac435d4 941extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
a06ea964
NC		 942
943/* Shift/extending operator kinds.
944 N.B. order is important; keep aarch64_operand_modifiers synced. */
945enum aarch64_modifier_kind
946{
947 AARCH64_MOD_NONE,
948 AARCH64_MOD_MSL,
949 AARCH64_MOD_ROR,
950 AARCH64_MOD_ASR,
951 AARCH64_MOD_LSR,
952 AARCH64_MOD_LSL,
953 AARCH64_MOD_UXTB,
954 AARCH64_MOD_UXTH,
955 AARCH64_MOD_UXTW,
956 AARCH64_MOD_UXTX,
957 AARCH64_MOD_SXTB,
958 AARCH64_MOD_SXTH,
959 AARCH64_MOD_SXTW,
960 AARCH64_MOD_SXTX,
2442d846 961 AARCH64_MOD_MUL,
98907a70 962 AARCH64_MOD_MUL_VL,
a06ea964
NC		 963};
964
965bfd_boolean
966aarch64_extend_operator_p (enum aarch64_modifier_kind);
967
968enum aarch64_modifier_kind
969aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
970/* Condition. */
971
972typedef struct
973{
974 /* A list of names with the first one as the disassembly preference;
975 terminated by NULL if fewer than 3. */
bb7eff52 976 const char *names[4];
a06ea964
NC		 977 aarch64_insn value;
978} aarch64_cond;
979
980extern const aarch64_cond aarch64_conds[16];
981
982const aarch64_cond* get_cond_from_value (aarch64_insn value);
983const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
984\f
985/* Structure representing an operand. */
986
987struct aarch64_opnd_info
988{
989 enum aarch64_opnd type;
990 aarch64_opnd_qualifier_t qualifier;
991 int idx;
992
993 union
994 {
995 struct
996 {
997 unsigned regno;
998 } reg;
999 struct
1000 {
dab26bf4
RS		 1001 unsigned int regno;
1002 int64_t index;
a06ea964
NC		 1003 } reglane;
1004 /* e.g. LVn. */
1005 struct
1006 {
1007 unsigned first_regno : 5;
1008 unsigned num_regs : 3;
1009 /* 1 if it is a list of reg element. */
1010 unsigned has_index : 1;
1011 /* Lane index; valid only when has_index is 1. */
dab26bf4 1012 int64_t index;
a06ea964
NC		 1013 } reglist;
1014 /* e.g. immediate or pc relative address offset. */
1015 struct
1016 {
1017 int64_t value;
1018 unsigned is_fp : 1;
1019 } imm;
1020 /* e.g. address in STR (register offset). */
1021 struct
1022 {
1023 unsigned base_regno;
1024 struct
1025 {
1026 union
1027 {
1028 int imm;
1029 unsigned regno;
1030 };
1031 unsigned is_reg;
1032 } offset;
1033 unsigned pcrel : 1; /* PC-relative. */
1034 unsigned writeback : 1;
1035 unsigned preind : 1; /* Pre-indexed. */
1036 unsigned postind : 1; /* Post-indexed. */
1037 } addr;
561a72d4
TC		 1038
1039 struct
1040 {
1041 /* The encoding of the system register. */
1042 aarch64_insn value;
1043
1044 /* The system register flags. */
1045 uint32_t flags;
1046 } sysreg;
1047
a06ea964 1048 const aarch64_cond *cond;
a06ea964
NC		 1049 /* The encoding of the PSTATE field. */
1050 aarch64_insn pstatefield;
1051 const aarch64_sys_ins_reg *sysins_op;
1052 const struct aarch64_name_value_pair *barrier;
9ed608f9 1053 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 1054 const struct aarch64_name_value_pair *prfop;
1055 };
1056
1057 /* Operand shifter; in use when the operand is a register offset address,
1058 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
1059 struct
1060 {
1061 enum aarch64_modifier_kind kind;
a06ea964
NC		 1062 unsigned operator_present: 1; /* Only valid during encoding. */
1063 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
1064 unsigned amount_present: 1;
2442d846 1065 int64_t amount;
a06ea964
NC		 1066 } shifter;
1067
1068 unsigned skip:1; /* Operand is not completed if there is a fixup needed
1069 to be done on it. In some (but not all) of these
1070 cases, we need to tell libopcodes to skip the
1071 constraint checking and the encoding for this
1072 operand, so that the libopcodes can pick up the
1073 right opcode before the operand is fixed-up. This
1074 flag should only be used during the
1075 assembling/encoding. */
1076 unsigned present:1; /* Whether this operand is present in the assembly
1077 line; not used during the disassembly. */
1078};
1079
1080typedef struct aarch64_opnd_info aarch64_opnd_info;
1081
1082/* Structure representing an instruction.
1083
1084 It is used during both the assembling and disassembling. The assembler
1085 fills an aarch64_inst after a successful parsing and then passes it to the
1086 encoding routine to do the encoding. During the disassembling, the
1087 disassembler calls the decoding routine to decode a binary instruction; on a
1088 successful return, such a structure will be filled with information of the
1089 instruction; then the disassembler uses the information to print out the
1090 instruction. */
1091
1092struct aarch64_inst
1093{
1094 /* The value of the binary instruction. */
1095 aarch64_insn value;
1096
1097 /* Corresponding opcode entry. */
1098 const aarch64_opcode *opcode;
1099
1100 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
1101 const aarch64_cond *cond;
1102
1103 /* Operands information. */
1104 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1105};
1106
ff605452
SD		 1107/* Defining the HINT #imm values for the aarch64_hint_options. */
1108#define HINT_OPD_CSYNC 0x11
1109#define HINT_OPD_C 0x22
1110#define HINT_OPD_J 0x24
1111#define HINT_OPD_JC 0x26
1112#define HINT_OPD_NULL 0x00
1113
a06ea964
NC		 1114\f
1115/* Diagnosis related declaration and interface. */
1116
1117/* Operand error kind enumerators.
1118
1119 AARCH64_OPDE_RECOVERABLE
1120 Less severe error found during the parsing, very possibly because that
1121 GAS has picked up a wrong instruction template for the parsing.
1122
1123 AARCH64_OPDE_SYNTAX_ERROR
1124 General syntax error; it can be either a user error, or simply because
1125 that GAS is trying a wrong instruction template.
1126
1127 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1128 Definitely a user syntax error.
1129
1130 AARCH64_OPDE_INVALID_VARIANT
1131 No syntax error, but the operands are not a valid combination, e.g.
1132 FMOV D0,S0
1133
0c608d6b
RS		 1134 AARCH64_OPDE_UNTIED_OPERAND
1135 The asm failed to use the same register for a destination operand
1136 and a tied source operand.
1137
a06ea964
NC		 1138 AARCH64_OPDE_OUT_OF_RANGE
1139 Error about some immediate value out of a valid range.
1140
1141 AARCH64_OPDE_UNALIGNED
1142 Error about some immediate value not properly aligned (i.e. not being a
1143 multiple times of a certain value).
1144
1145 AARCH64_OPDE_REG_LIST
1146 Error about the register list operand having unexpected number of
1147 registers.
1148
1149 AARCH64_OPDE_OTHER_ERROR
1150 Error of the highest severity and used for any severe issue that does not
1151 fall into any of the above categories.
1152
1153 The enumerators are only interesting to GAS. They are declared here (in
1154 libopcodes) because that some errors are detected (and then notified to GAS)
1155 by libopcodes (rather than by GAS solely).
1156
1157 The first three errors are only deteced by GAS while the
1158 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1159 only libopcodes has the information about the valid variants of each
1160 instruction.
1161
1162 The enumerators have an increasing severity. This is helpful when there are
1163 multiple instruction templates available for a given mnemonic name (e.g.
1164 FMOV); this mechanism will help choose the most suitable template from which
1165 the generated diagnostics can most closely describe the issues, if any. */
1166
1167enum aarch64_operand_error_kind
1168{
1169 AARCH64_OPDE_NIL,
1170 AARCH64_OPDE_RECOVERABLE,
1171 AARCH64_OPDE_SYNTAX_ERROR,
1172 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1173 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1174 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1175 AARCH64_OPDE_OUT_OF_RANGE,
1176 AARCH64_OPDE_UNALIGNED,
1177 AARCH64_OPDE_REG_LIST,
1178 AARCH64_OPDE_OTHER_ERROR
1179};
1180
1181/* N.B. GAS assumes that this structure work well with shallow copy. */
1182struct aarch64_operand_error
1183{
1184 enum aarch64_operand_error_kind kind;
1185 int index;
1186 const char *error;
1187 int data[3]; /* Some data for extra information. */
7d02540a 1188 bfd_boolean non_fatal;
a06ea964
NC		 1189};
1190
7e84b55d
TC		 1191/* AArch64 sequence structure used to track instructions with F_SCAN
1192 dependencies for both assembler and disassembler. */
1193struct aarch64_instr_sequence
1194{
1195 /* The instruction that caused this sequence to be opened. */
1196 aarch64_inst *instr;
1197 /* The number of instructions the above instruction allows to be kept in the
1198 sequence before an automatic close is done. */
1199 int num_insns;
1200 /* The instructions currently added to the sequence. */
1201 aarch64_inst **current_insns;
1202 /* The number of instructions already in the sequence. */
1203 int next_insn;
1204};
a06ea964
NC		 1205
1206/* Encoding entrypoint. */
1207
1208extern int
1209aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1210 aarch64_insn *, aarch64_opnd_qualifier_t *,
7e84b55d 1211 aarch64_operand_error *, aarch64_instr_sequence *);
a06ea964
NC		 1212
1213extern const aarch64_opcode *
1214aarch64_replace_opcode (struct aarch64_inst *,
1215 const aarch64_opcode *);
1216
1217/* Given the opcode enumerator OP, return the pointer to the corresponding
1218 opcode entry. */
1219
1220extern const aarch64_opcode *
1221aarch64_get_opcode (enum aarch64_op);
1222
1223/* Generate the string representation of an operand. */
1224extern void
1225aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
7d02540a
TC		 1226 const aarch64_opnd_info *, int, int *, bfd_vma *,
1227 char **);
a06ea964
NC		 1228
1229/* Miscellaneous interface. */
1230
1231extern int
1232aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1233
1234extern aarch64_opnd_qualifier_t
1235aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1236 const aarch64_opnd_qualifier_t, int);
1237
a68f4cd2
TC		 1238extern bfd_boolean
1239aarch64_is_destructive_by_operands (const aarch64_opcode *);
1240
a06ea964
NC		 1241extern int
1242aarch64_num_of_operands (const aarch64_opcode *);
1243
1244extern int
1245aarch64_stack_pointer_p (const aarch64_opnd_info *);
1246
e141d84e
YQ		 1247extern int
1248aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1249
1d482394 1250extern enum err_type
561a72d4 1251aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
a68f4cd2
TC		 1252 aarch64_operand_error *);
1253
1254extern void
1255init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
36f4aab1 1256
a06ea964
NC		 1257/* Given an operand qualifier, return the expected data element size
1258 of a qualified operand. */
1259extern unsigned char
1260aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1261
1262extern enum aarch64_operand_class
1263aarch64_get_operand_class (enum aarch64_opnd);
1264
1265extern const char *
1266aarch64_get_operand_name (enum aarch64_opnd);
1267
1268extern const char *
1269aarch64_get_operand_desc (enum aarch64_opnd);
1270
e950b345
RS		 1271extern bfd_boolean
1272aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1273
a06ea964
NC		 1274#ifdef DEBUG_AARCH64
1275extern int debug_dump;
1276
1277extern void
1278aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1279
1280#define DEBUG_TRACE(M, ...) \
1281 { \
1282 if (debug_dump) \
1283 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1284 }
1285
1286#define DEBUG_TRACE_IF(C, M, ...) \
1287 { \
1288 if (debug_dump && (C)) \
1289 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1290 }
1291#else /* !DEBUG_AARCH64 */
1292#define DEBUG_TRACE(M, ...) ;
1293#define DEBUG_TRACE_IF(C, M, ...) ;
1294#endif /* DEBUG_AARCH64 */
1295
245d2e3f
RS		 1296extern const char *const aarch64_sve_pattern_array[32];
1297extern const char *const aarch64_sve_prfop_array[16];
1298
d3e12b29
YQ		 1299#ifdef __cplusplus
1300}
1301#endif
1302
a06ea964 1303#endif /* OPCODE_AARCH64_H */
GDB Binutils - Deliverables
This page took 0.368723 seconds and 4 git commands to generate.