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[binutils][aarch64] New SVE_Zm3_11_INDEX operand.
[deliverable/binutils-gdb.git] / include / opcode / aarch64.h
CommitLineData
a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
82704155 3 Copyright (C) 2009-2019 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
c0e7cef7
NC		 40#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
41#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
b6b9ca0c
TC		 42#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
43#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
44#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
a06ea964 45#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
acb787b0 46#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
1924ff75 47#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
a06ea964
NC		 48#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
49#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
50#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
e60bb1dd 51#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
ee804238 52#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
f21cce2c 53#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
290806fd 54#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
9e1f0fa7 55#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
250aafa4 56#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
af117b3c 57#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
c8a6db6f 58#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
73af8ed6 59#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
c0890d26 60#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
d74d4880 61#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
f482d304 62#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
65a55fbb 63#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
d0f7791c 64#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */
70d56181 65#define AARCH64_FEATURE_V8_5 0x2000000000ULL /* ARMv8.5 processors. */
a06ea964 66
13c60ad7
SD		 67/* Flag Manipulation insns. */
68#define AARCH64_FEATURE_FLAGMANIP 0x4000000000ULL
69/* FRINT[32,64][Z,X] insns. */
70#define AARCH64_FEATURE_FRINTTS 0x8000000000ULL
68dfbb92
SD		 71/* SB instruction. */
72#define AARCH64_FEATURE_SB 0x10000000000ULL
2ac435d4
SD		 73/* Execution and Data Prediction Restriction instructions. */
74#define AARCH64_FEATURE_PREDRES 0x20000000000ULL
3fd229a4
SD		 75/* DC CVADP. */
76#define AARCH64_FEATURE_CVADP 0x40000000000ULL
af4bcb4c
SD		 77/* Random Number instructions. */
78#define AARCH64_FEATURE_RNG 0x80000000000ULL
ff605452
SD		 79/* BTI instructions. */
80#define AARCH64_FEATURE_BTI 0x100000000000ULL
a97330e7
SD		 81/* SCXTNUM_ELx. */
82#define AARCH64_FEATURE_SCXTNUM 0x200000000000ULL
83/* ID_PFR2 instructions. */
84#define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL
104fefee
SD		 85/* SSBS mechanism enabled. */
86#define AARCH64_FEATURE_SSBS 0x800000000000ULL
73b605ec
SD		 87/* Memory Tagging Extension. */
88#define AARCH64_FEATURE_MEMTAG 0x1000000000000ULL
b83b4b13
SD		 89/* Transactional Memory Extension. */
90#define AARCH64_FEATURE_TME 0x2000000000000ULL
13c60ad7 91
7ce2460a
MM		 92/* SVE2 instructions. */
93#define AARCH64_FEATURE_SVE2 0x000000010
94#define AARCH64_FEATURE_SVE2_AES 0x000000080
95#define AARCH64_FEATURE_SVE2_BITPERM 0x000000100
96#define AARCH64_FEATURE_SVE2_SM4 0x000000200
97#define AARCH64_FEATURE_SVE2_SHA3 0x000000400
98
a06ea964
NC		 99/* Architectures are the sum of the base and extensions. */
100#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
101 AARCH64_FEATURE_FP \
102 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 103#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
104 AARCH64_FEATURE_CRC \
250aafa4 105 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 106 | AARCH64_FEATURE_LSE \
107 | AARCH64_FEATURE_PAN \
108 | AARCH64_FEATURE_LOR \
109 | AARCH64_FEATURE_RDMA)
1924ff75 110#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 111 AARCH64_FEATURE_V8_2 \
1924ff75
SN		 112 | AARCH64_FEATURE_RAS)
113#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
d74d4880 114 AARCH64_FEATURE_V8_3 \
f482d304
RS		 115 | AARCH64_FEATURE_RCPC \
116 | AARCH64_FEATURE_COMPNUM)
b6b9ca0c 117#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
981b557a 118 AARCH64_FEATURE_V8_4 \
d0f7791c
TC		 119 | AARCH64_FEATURE_DOTPROD \
120 | AARCH64_FEATURE_F16_FML)
70d56181 121#define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
13c60ad7
SD		 122 AARCH64_FEATURE_V8_5 \
123 | AARCH64_FEATURE_FLAGMANIP \
68dfbb92 124 | AARCH64_FEATURE_FRINTTS \
2ac435d4 125 | AARCH64_FEATURE_SB \
3fd229a4 126 | AARCH64_FEATURE_PREDRES \
ff605452 127 | AARCH64_FEATURE_CVADP \
a97330e7
SD		 128 | AARCH64_FEATURE_BTI \
129 | AARCH64_FEATURE_SCXTNUM \
104fefee
SD		 130 | AARCH64_FEATURE_ID_PFR2 \
131 | AARCH64_FEATURE_SSBS)
70d56181 132
88f0ea34 133
a06ea964
NC		 134#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
135#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
136
137/* CPU-specific features. */
21b81e67 138typedef unsigned long long aarch64_feature_set;
a06ea964 139
93d8990c
SN		 140#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
141 ((~(CPU) & (FEAT)) == 0)
142
143#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 144 (((CPU) & (FEAT)) != 0)
145
93d8990c
SN		 146#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
147 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
148
a06ea964
NC		 149#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
150 do \
151 { \
152 (TARG) = (F1) | (F2); \
153 } \
154 while (0)
155
156#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
157 do \
158 { \
159 (TARG) = (F1) &~ (F2); \
160 } \
161 while (0)
162
163#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
164
a06ea964
NC		 165enum aarch64_operand_class
166{
167 AARCH64_OPND_CLASS_NIL,
168 AARCH64_OPND_CLASS_INT_REG,
169 AARCH64_OPND_CLASS_MODIFIED_REG,
170 AARCH64_OPND_CLASS_FP_REG,
171 AARCH64_OPND_CLASS_SIMD_REG,
172 AARCH64_OPND_CLASS_SIMD_ELEMENT,
173 AARCH64_OPND_CLASS_SISD_REG,
174 AARCH64_OPND_CLASS_SIMD_REGLIST,
f11ad6bc
RS		 175 AARCH64_OPND_CLASS_SVE_REG,
176 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 177 AARCH64_OPND_CLASS_ADDRESS,
178 AARCH64_OPND_CLASS_IMMEDIATE,
179 AARCH64_OPND_CLASS_SYSTEM,
68a64283 180 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 181};
182
183/* Operand code that helps both parsing and coding.
184 Keep AARCH64_OPERANDS synced. */
185
186enum aarch64_opnd
187{
188 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
189
190 AARCH64_OPND_Rd, /* Integer register as destination. */
191 AARCH64_OPND_Rn, /* Integer register as source. */
192 AARCH64_OPND_Rm, /* Integer register as source. */
193 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
194 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
bd7ceb8d 195 AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */
a06ea964
NC		 196 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
197 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
198 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
199
200 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
201 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 202 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 203 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 204 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
205 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
206
207 AARCH64_OPND_Fd, /* Floating-point Fd. */
208 AARCH64_OPND_Fn, /* Floating-point Fn. */
209 AARCH64_OPND_Fm, /* Floating-point Fm. */
210 AARCH64_OPND_Fa, /* Floating-point Fa. */
211 AARCH64_OPND_Ft, /* Floating-point Ft. */
212 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
213
214 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
215 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
216 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
217
f42f1a1d 218 AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
a06ea964
NC		 219 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
220 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
221 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
222 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
223 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
224 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
225 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
226 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
369c9167
TC		 227 AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
228 qualifier is S_H. */
a06ea964
NC		 229 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
230 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
231 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
232 structure to all lanes. */
233 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
234
a6a51754
RL		 235 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
236 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
a06ea964
NC		 237
238 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
f42f1a1d 239 AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */
a06ea964
NC		 240 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
241 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
242 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
243 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
244 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
245 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
246 (no encoding). */
247 AARCH64_OPND_IMM0, /* Immediate for #0. */
248 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
249 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
250 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
251 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
252 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
253 AARCH64_OPND_IMM, /* Immediate. */
f42f1a1d 254 AARCH64_OPND_IMM_2, /* Immediate. */
a06ea964
NC		 255 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
256 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
257 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
193614f2 258 AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */
a06ea964 259 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
193614f2 260 AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */
a06ea964
NC		 261 AARCH64_OPND_BIT_NUM, /* Immediate. */
262 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
263 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 264 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 265 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
266 each condition flag. */
267
268 AARCH64_OPND_LIMM, /* Logical Immediate. */
269 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
270 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
271 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
272 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
c2c4ff8d
SN		 273 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
274 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
275 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
a06ea964
NC		 276
277 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 278 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 279
280 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
281 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
282 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
283 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
284 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
285
286 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
287 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
288 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
289 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
290 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
291 negative or unaligned and there is
292 no writeback allowed. This operand code
293 is only used to support the programmer-
294 friendly feature of using LDR/STR as the
295 the mnemonic name for LDUR/STUR instructions
296 wherever there is no ambiguity. */
3f06e550 297 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
fb3265b3
SD		 298 AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of
299 16) immediate. */
a06ea964 300 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
fb3265b3
SD		 301 AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of
302 16) immediate. */
a06ea964 303 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
f42f1a1d 304 AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
a06ea964
NC		 305 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
306
307 AARCH64_OPND_SYSREG, /* System register operand. */
308 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
309 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
310 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
311 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
312 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
2ac435d4 313 AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
a06ea964
NC		 314 AARCH64_OPND_BARRIER, /* Barrier operand. */
315 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
316 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 317 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
ff605452 318 AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
f11ad6bc 319
582e12bf 320 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
98907a70
RS		 321 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
322 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
323 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
324 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
325 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
326 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 327 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
328 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
329 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
330 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
c8d59609 331 AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */
4df068de
RS		 332 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
333 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
334 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
335 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
336 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
337 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
338 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
339 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
340 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
341 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
342 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
343 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
344 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
345 Bit 14 controls S/U choice. */
346 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
347 Bit 22 controls S/U choice. */
348 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
349 Bit 14 controls S/U choice. */
350 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
351 Bit 22 controls S/U choice. */
352 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
353 Bit 14 controls S/U choice. */
354 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
355 Bit 22 controls S/U choice. */
356 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
357 Bit 14 controls S/U choice. */
358 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
359 Bit 22 controls S/U choice. */
360 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
361 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
362 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
363 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
364 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
365 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
366 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 367 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
368 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 369 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
370 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
371 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
372 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
582e12bf
RS		 373 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
374 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
adccc507 375 AARCH64_OPND_SVE_IMM_ROT3, /* SVE cadd 1-bit rotate (90 or 270). */
e950b345
RS		 376 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
377 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
378 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 379 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 380 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 381 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 382 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
383 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
384 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
385 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
386 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
387 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
388 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
389 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 390 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
391 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 392 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
393 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
394 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
395 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
396 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
397 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
398 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
399 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
400 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
401 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
402 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
403 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 404 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
405 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
406 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
407 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 408 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
409 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
410 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
411 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
412 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
582e12bf
RS		 413 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
414 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
116adc27 415 AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */
582e12bf 416 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
f11ad6bc
RS		 417 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
418 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
419 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
420 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
421 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
b83b4b13 422 AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
f42f1a1d 423 AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
a06ea964
NC		 424};
425
426/* Qualifier constrains an operand. It either specifies a variant of an
427 operand type or limits values available to an operand type.
428
429 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
430
431enum aarch64_opnd_qualifier
432{
433 /* Indicating no further qualification on an operand. */
434 AARCH64_OPND_QLF_NIL,
435
436 /* Qualifying an operand which is a general purpose (integer) register;
437 indicating the operand data size or a specific register. */
438 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
439 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
440 AARCH64_OPND_QLF_WSP, /* WSP. */
441 AARCH64_OPND_QLF_SP, /* SP. */
442
443 /* Qualifying an operand which is a floating-point register, a SIMD
444 vector element or a SIMD vector element list; indicating operand data
445 size or the size of each SIMD vector element in the case of a SIMD
446 vector element list.
447 These qualifiers are also used to qualify an address operand to
448 indicate the size of data element a load/store instruction is
449 accessing.
450 They are also used for the immediate shift operand in e.g. SSHR. Such
451 a use is only for the ease of operand encoding/decoding and qualifier
452 sequence matching; such a use should not be applied widely; use the value
453 constraint qualifiers for immediate operands wherever possible. */
454 AARCH64_OPND_QLF_S_B,
455 AARCH64_OPND_QLF_S_H,
456 AARCH64_OPND_QLF_S_S,
457 AARCH64_OPND_QLF_S_D,
458 AARCH64_OPND_QLF_S_Q,
00c2093f
TC		 459 /* This type qualifier has a special meaning in that it means that 4 x 1 byte
460 are selected by the instruction. Other than that it has no difference
461 with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical
462 reasons and is an exception from normal AArch64 disassembly scheme. */
463 AARCH64_OPND_QLF_S_4B,
a06ea964
NC		 464
465 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
466 register list; indicating register shape.
467 They are also used for the immediate shift operand in e.g. SSHR. Such
468 a use is only for the ease of operand encoding/decoding and qualifier
469 sequence matching; such a use should not be applied widely; use the value
470 constraint qualifiers for immediate operands wherever possible. */
a3b3345a 471 AARCH64_OPND_QLF_V_4B,
a06ea964
NC		 472 AARCH64_OPND_QLF_V_8B,
473 AARCH64_OPND_QLF_V_16B,
3067d3b9 474 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 475 AARCH64_OPND_QLF_V_4H,
476 AARCH64_OPND_QLF_V_8H,
477 AARCH64_OPND_QLF_V_2S,
478 AARCH64_OPND_QLF_V_4S,
479 AARCH64_OPND_QLF_V_1D,
480 AARCH64_OPND_QLF_V_2D,
481 AARCH64_OPND_QLF_V_1Q,
482
d50c751e
RS		 483 AARCH64_OPND_QLF_P_Z,
484 AARCH64_OPND_QLF_P_M,
fb3265b3
SD		 485
486 /* Used in scaled signed immediate that are scaled by a Tag granule
487 like in stg, st2g, etc. */
488 AARCH64_OPND_QLF_imm_tag,
d50c751e 489
a06ea964 490 /* Constraint on value. */
a6a51754 491 AARCH64_OPND_QLF_CR, /* CRn, CRm. */
a06ea964
NC		 492 AARCH64_OPND_QLF_imm_0_7,
493 AARCH64_OPND_QLF_imm_0_15,
494 AARCH64_OPND_QLF_imm_0_31,
495 AARCH64_OPND_QLF_imm_0_63,
496 AARCH64_OPND_QLF_imm_1_32,
497 AARCH64_OPND_QLF_imm_1_64,
498
499 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
500 or shift-ones. */
501 AARCH64_OPND_QLF_LSL,
502 AARCH64_OPND_QLF_MSL,
503
504 /* Special qualifier helping retrieve qualifier information during the
505 decoding time (currently not in use). */
506 AARCH64_OPND_QLF_RETRIEVE,
507};
508\f
509/* Instruction class. */
510
511enum aarch64_insn_class
512{
513 addsub_carry,
514 addsub_ext,
515 addsub_imm,
516 addsub_shift,
517 asimdall,
518 asimddiff,
519 asimdelem,
520 asimdext,
521 asimdimm,
522 asimdins,
523 asimdmisc,
524 asimdperm,
525 asimdsame,
526 asimdshf,
527 asimdtbl,
528 asisddiff,
529 asisdelem,
530 asisdlse,
531 asisdlsep,
532 asisdlso,
533 asisdlsop,
534 asisdmisc,
535 asisdone,
536 asisdpair,
537 asisdsame,
538 asisdshf,
539 bitfield,
540 branch_imm,
541 branch_reg,
542 compbranch,
543 condbranch,
544 condcmp_imm,
545 condcmp_reg,
546 condsel,
547 cryptoaes,
548 cryptosha2,
549 cryptosha3,
550 dp_1src,
551 dp_2src,
552 dp_3src,
553 exception,
554 extract,
555 float2fix,
556 float2int,
557 floatccmp,
558 floatcmp,
559 floatdp1,
560 floatdp2,
561 floatdp3,
562 floatimm,
563 floatsel,
564 ldst_immpost,
565 ldst_immpre,
566 ldst_imm9, /* immpost or immpre */
3f06e550 567 ldst_imm10, /* LDRAA/LDRAB */
a06ea964
NC		 568 ldst_pos,
569 ldst_regoff,
570 ldst_unpriv,
571 ldst_unscaled,
572 ldstexcl,
573 ldstnapair_offs,
574 ldstpair_off,
575 ldstpair_indexed,
576 loadlit,
577 log_imm,
578 log_shift,
ee804238 579 lse_atomic,
a06ea964
NC		 580 movewide,
581 pcreladdr,
582 ic_system,
116b6019
RS		 583 sve_cpy,
584 sve_index,
585 sve_limm,
586 sve_misc,
587 sve_movprfx,
588 sve_pred_zm,
589 sve_shift_pred,
590 sve_shift_unpred,
591 sve_size_bhs,
592 sve_size_bhsd,
593 sve_size_hsd,
3bd82c86 594 sve_size_hsd2,
116b6019 595 sve_size_sd,
a06ea964 596 testbranch,
f42f1a1d
TC		 597 cryptosm3,
598 cryptosm4,
65a55fbb 599 dotproduct,
a06ea964
NC		 600};
601
602/* Opcode enumerators. */
603
604enum aarch64_op
605{
606 OP_NIL,
607 OP_STRB_POS,
608 OP_LDRB_POS,
609 OP_LDRSB_POS,
610 OP_STRH_POS,
611 OP_LDRH_POS,
612 OP_LDRSH_POS,
613 OP_STR_POS,
614 OP_LDR_POS,
615 OP_STRF_POS,
616 OP_LDRF_POS,
617 OP_LDRSW_POS,
618 OP_PRFM_POS,
619
620 OP_STURB,
621 OP_LDURB,
622 OP_LDURSB,
623 OP_STURH,
624 OP_LDURH,
625 OP_LDURSH,
626 OP_STUR,
627 OP_LDUR,
628 OP_STURV,
629 OP_LDURV,
630 OP_LDURSW,
631 OP_PRFUM,
632
633 OP_LDR_LIT,
634 OP_LDRV_LIT,
635 OP_LDRSW_LIT,
636 OP_PRFM_LIT,
637
638 OP_ADD,
639 OP_B,
640 OP_BL,
641
642 OP_MOVN,
643 OP_MOVZ,
644 OP_MOVK,
645
646 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
647 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
648 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
649
650 OP_MOV_V, /* MOV alias for moving vector register. */
651
652 OP_ASR_IMM,
653 OP_LSR_IMM,
654 OP_LSL_IMM,
655
656 OP_BIC,
657
658 OP_UBFX,
659 OP_BFXIL,
660 OP_SBFX,
661 OP_SBFIZ,
662 OP_BFI,
d685192a 663 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 664 OP_UBFIZ,
665 OP_UXTB,
666 OP_UXTH,
667 OP_UXTW,
668
a06ea964
NC		 669 OP_CINC,
670 OP_CINV,
671 OP_CNEG,
672 OP_CSET,
673 OP_CSETM,
674
675 OP_FCVT,
676 OP_FCVTN,
677 OP_FCVTN2,
678 OP_FCVTL,
679 OP_FCVTL2,
680 OP_FCVTXN_S, /* Scalar version. */
681
682 OP_ROR_IMM,
683
e30181a5
YZ		 684 OP_SXTL,
685 OP_SXTL2,
686 OP_UXTL,
687 OP_UXTL2,
688
c0890d26
RS		 689 OP_MOV_P_P,
690 OP_MOV_Z_P_Z,
691 OP_MOV_Z_V,
692 OP_MOV_Z_Z,
693 OP_MOV_Z_Zi,
694 OP_MOVM_P_P_P,
695 OP_MOVS_P_P,
696 OP_MOVZS_P_P_P,
697 OP_MOVZ_P_P_P,
698 OP_NOTS_P_P_P_Z,
699 OP_NOT_P_P_P_Z,
700
c2c4ff8d
SN		 701 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
702
a06ea964
NC		 703 OP_TOTAL_NUM, /* Pseudo. */
704};
705
1d482394
TC		 706/* Error types. */
707enum err_type
708{
709 ERR_OK,
710 ERR_UND,
711 ERR_UNP,
712 ERR_NYI,
a68f4cd2 713 ERR_VFI,
1d482394
TC		 714 ERR_NR_ENTRIES
715};
716
a06ea964
NC		 717/* Maximum number of operands an instruction can have. */
718#define AARCH64_MAX_OPND_NUM 6
719/* Maximum number of qualifier sequences an instruction can have. */
720#define AARCH64_MAX_QLF_SEQ_NUM 10
721/* Operand qualifier typedef; optimized for the size. */
722typedef unsigned char aarch64_opnd_qualifier_t;
723/* Operand qualifier sequence typedef. */
724typedef aarch64_opnd_qualifier_t \
725 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
726
727/* FIXME: improve the efficiency. */
728static inline bfd_boolean
729empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
730{
731 int i;
732 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
733 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
734 return FALSE;
735 return TRUE;
736}
737
7e84b55d
TC		 738/* Forward declare error reporting type. */
739typedef struct aarch64_operand_error aarch64_operand_error;
740/* Forward declare instruction sequence type. */
741typedef struct aarch64_instr_sequence aarch64_instr_sequence;
742/* Forward declare instruction definition. */
743typedef struct aarch64_inst aarch64_inst;
744
a06ea964
NC		 745/* This structure holds information for a particular opcode. */
746
747struct aarch64_opcode
748{
749 /* The name of the mnemonic. */
750 const char *name;
751
752 /* The opcode itself. Those bits which will be filled in with
753 operands are zeroes. */
754 aarch64_insn opcode;
755
756 /* The opcode mask. This is used by the disassembler. This is a
757 mask containing ones indicating those bits which must match the
758 opcode field, and zeroes indicating those bits which need not
759 match (and are presumably filled in by operands). */
760 aarch64_insn mask;
761
762 /* Instruction class. */
763 enum aarch64_insn_class iclass;
764
765 /* Enumerator identifier. */
766 enum aarch64_op op;
767
768 /* Which architecture variant provides this instruction. */
769 const aarch64_feature_set *avariant;
770
771 /* An array of operand codes. Each code is an index into the
772 operand table. They appear in the order which the operands must
773 appear in assembly code, and are terminated by a zero. */
774 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
775
776 /* A list of operand qualifier code sequence. Each operand qualifier
777 code qualifies the corresponding operand code. Each operand
778 qualifier sequence specifies a valid opcode variant and related
779 constraint on operands. */
780 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
781
782 /* Flags providing information about this instruction */
eae424ae
TC		 783 uint64_t flags;
784
785 /* Extra constraints on the instruction that the verifier checks. */
786 uint32_t constraints;
4bd13cde 787
0c608d6b
RS		 788 /* If nonzero, this operand and operand 0 are both registers and
789 are required to have the same register number. */
790 unsigned char tied_operand;
791
4bd13cde 792 /* If non-NULL, a function to verify that a given instruction is valid. */
755b748f
TC		 793 enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
794 bfd_vma, bfd_boolean, aarch64_operand_error *,
795 struct aarch64_instr_sequence *);
a06ea964
NC		 796};
797
798typedef struct aarch64_opcode aarch64_opcode;
799
800/* Table describing all the AArch64 opcodes. */
801extern aarch64_opcode aarch64_opcode_table[];
802
803/* Opcode flags. */
804#define F_ALIAS (1 << 0)
805#define F_HAS_ALIAS (1 << 1)
806/* Disassembly preference priority 1-3 (the larger the higher). If nothing
807 is specified, it is the priority 0 by default, i.e. the lowest priority. */
808#define F_P1 (1 << 2)
809#define F_P2 (2 << 2)
810#define F_P3 (3 << 2)
811/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
812#define F_COND (1 << 4)
813/* Instruction has the field of 'sf'. */
814#define F_SF (1 << 5)
815/* Instruction has the field of 'size:Q'. */
816#define F_SIZEQ (1 << 6)
817/* Floating-point instruction has the field of 'type'. */
818#define F_FPTYPE (1 << 7)
819/* AdvSIMD scalar instruction has the field of 'size'. */
820#define F_SSIZE (1 << 8)
821/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
822#define F_T (1 << 9)
823/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
824#define F_GPRSIZE_IN_Q (1 << 10)
825/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
826#define F_LDS_SIZE (1 << 11)
827/* Optional operand; assume maximum of 1 operand can be optional. */
828#define F_OPD0_OPT (1 << 12)
829#define F_OPD1_OPT (2 << 12)
830#define F_OPD2_OPT (3 << 12)
831#define F_OPD3_OPT (4 << 12)
832#define F_OPD4_OPT (5 << 12)
833/* Default value for the optional operand when omitted from the assembly. */
834#define F_DEFAULT(X) (((X) & 0x1f) << 15)
835/* Instruction that is an alias of another instruction needs to be
836 encoded/decoded by converting it to/from the real form, followed by
837 the encoding/decoding according to the rules of the real opcode.
838 This compares to the direct coding using the alias's information.
839 N.B. this flag requires F_ALIAS to be used together. */
840#define F_CONV (1 << 20)
841/* Use together with F_ALIAS to indicate an alias opcode is a programmer
842 friendly pseudo instruction available only in the assembly code (thus will
843 not show up in the disassembly). */
844#define F_PSEUDO (1 << 21)
845/* Instruction has miscellaneous encoding/decoding rules. */
846#define F_MISC (1 << 22)
847/* Instruction has the field of 'N'; used in conjunction with F_SF. */
848#define F_N (1 << 23)
849/* Opcode dependent field. */
850#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 851/* Instruction has the field of 'sz'. */
852#define F_LSE_SZ (1 << 27)
4989adac
RS		 853/* Require an exact qualifier match, even for NIL qualifiers. */
854#define F_STRICT (1ULL << 28)
f9830ec1
TC		 855/* This system instruction is used to read system registers. */
856#define F_SYS_READ (1ULL << 29)
857/* This system instruction is used to write system registers. */
858#define F_SYS_WRITE (1ULL << 30)
eae424ae
TC		 859/* This instruction has an extra constraint on it that imposes a requirement on
860 subsequent instructions. */
861#define F_SCAN (1ULL << 31)
862/* Next bit is 32. */
863
864/* Instruction constraints. */
865/* This instruction has a predication constraint on the instruction at PC+4. */
866#define C_SCAN_MOVPRFX (1U << 0)
867/* This instruction's operation width is determined by the operand with the
868 largest element size. */
869#define C_MAX_ELEM (1U << 1)
870/* Next bit is 2. */
a06ea964
NC		 871
872static inline bfd_boolean
873alias_opcode_p (const aarch64_opcode *opcode)
874{
875 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
876}
877
878static inline bfd_boolean
879opcode_has_alias (const aarch64_opcode *opcode)
880{
881 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
882}
883
884/* Priority for disassembling preference. */
885static inline int
886opcode_priority (const aarch64_opcode *opcode)
887{
888 return (opcode->flags >> 2) & 0x3;
889}
890
891static inline bfd_boolean
892pseudo_opcode_p (const aarch64_opcode *opcode)
893{
894 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
895}
896
897static inline bfd_boolean
898optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
899{
900 return (((opcode->flags >> 12) & 0x7) == idx + 1)
901 ? TRUE : FALSE;
902}
903
904static inline aarch64_insn
905get_optional_operand_default_value (const aarch64_opcode *opcode)
906{
907 return (opcode->flags >> 15) & 0x1f;
908}
909
910static inline unsigned int
911get_opcode_dependent_value (const aarch64_opcode *opcode)
912{
913 return (opcode->flags >> 24) & 0x7;
914}
915
916static inline bfd_boolean
917opcode_has_special_coder (const aarch64_opcode *opcode)
918{
ee804238 919 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 920 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
921 : FALSE;
922}
923\f
924struct aarch64_name_value_pair
925{
926 const char * name;
927 aarch64_insn value;
928};
929
930extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964
NC		 931extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
932extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 933extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 934
49eec193
YZ		 935typedef struct
936{
937 const char * name;
938 aarch64_insn value;
939 uint32_t flags;
940} aarch64_sys_reg;
941
942extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 943extern const aarch64_sys_reg aarch64_pstatefields [];
49eec193 944extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
f21cce2c
MW		 945extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
946 const aarch64_sys_reg *);
947extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
948 const aarch64_sys_reg *);
49eec193 949
a06ea964
NC		 950typedef struct
951{
875880c6 952 const char *name;
a06ea964 953 uint32_t value;
ea2deeec 954 uint32_t flags ;
a06ea964
NC		 955} aarch64_sys_ins_reg;
956
ea2deeec 957extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6
MW		 958extern bfd_boolean
959aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
960 const aarch64_sys_ins_reg *);
ea2deeec 961
a06ea964
NC		 962extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
963extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
964extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
965extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
2ac435d4 966extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
a06ea964
NC		 967
968/* Shift/extending operator kinds.
969 N.B. order is important; keep aarch64_operand_modifiers synced. */
970enum aarch64_modifier_kind
971{
972 AARCH64_MOD_NONE,
973 AARCH64_MOD_MSL,
974 AARCH64_MOD_ROR,
975 AARCH64_MOD_ASR,
976 AARCH64_MOD_LSR,
977 AARCH64_MOD_LSL,
978 AARCH64_MOD_UXTB,
979 AARCH64_MOD_UXTH,
980 AARCH64_MOD_UXTW,
981 AARCH64_MOD_UXTX,
982 AARCH64_MOD_SXTB,
983 AARCH64_MOD_SXTH,
984 AARCH64_MOD_SXTW,
985 AARCH64_MOD_SXTX,
2442d846 986 AARCH64_MOD_MUL,
98907a70 987 AARCH64_MOD_MUL_VL,
a06ea964
NC		 988};
989
990bfd_boolean
991aarch64_extend_operator_p (enum aarch64_modifier_kind);
992
993enum aarch64_modifier_kind
994aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
995/* Condition. */
996
997typedef struct
998{
999 /* A list of names with the first one as the disassembly preference;
1000 terminated by NULL if fewer than 3. */
bb7eff52 1001 const char *names[4];
a06ea964
NC		 1002 aarch64_insn value;
1003} aarch64_cond;
1004
1005extern const aarch64_cond aarch64_conds[16];
1006
1007const aarch64_cond* get_cond_from_value (aarch64_insn value);
1008const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
1009\f
1010/* Structure representing an operand. */
1011
1012struct aarch64_opnd_info
1013{
1014 enum aarch64_opnd type;
1015 aarch64_opnd_qualifier_t qualifier;
1016 int idx;
1017
1018 union
1019 {
1020 struct
1021 {
1022 unsigned regno;
1023 } reg;
1024 struct
1025 {
dab26bf4
RS		 1026 unsigned int regno;
1027 int64_t index;
a06ea964
NC		 1028 } reglane;
1029 /* e.g. LVn. */
1030 struct
1031 {
1032 unsigned first_regno : 5;
1033 unsigned num_regs : 3;
1034 /* 1 if it is a list of reg element. */
1035 unsigned has_index : 1;
1036 /* Lane index; valid only when has_index is 1. */
dab26bf4 1037 int64_t index;
a06ea964
NC		 1038 } reglist;
1039 /* e.g. immediate or pc relative address offset. */
1040 struct
1041 {
1042 int64_t value;
1043 unsigned is_fp : 1;
1044 } imm;
1045 /* e.g. address in STR (register offset). */
1046 struct
1047 {
1048 unsigned base_regno;
1049 struct
1050 {
1051 union
1052 {
1053 int imm;
1054 unsigned regno;
1055 };
1056 unsigned is_reg;
1057 } offset;
1058 unsigned pcrel : 1; /* PC-relative. */
1059 unsigned writeback : 1;
1060 unsigned preind : 1; /* Pre-indexed. */
1061 unsigned postind : 1; /* Post-indexed. */
1062 } addr;
561a72d4
TC		 1063
1064 struct
1065 {
1066 /* The encoding of the system register. */
1067 aarch64_insn value;
1068
1069 /* The system register flags. */
1070 uint32_t flags;
1071 } sysreg;
1072
a06ea964 1073 const aarch64_cond *cond;
a06ea964
NC		 1074 /* The encoding of the PSTATE field. */
1075 aarch64_insn pstatefield;
1076 const aarch64_sys_ins_reg *sysins_op;
1077 const struct aarch64_name_value_pair *barrier;
9ed608f9 1078 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 1079 const struct aarch64_name_value_pair *prfop;
1080 };
1081
1082 /* Operand shifter; in use when the operand is a register offset address,
1083 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
1084 struct
1085 {
1086 enum aarch64_modifier_kind kind;
a06ea964
NC		 1087 unsigned operator_present: 1; /* Only valid during encoding. */
1088 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
1089 unsigned amount_present: 1;
2442d846 1090 int64_t amount;
a06ea964
NC		 1091 } shifter;
1092
1093 unsigned skip:1; /* Operand is not completed if there is a fixup needed
1094 to be done on it. In some (but not all) of these
1095 cases, we need to tell libopcodes to skip the
1096 constraint checking and the encoding for this
1097 operand, so that the libopcodes can pick up the
1098 right opcode before the operand is fixed-up. This
1099 flag should only be used during the
1100 assembling/encoding. */
1101 unsigned present:1; /* Whether this operand is present in the assembly
1102 line; not used during the disassembly. */
1103};
1104
1105typedef struct aarch64_opnd_info aarch64_opnd_info;
1106
1107/* Structure representing an instruction.
1108
1109 It is used during both the assembling and disassembling. The assembler
1110 fills an aarch64_inst after a successful parsing and then passes it to the
1111 encoding routine to do the encoding. During the disassembling, the
1112 disassembler calls the decoding routine to decode a binary instruction; on a
1113 successful return, such a structure will be filled with information of the
1114 instruction; then the disassembler uses the information to print out the
1115 instruction. */
1116
1117struct aarch64_inst
1118{
1119 /* The value of the binary instruction. */
1120 aarch64_insn value;
1121
1122 /* Corresponding opcode entry. */
1123 const aarch64_opcode *opcode;
1124
1125 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
1126 const aarch64_cond *cond;
1127
1128 /* Operands information. */
1129 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1130};
1131
ff605452
SD		 1132/* Defining the HINT #imm values for the aarch64_hint_options. */
1133#define HINT_OPD_CSYNC 0x11
1134#define HINT_OPD_C 0x22
1135#define HINT_OPD_J 0x24
1136#define HINT_OPD_JC 0x26
1137#define HINT_OPD_NULL 0x00
1138
a06ea964
NC		 1139\f
1140/* Diagnosis related declaration and interface. */
1141
1142/* Operand error kind enumerators.
1143
1144 AARCH64_OPDE_RECOVERABLE
1145 Less severe error found during the parsing, very possibly because that
1146 GAS has picked up a wrong instruction template for the parsing.
1147
1148 AARCH64_OPDE_SYNTAX_ERROR
1149 General syntax error; it can be either a user error, or simply because
1150 that GAS is trying a wrong instruction template.
1151
1152 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1153 Definitely a user syntax error.
1154
1155 AARCH64_OPDE_INVALID_VARIANT
1156 No syntax error, but the operands are not a valid combination, e.g.
1157 FMOV D0,S0
1158
0c608d6b
RS		 1159 AARCH64_OPDE_UNTIED_OPERAND
1160 The asm failed to use the same register for a destination operand
1161 and a tied source operand.
1162
a06ea964
NC		 1163 AARCH64_OPDE_OUT_OF_RANGE
1164 Error about some immediate value out of a valid range.
1165
1166 AARCH64_OPDE_UNALIGNED
1167 Error about some immediate value not properly aligned (i.e. not being a
1168 multiple times of a certain value).
1169
1170 AARCH64_OPDE_REG_LIST
1171 Error about the register list operand having unexpected number of
1172 registers.
1173
1174 AARCH64_OPDE_OTHER_ERROR
1175 Error of the highest severity and used for any severe issue that does not
1176 fall into any of the above categories.
1177
1178 The enumerators are only interesting to GAS. They are declared here (in
1179 libopcodes) because that some errors are detected (and then notified to GAS)
1180 by libopcodes (rather than by GAS solely).
1181
1182 The first three errors are only deteced by GAS while the
1183 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1184 only libopcodes has the information about the valid variants of each
1185 instruction.
1186
1187 The enumerators have an increasing severity. This is helpful when there are
1188 multiple instruction templates available for a given mnemonic name (e.g.
1189 FMOV); this mechanism will help choose the most suitable template from which
1190 the generated diagnostics can most closely describe the issues, if any. */
1191
1192enum aarch64_operand_error_kind
1193{
1194 AARCH64_OPDE_NIL,
1195 AARCH64_OPDE_RECOVERABLE,
1196 AARCH64_OPDE_SYNTAX_ERROR,
1197 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1198 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1199 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1200 AARCH64_OPDE_OUT_OF_RANGE,
1201 AARCH64_OPDE_UNALIGNED,
1202 AARCH64_OPDE_REG_LIST,
1203 AARCH64_OPDE_OTHER_ERROR
1204};
1205
1206/* N.B. GAS assumes that this structure work well with shallow copy. */
1207struct aarch64_operand_error
1208{
1209 enum aarch64_operand_error_kind kind;
1210 int index;
1211 const char *error;
1212 int data[3]; /* Some data for extra information. */
7d02540a 1213 bfd_boolean non_fatal;
a06ea964
NC		 1214};
1215
7e84b55d
TC		 1216/* AArch64 sequence structure used to track instructions with F_SCAN
1217 dependencies for both assembler and disassembler. */
1218struct aarch64_instr_sequence
1219{
1220 /* The instruction that caused this sequence to be opened. */
1221 aarch64_inst *instr;
1222 /* The number of instructions the above instruction allows to be kept in the
1223 sequence before an automatic close is done. */
1224 int num_insns;
1225 /* The instructions currently added to the sequence. */
1226 aarch64_inst **current_insns;
1227 /* The number of instructions already in the sequence. */
1228 int next_insn;
1229};
a06ea964
NC		 1230
1231/* Encoding entrypoint. */
1232
1233extern int
1234aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1235 aarch64_insn *, aarch64_opnd_qualifier_t *,
7e84b55d 1236 aarch64_operand_error *, aarch64_instr_sequence *);
a06ea964
NC		 1237
1238extern const aarch64_opcode *
1239aarch64_replace_opcode (struct aarch64_inst *,
1240 const aarch64_opcode *);
1241
1242/* Given the opcode enumerator OP, return the pointer to the corresponding
1243 opcode entry. */
1244
1245extern const aarch64_opcode *
1246aarch64_get_opcode (enum aarch64_op);
1247
1248/* Generate the string representation of an operand. */
1249extern void
1250aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
7d02540a
TC		 1251 const aarch64_opnd_info *, int, int *, bfd_vma *,
1252 char **);
a06ea964
NC		 1253
1254/* Miscellaneous interface. */
1255
1256extern int
1257aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1258
1259extern aarch64_opnd_qualifier_t
1260aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1261 const aarch64_opnd_qualifier_t, int);
1262
a68f4cd2
TC		 1263extern bfd_boolean
1264aarch64_is_destructive_by_operands (const aarch64_opcode *);
1265
a06ea964
NC		 1266extern int
1267aarch64_num_of_operands (const aarch64_opcode *);
1268
1269extern int
1270aarch64_stack_pointer_p (const aarch64_opnd_info *);
1271
e141d84e
YQ		 1272extern int
1273aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1274
1d482394 1275extern enum err_type
561a72d4 1276aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
a68f4cd2
TC		 1277 aarch64_operand_error *);
1278
1279extern void
1280init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
36f4aab1 1281
a06ea964
NC		 1282/* Given an operand qualifier, return the expected data element size
1283 of a qualified operand. */
1284extern unsigned char
1285aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1286
1287extern enum aarch64_operand_class
1288aarch64_get_operand_class (enum aarch64_opnd);
1289
1290extern const char *
1291aarch64_get_operand_name (enum aarch64_opnd);
1292
1293extern const char *
1294aarch64_get_operand_desc (enum aarch64_opnd);
1295
e950b345
RS		 1296extern bfd_boolean
1297aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1298
a06ea964
NC		 1299#ifdef DEBUG_AARCH64
1300extern int debug_dump;
1301
1302extern void
1303aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1304
1305#define DEBUG_TRACE(M, ...) \
1306 { \
1307 if (debug_dump) \
1308 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1309 }
1310
1311#define DEBUG_TRACE_IF(C, M, ...) \
1312 { \
1313 if (debug_dump && (C)) \
1314 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1315 }
1316#else /* !DEBUG_AARCH64 */
1317#define DEBUG_TRACE(M, ...) ;
1318#define DEBUG_TRACE_IF(C, M, ...) ;
1319#endif /* DEBUG_AARCH64 */
1320
245d2e3f
RS		 1321extern const char *const aarch64_sve_pattern_array[32];
1322extern const char *const aarch64_sve_prfop_array[16];
1323
d3e12b29
YQ		 1324#ifdef __cplusplus
1325}
1326#endif
1327
a06ea964 1328#endif /* OPCODE_AARCH64_H */
GDB Binutils - Deliverables
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