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Add assembler and disassembler support for the new Armv8.4-a registers for AArch64.
[deliverable/binutils-gdb.git] / include / opcode / aarch64.h
CommitLineData
a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
2571583a 3 Copyright (C) 2009-2017 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
c0e7cef7
NC		 40#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
41#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
b6b9ca0c
TC		 42#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
43#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
44#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
a06ea964 45#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
acb787b0 46#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
1924ff75 47#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
a06ea964
NC		 48#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
49#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
50#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
e60bb1dd 51#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
ee804238 52#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
f21cce2c 53#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
290806fd 54#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
9e1f0fa7 55#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
250aafa4 56#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
af117b3c 57#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
c8a6db6f 58#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
73af8ed6 59#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
c0890d26 60#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
d74d4880 61#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
f482d304 62#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
65a55fbb 63#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
a06ea964
NC		 64
65/* Architectures are the sum of the base and extensions. */
66#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
67 AARCH64_FEATURE_FP \
68 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 69#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
70 AARCH64_FEATURE_CRC \
250aafa4 71 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 72 | AARCH64_FEATURE_LSE \
73 | AARCH64_FEATURE_PAN \
74 | AARCH64_FEATURE_LOR \
75 | AARCH64_FEATURE_RDMA)
1924ff75 76#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 77 AARCH64_FEATURE_V8_2 \
1924ff75
SN		 78 | AARCH64_FEATURE_RAS)
79#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
d74d4880 80 AARCH64_FEATURE_V8_3 \
f482d304
RS		 81 | AARCH64_FEATURE_RCPC \
82 | AARCH64_FEATURE_COMPNUM)
b6b9ca0c
TC		 83#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
84 AARCH64_FEATURE_V8_4)
88f0ea34 85
a06ea964
NC		 86#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
87#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
88
89/* CPU-specific features. */
21b81e67 90typedef unsigned long long aarch64_feature_set;
a06ea964 91
93d8990c
SN		 92#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
93 ((~(CPU) & (FEAT)) == 0)
94
95#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 96 (((CPU) & (FEAT)) != 0)
97
93d8990c
SN		 98#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
99 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
100
a06ea964
NC		 101#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
102 do \
103 { \
104 (TARG) = (F1) | (F2); \
105 } \
106 while (0)
107
108#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
109 do \
110 { \
111 (TARG) = (F1) &~ (F2); \
112 } \
113 while (0)
114
115#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
116
a06ea964
NC		 117enum aarch64_operand_class
118{
119 AARCH64_OPND_CLASS_NIL,
120 AARCH64_OPND_CLASS_INT_REG,
121 AARCH64_OPND_CLASS_MODIFIED_REG,
122 AARCH64_OPND_CLASS_FP_REG,
123 AARCH64_OPND_CLASS_SIMD_REG,
124 AARCH64_OPND_CLASS_SIMD_ELEMENT,
125 AARCH64_OPND_CLASS_SISD_REG,
126 AARCH64_OPND_CLASS_SIMD_REGLIST,
f11ad6bc
RS		 127 AARCH64_OPND_CLASS_SVE_REG,
128 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 129 AARCH64_OPND_CLASS_ADDRESS,
130 AARCH64_OPND_CLASS_IMMEDIATE,
131 AARCH64_OPND_CLASS_SYSTEM,
68a64283 132 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 133};
134
135/* Operand code that helps both parsing and coding.
136 Keep AARCH64_OPERANDS synced. */
137
138enum aarch64_opnd
139{
140 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
141
142 AARCH64_OPND_Rd, /* Integer register as destination. */
143 AARCH64_OPND_Rn, /* Integer register as source. */
144 AARCH64_OPND_Rm, /* Integer register as source. */
145 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
146 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
147 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
148 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
149 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
150
151 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
152 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 153 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 154 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 155 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
156 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
157
158 AARCH64_OPND_Fd, /* Floating-point Fd. */
159 AARCH64_OPND_Fn, /* Floating-point Fn. */
160 AARCH64_OPND_Fm, /* Floating-point Fm. */
161 AARCH64_OPND_Fa, /* Floating-point Fa. */
162 AARCH64_OPND_Ft, /* Floating-point Ft. */
163 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
164
165 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
166 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
167 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
168
f42f1a1d 169 AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
a06ea964
NC		 170 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
171 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
172 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
173 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
174 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
175 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
176 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
177 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
178 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
179 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
180 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
181 structure to all lanes. */
182 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
183
a6a51754
RL		 184 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
185 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
a06ea964
NC		 186
187 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
f42f1a1d 188 AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */
a06ea964
NC		 189 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
190 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
191 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
192 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
193 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
194 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
195 (no encoding). */
196 AARCH64_OPND_IMM0, /* Immediate for #0. */
197 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
198 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
199 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
200 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
201 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
202 AARCH64_OPND_IMM, /* Immediate. */
f42f1a1d 203 AARCH64_OPND_IMM_2, /* Immediate. */
a06ea964
NC		 204 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
205 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
206 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
207 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
208 AARCH64_OPND_BIT_NUM, /* Immediate. */
209 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
210 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 211 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 212 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
213 each condition flag. */
214
215 AARCH64_OPND_LIMM, /* Logical Immediate. */
216 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
217 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
218 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
219 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
c2c4ff8d
SN		 220 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
221 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
222 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
a06ea964
NC		 223
224 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 225 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 226
227 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
228 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
229 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
230 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
231 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
232
233 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
234 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
235 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
236 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
237 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
238 negative or unaligned and there is
239 no writeback allowed. This operand code
240 is only used to support the programmer-
241 friendly feature of using LDR/STR as the
242 the mnemonic name for LDUR/STUR instructions
243 wherever there is no ambiguity. */
3f06e550 244 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
a06ea964
NC		 245 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
246 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
f42f1a1d 247 AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
a06ea964
NC		 248 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
249
250 AARCH64_OPND_SYSREG, /* System register operand. */
251 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
252 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
253 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
254 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
255 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
256 AARCH64_OPND_BARRIER, /* Barrier operand. */
257 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
258 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 259 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
f11ad6bc 260
582e12bf 261 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
98907a70
RS		 262 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
263 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
264 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
265 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
266 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
267 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 268 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
269 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
270 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
271 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
272 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
273 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
274 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
275 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
276 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
277 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
278 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
279 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
280 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
281 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
282 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
283 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
284 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
285 Bit 14 controls S/U choice. */
286 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
287 Bit 22 controls S/U choice. */
288 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
289 Bit 14 controls S/U choice. */
290 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
291 Bit 22 controls S/U choice. */
292 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
293 Bit 14 controls S/U choice. */
294 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
295 Bit 22 controls S/U choice. */
296 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
297 Bit 14 controls S/U choice. */
298 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
299 Bit 22 controls S/U choice. */
300 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
301 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
302 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
303 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
304 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
305 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
306 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 307 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
308 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 309 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
310 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
311 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
312 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
582e12bf
RS		 313 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
314 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
e950b345
RS		 315 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
316 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
317 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 318 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 319 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 320 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 321 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
322 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
323 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
324 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
325 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
326 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
327 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
328 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 329 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
330 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 331 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
332 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
333 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
334 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
335 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
336 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
337 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
338 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
339 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
340 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
341 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
342 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 343 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
344 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
345 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
346 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 347 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
348 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
349 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
350 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
351 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
582e12bf
RS		 352 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
353 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
354 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
f11ad6bc
RS		 355 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
356 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
357 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
358 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
359 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
f42f1a1d 360 AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
a06ea964
NC		 361};
362
363/* Qualifier constrains an operand. It either specifies a variant of an
364 operand type or limits values available to an operand type.
365
366 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
367
368enum aarch64_opnd_qualifier
369{
370 /* Indicating no further qualification on an operand. */
371 AARCH64_OPND_QLF_NIL,
372
373 /* Qualifying an operand which is a general purpose (integer) register;
374 indicating the operand data size or a specific register. */
375 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
376 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
377 AARCH64_OPND_QLF_WSP, /* WSP. */
378 AARCH64_OPND_QLF_SP, /* SP. */
379
380 /* Qualifying an operand which is a floating-point register, a SIMD
381 vector element or a SIMD vector element list; indicating operand data
382 size or the size of each SIMD vector element in the case of a SIMD
383 vector element list.
384 These qualifiers are also used to qualify an address operand to
385 indicate the size of data element a load/store instruction is
386 accessing.
387 They are also used for the immediate shift operand in e.g. SSHR. Such
388 a use is only for the ease of operand encoding/decoding and qualifier
389 sequence matching; such a use should not be applied widely; use the value
390 constraint qualifiers for immediate operands wherever possible. */
391 AARCH64_OPND_QLF_S_B,
392 AARCH64_OPND_QLF_S_H,
393 AARCH64_OPND_QLF_S_S,
394 AARCH64_OPND_QLF_S_D,
395 AARCH64_OPND_QLF_S_Q,
396
397 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
398 register list; indicating register shape.
399 They are also used for the immediate shift operand in e.g. SSHR. Such
400 a use is only for the ease of operand encoding/decoding and qualifier
401 sequence matching; such a use should not be applied widely; use the value
402 constraint qualifiers for immediate operands wherever possible. */
403 AARCH64_OPND_QLF_V_8B,
404 AARCH64_OPND_QLF_V_16B,
3067d3b9 405 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 406 AARCH64_OPND_QLF_V_4H,
407 AARCH64_OPND_QLF_V_8H,
408 AARCH64_OPND_QLF_V_2S,
409 AARCH64_OPND_QLF_V_4S,
410 AARCH64_OPND_QLF_V_1D,
411 AARCH64_OPND_QLF_V_2D,
412 AARCH64_OPND_QLF_V_1Q,
413
d50c751e
RS		 414 AARCH64_OPND_QLF_P_Z,
415 AARCH64_OPND_QLF_P_M,
416
a06ea964 417 /* Constraint on value. */
a6a51754 418 AARCH64_OPND_QLF_CR, /* CRn, CRm. */
a06ea964
NC		 419 AARCH64_OPND_QLF_imm_0_7,
420 AARCH64_OPND_QLF_imm_0_15,
421 AARCH64_OPND_QLF_imm_0_31,
422 AARCH64_OPND_QLF_imm_0_63,
423 AARCH64_OPND_QLF_imm_1_32,
424 AARCH64_OPND_QLF_imm_1_64,
425
426 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
427 or shift-ones. */
428 AARCH64_OPND_QLF_LSL,
429 AARCH64_OPND_QLF_MSL,
430
431 /* Special qualifier helping retrieve qualifier information during the
432 decoding time (currently not in use). */
433 AARCH64_OPND_QLF_RETRIEVE,
434};
435\f
436/* Instruction class. */
437
438enum aarch64_insn_class
439{
440 addsub_carry,
441 addsub_ext,
442 addsub_imm,
443 addsub_shift,
444 asimdall,
445 asimddiff,
446 asimdelem,
447 asimdext,
448 asimdimm,
449 asimdins,
450 asimdmisc,
451 asimdperm,
452 asimdsame,
453 asimdshf,
454 asimdtbl,
455 asisddiff,
456 asisdelem,
457 asisdlse,
458 asisdlsep,
459 asisdlso,
460 asisdlsop,
461 asisdmisc,
462 asisdone,
463 asisdpair,
464 asisdsame,
465 asisdshf,
466 bitfield,
467 branch_imm,
468 branch_reg,
469 compbranch,
470 condbranch,
471 condcmp_imm,
472 condcmp_reg,
473 condsel,
474 cryptoaes,
475 cryptosha2,
476 cryptosha3,
477 dp_1src,
478 dp_2src,
479 dp_3src,
480 exception,
481 extract,
482 float2fix,
483 float2int,
484 floatccmp,
485 floatcmp,
486 floatdp1,
487 floatdp2,
488 floatdp3,
489 floatimm,
490 floatsel,
491 ldst_immpost,
492 ldst_immpre,
493 ldst_imm9, /* immpost or immpre */
3f06e550 494 ldst_imm10, /* LDRAA/LDRAB */
a06ea964
NC		 495 ldst_pos,
496 ldst_regoff,
497 ldst_unpriv,
498 ldst_unscaled,
499 ldstexcl,
500 ldstnapair_offs,
501 ldstpair_off,
502 ldstpair_indexed,
503 loadlit,
504 log_imm,
505 log_shift,
ee804238 506 lse_atomic,
a06ea964
NC		 507 movewide,
508 pcreladdr,
509 ic_system,
116b6019
RS		 510 sve_cpy,
511 sve_index,
512 sve_limm,
513 sve_misc,
514 sve_movprfx,
515 sve_pred_zm,
516 sve_shift_pred,
517 sve_shift_unpred,
518 sve_size_bhs,
519 sve_size_bhsd,
520 sve_size_hsd,
521 sve_size_sd,
a06ea964 522 testbranch,
f42f1a1d
TC		 523 cryptosm3,
524 cryptosm4,
65a55fbb 525 dotproduct,
a06ea964
NC		 526};
527
528/* Opcode enumerators. */
529
530enum aarch64_op
531{
532 OP_NIL,
533 OP_STRB_POS,
534 OP_LDRB_POS,
535 OP_LDRSB_POS,
536 OP_STRH_POS,
537 OP_LDRH_POS,
538 OP_LDRSH_POS,
539 OP_STR_POS,
540 OP_LDR_POS,
541 OP_STRF_POS,
542 OP_LDRF_POS,
543 OP_LDRSW_POS,
544 OP_PRFM_POS,
545
546 OP_STURB,
547 OP_LDURB,
548 OP_LDURSB,
549 OP_STURH,
550 OP_LDURH,
551 OP_LDURSH,
552 OP_STUR,
553 OP_LDUR,
554 OP_STURV,
555 OP_LDURV,
556 OP_LDURSW,
557 OP_PRFUM,
558
559 OP_LDR_LIT,
560 OP_LDRV_LIT,
561 OP_LDRSW_LIT,
562 OP_PRFM_LIT,
563
564 OP_ADD,
565 OP_B,
566 OP_BL,
567
568 OP_MOVN,
569 OP_MOVZ,
570 OP_MOVK,
571
572 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
573 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
574 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
575
576 OP_MOV_V, /* MOV alias for moving vector register. */
577
578 OP_ASR_IMM,
579 OP_LSR_IMM,
580 OP_LSL_IMM,
581
582 OP_BIC,
583
584 OP_UBFX,
585 OP_BFXIL,
586 OP_SBFX,
587 OP_SBFIZ,
588 OP_BFI,
d685192a 589 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 590 OP_UBFIZ,
591 OP_UXTB,
592 OP_UXTH,
593 OP_UXTW,
594
a06ea964
NC		 595 OP_CINC,
596 OP_CINV,
597 OP_CNEG,
598 OP_CSET,
599 OP_CSETM,
600
601 OP_FCVT,
602 OP_FCVTN,
603 OP_FCVTN2,
604 OP_FCVTL,
605 OP_FCVTL2,
606 OP_FCVTXN_S, /* Scalar version. */
607
608 OP_ROR_IMM,
609
e30181a5
YZ		 610 OP_SXTL,
611 OP_SXTL2,
612 OP_UXTL,
613 OP_UXTL2,
614
c0890d26
RS		 615 OP_MOV_P_P,
616 OP_MOV_Z_P_Z,
617 OP_MOV_Z_V,
618 OP_MOV_Z_Z,
619 OP_MOV_Z_Zi,
620 OP_MOVM_P_P_P,
621 OP_MOVS_P_P,
622 OP_MOVZS_P_P_P,
623 OP_MOVZ_P_P_P,
624 OP_NOTS_P_P_P_Z,
625 OP_NOT_P_P_P_Z,
626
c2c4ff8d
SN		 627 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
628
a06ea964
NC		 629 OP_TOTAL_NUM, /* Pseudo. */
630};
631
632/* Maximum number of operands an instruction can have. */
633#define AARCH64_MAX_OPND_NUM 6
634/* Maximum number of qualifier sequences an instruction can have. */
635#define AARCH64_MAX_QLF_SEQ_NUM 10
636/* Operand qualifier typedef; optimized for the size. */
637typedef unsigned char aarch64_opnd_qualifier_t;
638/* Operand qualifier sequence typedef. */
639typedef aarch64_opnd_qualifier_t \
640 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
641
642/* FIXME: improve the efficiency. */
643static inline bfd_boolean
644empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
645{
646 int i;
647 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
648 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
649 return FALSE;
650 return TRUE;
651}
652
653/* This structure holds information for a particular opcode. */
654
655struct aarch64_opcode
656{
657 /* The name of the mnemonic. */
658 const char *name;
659
660 /* The opcode itself. Those bits which will be filled in with
661 operands are zeroes. */
662 aarch64_insn opcode;
663
664 /* The opcode mask. This is used by the disassembler. This is a
665 mask containing ones indicating those bits which must match the
666 opcode field, and zeroes indicating those bits which need not
667 match (and are presumably filled in by operands). */
668 aarch64_insn mask;
669
670 /* Instruction class. */
671 enum aarch64_insn_class iclass;
672
673 /* Enumerator identifier. */
674 enum aarch64_op op;
675
676 /* Which architecture variant provides this instruction. */
677 const aarch64_feature_set *avariant;
678
679 /* An array of operand codes. Each code is an index into the
680 operand table. They appear in the order which the operands must
681 appear in assembly code, and are terminated by a zero. */
682 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
683
684 /* A list of operand qualifier code sequence. Each operand qualifier
685 code qualifies the corresponding operand code. Each operand
686 qualifier sequence specifies a valid opcode variant and related
687 constraint on operands. */
688 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
689
690 /* Flags providing information about this instruction */
691 uint32_t flags;
4bd13cde 692
0c608d6b
RS		 693 /* If nonzero, this operand and operand 0 are both registers and
694 are required to have the same register number. */
695 unsigned char tied_operand;
696
4bd13cde
NC		 697 /* If non-NULL, a function to verify that a given instruction is valid. */
698 bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
a06ea964
NC		 699};
700
701typedef struct aarch64_opcode aarch64_opcode;
702
703/* Table describing all the AArch64 opcodes. */
704extern aarch64_opcode aarch64_opcode_table[];
705
706/* Opcode flags. */
707#define F_ALIAS (1 << 0)
708#define F_HAS_ALIAS (1 << 1)
709/* Disassembly preference priority 1-3 (the larger the higher). If nothing
710 is specified, it is the priority 0 by default, i.e. the lowest priority. */
711#define F_P1 (1 << 2)
712#define F_P2 (2 << 2)
713#define F_P3 (3 << 2)
714/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
715#define F_COND (1 << 4)
716/* Instruction has the field of 'sf'. */
717#define F_SF (1 << 5)
718/* Instruction has the field of 'size:Q'. */
719#define F_SIZEQ (1 << 6)
720/* Floating-point instruction has the field of 'type'. */
721#define F_FPTYPE (1 << 7)
722/* AdvSIMD scalar instruction has the field of 'size'. */
723#define F_SSIZE (1 << 8)
724/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
725#define F_T (1 << 9)
726/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
727#define F_GPRSIZE_IN_Q (1 << 10)
728/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
729#define F_LDS_SIZE (1 << 11)
730/* Optional operand; assume maximum of 1 operand can be optional. */
731#define F_OPD0_OPT (1 << 12)
732#define F_OPD1_OPT (2 << 12)
733#define F_OPD2_OPT (3 << 12)
734#define F_OPD3_OPT (4 << 12)
735#define F_OPD4_OPT (5 << 12)
736/* Default value for the optional operand when omitted from the assembly. */
737#define F_DEFAULT(X) (((X) & 0x1f) << 15)
738/* Instruction that is an alias of another instruction needs to be
739 encoded/decoded by converting it to/from the real form, followed by
740 the encoding/decoding according to the rules of the real opcode.
741 This compares to the direct coding using the alias's information.
742 N.B. this flag requires F_ALIAS to be used together. */
743#define F_CONV (1 << 20)
744/* Use together with F_ALIAS to indicate an alias opcode is a programmer
745 friendly pseudo instruction available only in the assembly code (thus will
746 not show up in the disassembly). */
747#define F_PSEUDO (1 << 21)
748/* Instruction has miscellaneous encoding/decoding rules. */
749#define F_MISC (1 << 22)
750/* Instruction has the field of 'N'; used in conjunction with F_SF. */
751#define F_N (1 << 23)
752/* Opcode dependent field. */
753#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 754/* Instruction has the field of 'sz'. */
755#define F_LSE_SZ (1 << 27)
4989adac
RS		 756/* Require an exact qualifier match, even for NIL qualifiers. */
757#define F_STRICT (1ULL << 28)
758/* Next bit is 29. */
a06ea964
NC		 759
760static inline bfd_boolean
761alias_opcode_p (const aarch64_opcode *opcode)
762{
763 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
764}
765
766static inline bfd_boolean
767opcode_has_alias (const aarch64_opcode *opcode)
768{
769 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
770}
771
772/* Priority for disassembling preference. */
773static inline int
774opcode_priority (const aarch64_opcode *opcode)
775{
776 return (opcode->flags >> 2) & 0x3;
777}
778
779static inline bfd_boolean
780pseudo_opcode_p (const aarch64_opcode *opcode)
781{
782 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
783}
784
785static inline bfd_boolean
786optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
787{
788 return (((opcode->flags >> 12) & 0x7) == idx + 1)
789 ? TRUE : FALSE;
790}
791
792static inline aarch64_insn
793get_optional_operand_default_value (const aarch64_opcode *opcode)
794{
795 return (opcode->flags >> 15) & 0x1f;
796}
797
798static inline unsigned int
799get_opcode_dependent_value (const aarch64_opcode *opcode)
800{
801 return (opcode->flags >> 24) & 0x7;
802}
803
804static inline bfd_boolean
805opcode_has_special_coder (const aarch64_opcode *opcode)
806{
ee804238 807 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 808 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
809 : FALSE;
810}
811\f
812struct aarch64_name_value_pair
813{
814 const char * name;
815 aarch64_insn value;
816};
817
818extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964
NC		 819extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
820extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 821extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 822
49eec193
YZ		 823typedef struct
824{
825 const char * name;
826 aarch64_insn value;
827 uint32_t flags;
828} aarch64_sys_reg;
829
830extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 831extern const aarch64_sys_reg aarch64_pstatefields [];
49eec193 832extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
f21cce2c
MW		 833extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
834 const aarch64_sys_reg *);
835extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
836 const aarch64_sys_reg *);
49eec193 837
a06ea964
NC		 838typedef struct
839{
875880c6 840 const char *name;
a06ea964 841 uint32_t value;
ea2deeec 842 uint32_t flags ;
a06ea964
NC		 843} aarch64_sys_ins_reg;
844
ea2deeec 845extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6
MW		 846extern bfd_boolean
847aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
848 const aarch64_sys_ins_reg *);
ea2deeec 849
a06ea964
NC		 850extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
851extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
852extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
853extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
854
855/* Shift/extending operator kinds.
856 N.B. order is important; keep aarch64_operand_modifiers synced. */
857enum aarch64_modifier_kind
858{
859 AARCH64_MOD_NONE,
860 AARCH64_MOD_MSL,
861 AARCH64_MOD_ROR,
862 AARCH64_MOD_ASR,
863 AARCH64_MOD_LSR,
864 AARCH64_MOD_LSL,
865 AARCH64_MOD_UXTB,
866 AARCH64_MOD_UXTH,
867 AARCH64_MOD_UXTW,
868 AARCH64_MOD_UXTX,
869 AARCH64_MOD_SXTB,
870 AARCH64_MOD_SXTH,
871 AARCH64_MOD_SXTW,
872 AARCH64_MOD_SXTX,
2442d846 873 AARCH64_MOD_MUL,
98907a70 874 AARCH64_MOD_MUL_VL,
a06ea964
NC		 875};
876
877bfd_boolean
878aarch64_extend_operator_p (enum aarch64_modifier_kind);
879
880enum aarch64_modifier_kind
881aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
882/* Condition. */
883
884typedef struct
885{
886 /* A list of names with the first one as the disassembly preference;
887 terminated by NULL if fewer than 3. */
bb7eff52 888 const char *names[4];
a06ea964
NC		 889 aarch64_insn value;
890} aarch64_cond;
891
892extern const aarch64_cond aarch64_conds[16];
893
894const aarch64_cond* get_cond_from_value (aarch64_insn value);
895const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
896\f
897/* Structure representing an operand. */
898
899struct aarch64_opnd_info
900{
901 enum aarch64_opnd type;
902 aarch64_opnd_qualifier_t qualifier;
903 int idx;
904
905 union
906 {
907 struct
908 {
909 unsigned regno;
910 } reg;
911 struct
912 {
dab26bf4
RS		 913 unsigned int regno;
914 int64_t index;
a06ea964
NC		 915 } reglane;
916 /* e.g. LVn. */
917 struct
918 {
919 unsigned first_regno : 5;
920 unsigned num_regs : 3;
921 /* 1 if it is a list of reg element. */
922 unsigned has_index : 1;
923 /* Lane index; valid only when has_index is 1. */
dab26bf4 924 int64_t index;
a06ea964
NC		 925 } reglist;
926 /* e.g. immediate or pc relative address offset. */
927 struct
928 {
929 int64_t value;
930 unsigned is_fp : 1;
931 } imm;
932 /* e.g. address in STR (register offset). */
933 struct
934 {
935 unsigned base_regno;
936 struct
937 {
938 union
939 {
940 int imm;
941 unsigned regno;
942 };
943 unsigned is_reg;
944 } offset;
945 unsigned pcrel : 1; /* PC-relative. */
946 unsigned writeback : 1;
947 unsigned preind : 1; /* Pre-indexed. */
948 unsigned postind : 1; /* Post-indexed. */
949 } addr;
950 const aarch64_cond *cond;
951 /* The encoding of the system register. */
952 aarch64_insn sysreg;
953 /* The encoding of the PSTATE field. */
954 aarch64_insn pstatefield;
955 const aarch64_sys_ins_reg *sysins_op;
956 const struct aarch64_name_value_pair *barrier;
9ed608f9 957 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 958 const struct aarch64_name_value_pair *prfop;
959 };
960
961 /* Operand shifter; in use when the operand is a register offset address,
962 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
963 struct
964 {
965 enum aarch64_modifier_kind kind;
a06ea964
NC		 966 unsigned operator_present: 1; /* Only valid during encoding. */
967 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
968 unsigned amount_present: 1;
2442d846 969 int64_t amount;
a06ea964
NC		 970 } shifter;
971
972 unsigned skip:1; /* Operand is not completed if there is a fixup needed
973 to be done on it. In some (but not all) of these
974 cases, we need to tell libopcodes to skip the
975 constraint checking and the encoding for this
976 operand, so that the libopcodes can pick up the
977 right opcode before the operand is fixed-up. This
978 flag should only be used during the
979 assembling/encoding. */
980 unsigned present:1; /* Whether this operand is present in the assembly
981 line; not used during the disassembly. */
982};
983
984typedef struct aarch64_opnd_info aarch64_opnd_info;
985
986/* Structure representing an instruction.
987
988 It is used during both the assembling and disassembling. The assembler
989 fills an aarch64_inst after a successful parsing and then passes it to the
990 encoding routine to do the encoding. During the disassembling, the
991 disassembler calls the decoding routine to decode a binary instruction; on a
992 successful return, such a structure will be filled with information of the
993 instruction; then the disassembler uses the information to print out the
994 instruction. */
995
996struct aarch64_inst
997{
998 /* The value of the binary instruction. */
999 aarch64_insn value;
1000
1001 /* Corresponding opcode entry. */
1002 const aarch64_opcode *opcode;
1003
1004 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
1005 const aarch64_cond *cond;
1006
1007 /* Operands information. */
1008 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1009};
1010
1011typedef struct aarch64_inst aarch64_inst;
1012\f
1013/* Diagnosis related declaration and interface. */
1014
1015/* Operand error kind enumerators.
1016
1017 AARCH64_OPDE_RECOVERABLE
1018 Less severe error found during the parsing, very possibly because that
1019 GAS has picked up a wrong instruction template for the parsing.
1020
1021 AARCH64_OPDE_SYNTAX_ERROR
1022 General syntax error; it can be either a user error, or simply because
1023 that GAS is trying a wrong instruction template.
1024
1025 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1026 Definitely a user syntax error.
1027
1028 AARCH64_OPDE_INVALID_VARIANT
1029 No syntax error, but the operands are not a valid combination, e.g.
1030 FMOV D0,S0
1031
0c608d6b
RS		 1032 AARCH64_OPDE_UNTIED_OPERAND
1033 The asm failed to use the same register for a destination operand
1034 and a tied source operand.
1035
a06ea964
NC		 1036 AARCH64_OPDE_OUT_OF_RANGE
1037 Error about some immediate value out of a valid range.
1038
1039 AARCH64_OPDE_UNALIGNED
1040 Error about some immediate value not properly aligned (i.e. not being a
1041 multiple times of a certain value).
1042
1043 AARCH64_OPDE_REG_LIST
1044 Error about the register list operand having unexpected number of
1045 registers.
1046
1047 AARCH64_OPDE_OTHER_ERROR
1048 Error of the highest severity and used for any severe issue that does not
1049 fall into any of the above categories.
1050
1051 The enumerators are only interesting to GAS. They are declared here (in
1052 libopcodes) because that some errors are detected (and then notified to GAS)
1053 by libopcodes (rather than by GAS solely).
1054
1055 The first three errors are only deteced by GAS while the
1056 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1057 only libopcodes has the information about the valid variants of each
1058 instruction.
1059
1060 The enumerators have an increasing severity. This is helpful when there are
1061 multiple instruction templates available for a given mnemonic name (e.g.
1062 FMOV); this mechanism will help choose the most suitable template from which
1063 the generated diagnostics can most closely describe the issues, if any. */
1064
1065enum aarch64_operand_error_kind
1066{
1067 AARCH64_OPDE_NIL,
1068 AARCH64_OPDE_RECOVERABLE,
1069 AARCH64_OPDE_SYNTAX_ERROR,
1070 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1071 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1072 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1073 AARCH64_OPDE_OUT_OF_RANGE,
1074 AARCH64_OPDE_UNALIGNED,
1075 AARCH64_OPDE_REG_LIST,
1076 AARCH64_OPDE_OTHER_ERROR
1077};
1078
1079/* N.B. GAS assumes that this structure work well with shallow copy. */
1080struct aarch64_operand_error
1081{
1082 enum aarch64_operand_error_kind kind;
1083 int index;
1084 const char *error;
1085 int data[3]; /* Some data for extra information. */
1086};
1087
1088typedef struct aarch64_operand_error aarch64_operand_error;
1089
1090/* Encoding entrypoint. */
1091
1092extern int
1093aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1094 aarch64_insn *, aarch64_opnd_qualifier_t *,
1095 aarch64_operand_error *);
1096
1097extern const aarch64_opcode *
1098aarch64_replace_opcode (struct aarch64_inst *,
1099 const aarch64_opcode *);
1100
1101/* Given the opcode enumerator OP, return the pointer to the corresponding
1102 opcode entry. */
1103
1104extern const aarch64_opcode *
1105aarch64_get_opcode (enum aarch64_op);
1106
1107/* Generate the string representation of an operand. */
1108extern void
1109aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1110 const aarch64_opnd_info *, int, int *, bfd_vma *);
1111
1112/* Miscellaneous interface. */
1113
1114extern int
1115aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1116
1117extern aarch64_opnd_qualifier_t
1118aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1119 const aarch64_opnd_qualifier_t, int);
1120
1121extern int
1122aarch64_num_of_operands (const aarch64_opcode *);
1123
1124extern int
1125aarch64_stack_pointer_p (const aarch64_opnd_info *);
1126
e141d84e
YQ		 1127extern int
1128aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1129
36f4aab1 1130extern int
43cdf5ae 1131aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
36f4aab1 1132
a06ea964
NC		 1133/* Given an operand qualifier, return the expected data element size
1134 of a qualified operand. */
1135extern unsigned char
1136aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1137
1138extern enum aarch64_operand_class
1139aarch64_get_operand_class (enum aarch64_opnd);
1140
1141extern const char *
1142aarch64_get_operand_name (enum aarch64_opnd);
1143
1144extern const char *
1145aarch64_get_operand_desc (enum aarch64_opnd);
1146
e950b345
RS		 1147extern bfd_boolean
1148aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1149
a06ea964
NC		 1150#ifdef DEBUG_AARCH64
1151extern int debug_dump;
1152
1153extern void
1154aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1155
1156#define DEBUG_TRACE(M, ...) \
1157 { \
1158 if (debug_dump) \
1159 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1160 }
1161
1162#define DEBUG_TRACE_IF(C, M, ...) \
1163 { \
1164 if (debug_dump && (C)) \
1165 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1166 }
1167#else /* !DEBUG_AARCH64 */
1168#define DEBUG_TRACE(M, ...) ;
1169#define DEBUG_TRACE_IF(C, M, ...) ;
1170#endif /* DEBUG_AARCH64 */
1171
245d2e3f
RS		 1172extern const char *const aarch64_sve_pattern_array[32];
1173extern const char *const aarch64_sve_prfop_array[16];
1174
d3e12b29
YQ		 1175#ifdef __cplusplus
1176}
1177#endif
1178
a06ea964 1179#endif /* OPCODE_AARCH64_H */
GDB Binutils - Deliverables
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