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a06ea964 NC |
1 | /* AArch64 assembler/disassembler support. |
2 | ||
b90efa5b | 3 | Copyright (C) 2009-2015 Free Software Foundation, Inc. |
a06ea964 NC |
4 | Contributed by ARM Ltd. |
5 | ||
6 | This file is part of GNU Binutils. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the license, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; see the file COPYING3. If not, | |
20 | see <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #ifndef OPCODE_AARCH64_H | |
23 | #define OPCODE_AARCH64_H | |
24 | ||
25 | #include "bfd.h" | |
26 | #include "bfd_stdint.h" | |
27 | #include <assert.h> | |
28 | #include <stdlib.h> | |
29 | ||
d3e12b29 YQ |
30 | #ifdef __cplusplus |
31 | extern "C" { | |
32 | #endif | |
33 | ||
a06ea964 NC |
34 | /* The offset for pc-relative addressing is currently defined to be 0. */ |
35 | #define AARCH64_PCREL_OFFSET 0 | |
36 | ||
37 | typedef uint32_t aarch64_insn; | |
38 | ||
39 | /* The following bitmasks control CPU features. */ | |
40 | #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ | |
acb787b0 | 41 | #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */ |
a06ea964 NC |
42 | #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */ |
43 | #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ | |
44 | #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ | |
e60bb1dd | 45 | #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */ |
ee804238 | 46 | #define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */ |
f21cce2c | 47 | #define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */ |
290806fd | 48 | #define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */ |
9e1f0fa7 | 49 | #define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */ |
250aafa4 | 50 | #define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */ |
af117b3c | 51 | #define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */ |
a06ea964 NC |
52 | |
53 | /* Architectures are the sum of the base and extensions. */ | |
54 | #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ | |
55 | AARCH64_FEATURE_FP \ | |
56 | | AARCH64_FEATURE_SIMD) | |
88f0ea34 MW |
57 | #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ |
58 | AARCH64_FEATURE_FP \ | |
59 | | AARCH64_FEATURE_SIMD \ | |
af117b3c | 60 | | AARCH64_FEATURE_CRC \ |
250aafa4 | 61 | | AARCH64_FEATURE_V8_1 \ |
88f0ea34 MW |
62 | | AARCH64_FEATURE_LSE \ |
63 | | AARCH64_FEATURE_PAN \ | |
64 | | AARCH64_FEATURE_LOR \ | |
65 | | AARCH64_FEATURE_RDMA) | |
acb787b0 MW |
66 | #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ |
67 | AARCH64_FEATURE_V8_2 \ | |
87018195 | 68 | | AARCH64_FEATURE_F16 \ |
acb787b0 | 69 | | AARCH64_FEATURE_FP \ |
af117b3c MW |
70 | | AARCH64_FEATURE_SIMD \ |
71 | | AARCH64_FEATURE_CRC \ | |
72 | | AARCH64_FEATURE_V8_1 \ | |
acb787b0 MW |
73 | | AARCH64_FEATURE_LSE \ |
74 | | AARCH64_FEATURE_PAN \ | |
75 | | AARCH64_FEATURE_LOR \ | |
76 | | AARCH64_FEATURE_RDMA) | |
88f0ea34 | 77 | |
a06ea964 NC |
78 | #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) |
79 | #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ | |
80 | ||
81 | /* CPU-specific features. */ | |
82 | typedef unsigned long aarch64_feature_set; | |
83 | ||
84 | #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ | |
85 | (((CPU) & (FEAT)) != 0) | |
86 | ||
87 | #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ | |
88 | do \ | |
89 | { \ | |
90 | (TARG) = (F1) | (F2); \ | |
91 | } \ | |
92 | while (0) | |
93 | ||
94 | #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \ | |
95 | do \ | |
96 | { \ | |
97 | (TARG) = (F1) &~ (F2); \ | |
98 | } \ | |
99 | while (0) | |
100 | ||
101 | #define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) | |
102 | ||
103 | #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \ | |
104 | (((OPC) & (FEAT)) != 0) | |
105 | ||
106 | enum aarch64_operand_class | |
107 | { | |
108 | AARCH64_OPND_CLASS_NIL, | |
109 | AARCH64_OPND_CLASS_INT_REG, | |
110 | AARCH64_OPND_CLASS_MODIFIED_REG, | |
111 | AARCH64_OPND_CLASS_FP_REG, | |
112 | AARCH64_OPND_CLASS_SIMD_REG, | |
113 | AARCH64_OPND_CLASS_SIMD_ELEMENT, | |
114 | AARCH64_OPND_CLASS_SISD_REG, | |
115 | AARCH64_OPND_CLASS_SIMD_REGLIST, | |
116 | AARCH64_OPND_CLASS_CP_REG, | |
117 | AARCH64_OPND_CLASS_ADDRESS, | |
118 | AARCH64_OPND_CLASS_IMMEDIATE, | |
119 | AARCH64_OPND_CLASS_SYSTEM, | |
68a64283 | 120 | AARCH64_OPND_CLASS_COND, |
a06ea964 NC |
121 | }; |
122 | ||
123 | /* Operand code that helps both parsing and coding. | |
124 | Keep AARCH64_OPERANDS synced. */ | |
125 | ||
126 | enum aarch64_opnd | |
127 | { | |
128 | AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/ | |
129 | ||
130 | AARCH64_OPND_Rd, /* Integer register as destination. */ | |
131 | AARCH64_OPND_Rn, /* Integer register as source. */ | |
132 | AARCH64_OPND_Rm, /* Integer register as source. */ | |
133 | AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ | |
134 | AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ | |
135 | AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ | |
136 | AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ | |
137 | AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */ | |
138 | ||
139 | AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ | |
140 | AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ | |
ee804238 | 141 | AARCH64_OPND_PAIRREG, /* Paired register operand. */ |
a06ea964 NC |
142 | AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ |
143 | AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ | |
144 | ||
145 | AARCH64_OPND_Fd, /* Floating-point Fd. */ | |
146 | AARCH64_OPND_Fn, /* Floating-point Fn. */ | |
147 | AARCH64_OPND_Fm, /* Floating-point Fm. */ | |
148 | AARCH64_OPND_Fa, /* Floating-point Fa. */ | |
149 | AARCH64_OPND_Ft, /* Floating-point Ft. */ | |
150 | AARCH64_OPND_Ft2, /* Floating-point Ft2. */ | |
151 | ||
152 | AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */ | |
153 | AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ | |
154 | AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ | |
155 | ||
156 | AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ | |
157 | AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ | |
158 | AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ | |
159 | AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */ | |
160 | AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */ | |
161 | AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ | |
162 | AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ | |
163 | AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ | |
164 | AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ | |
165 | AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ | |
166 | AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single | |
167 | structure to all lanes. */ | |
168 | AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ | |
169 | ||
170 | AARCH64_OPND_Cn, /* Co-processor register in CRn field. */ | |
171 | AARCH64_OPND_Cm, /* Co-processor register in CRm field. */ | |
172 | ||
173 | AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ | |
174 | AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ | |
175 | AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ | |
176 | AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ | |
177 | AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */ | |
178 | AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */ | |
179 | AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction | |
180 | (no encoding). */ | |
181 | AARCH64_OPND_IMM0, /* Immediate for #0. */ | |
182 | AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */ | |
183 | AARCH64_OPND_FPIMM, /* Floating-point Immediate. */ | |
184 | AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */ | |
185 | AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */ | |
186 | AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ | |
187 | AARCH64_OPND_IMM, /* Immediate. */ | |
188 | AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ | |
189 | AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ | |
190 | AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ | |
191 | AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */ | |
192 | AARCH64_OPND_BIT_NUM, /* Immediate. */ | |
193 | AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ | |
194 | AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ | |
195 | AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for | |
196 | each condition flag. */ | |
197 | ||
198 | AARCH64_OPND_LIMM, /* Logical Immediate. */ | |
199 | AARCH64_OPND_AIMM, /* Arithmetic immediate. */ | |
200 | AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ | |
201 | AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ | |
202 | AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ | |
203 | ||
204 | AARCH64_OPND_COND, /* Standard condition as the last operand. */ | |
68a64283 | 205 | AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ |
a06ea964 NC |
206 | |
207 | AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ | |
208 | AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ | |
209 | AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ | |
210 | AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ | |
211 | AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ | |
212 | ||
213 | AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ | |
214 | AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ | |
215 | AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ | |
216 | AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ | |
217 | AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is | |
218 | negative or unaligned and there is | |
219 | no writeback allowed. This operand code | |
220 | is only used to support the programmer- | |
221 | friendly feature of using LDR/STR as the | |
222 | the mnemonic name for LDUR/STUR instructions | |
223 | wherever there is no ambiguity. */ | |
224 | AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ | |
225 | AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ | |
226 | AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ | |
227 | ||
228 | AARCH64_OPND_SYSREG, /* System register operand. */ | |
229 | AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */ | |
230 | AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */ | |
231 | AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ | |
232 | AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ | |
233 | AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ | |
234 | AARCH64_OPND_BARRIER, /* Barrier operand. */ | |
235 | AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ | |
236 | AARCH64_OPND_PRFOP, /* Prefetch operation. */ | |
237 | }; | |
238 | ||
239 | /* Qualifier constrains an operand. It either specifies a variant of an | |
240 | operand type or limits values available to an operand type. | |
241 | ||
242 | N.B. Order is important; keep aarch64_opnd_qualifiers synced. */ | |
243 | ||
244 | enum aarch64_opnd_qualifier | |
245 | { | |
246 | /* Indicating no further qualification on an operand. */ | |
247 | AARCH64_OPND_QLF_NIL, | |
248 | ||
249 | /* Qualifying an operand which is a general purpose (integer) register; | |
250 | indicating the operand data size or a specific register. */ | |
251 | AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */ | |
252 | AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */ | |
253 | AARCH64_OPND_QLF_WSP, /* WSP. */ | |
254 | AARCH64_OPND_QLF_SP, /* SP. */ | |
255 | ||
256 | /* Qualifying an operand which is a floating-point register, a SIMD | |
257 | vector element or a SIMD vector element list; indicating operand data | |
258 | size or the size of each SIMD vector element in the case of a SIMD | |
259 | vector element list. | |
260 | These qualifiers are also used to qualify an address operand to | |
261 | indicate the size of data element a load/store instruction is | |
262 | accessing. | |
263 | They are also used for the immediate shift operand in e.g. SSHR. Such | |
264 | a use is only for the ease of operand encoding/decoding and qualifier | |
265 | sequence matching; such a use should not be applied widely; use the value | |
266 | constraint qualifiers for immediate operands wherever possible. */ | |
267 | AARCH64_OPND_QLF_S_B, | |
268 | AARCH64_OPND_QLF_S_H, | |
269 | AARCH64_OPND_QLF_S_S, | |
270 | AARCH64_OPND_QLF_S_D, | |
271 | AARCH64_OPND_QLF_S_Q, | |
272 | ||
273 | /* Qualifying an operand which is a SIMD vector register or a SIMD vector | |
274 | register list; indicating register shape. | |
275 | They are also used for the immediate shift operand in e.g. SSHR. Such | |
276 | a use is only for the ease of operand encoding/decoding and qualifier | |
277 | sequence matching; such a use should not be applied widely; use the value | |
278 | constraint qualifiers for immediate operands wherever possible. */ | |
279 | AARCH64_OPND_QLF_V_8B, | |
280 | AARCH64_OPND_QLF_V_16B, | |
281 | AARCH64_OPND_QLF_V_4H, | |
282 | AARCH64_OPND_QLF_V_8H, | |
283 | AARCH64_OPND_QLF_V_2S, | |
284 | AARCH64_OPND_QLF_V_4S, | |
285 | AARCH64_OPND_QLF_V_1D, | |
286 | AARCH64_OPND_QLF_V_2D, | |
287 | AARCH64_OPND_QLF_V_1Q, | |
288 | ||
289 | /* Constraint on value. */ | |
290 | AARCH64_OPND_QLF_imm_0_7, | |
291 | AARCH64_OPND_QLF_imm_0_15, | |
292 | AARCH64_OPND_QLF_imm_0_31, | |
293 | AARCH64_OPND_QLF_imm_0_63, | |
294 | AARCH64_OPND_QLF_imm_1_32, | |
295 | AARCH64_OPND_QLF_imm_1_64, | |
296 | ||
297 | /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros | |
298 | or shift-ones. */ | |
299 | AARCH64_OPND_QLF_LSL, | |
300 | AARCH64_OPND_QLF_MSL, | |
301 | ||
302 | /* Special qualifier helping retrieve qualifier information during the | |
303 | decoding time (currently not in use). */ | |
304 | AARCH64_OPND_QLF_RETRIEVE, | |
305 | }; | |
306 | \f | |
307 | /* Instruction class. */ | |
308 | ||
309 | enum aarch64_insn_class | |
310 | { | |
311 | addsub_carry, | |
312 | addsub_ext, | |
313 | addsub_imm, | |
314 | addsub_shift, | |
315 | asimdall, | |
316 | asimddiff, | |
317 | asimdelem, | |
318 | asimdext, | |
319 | asimdimm, | |
320 | asimdins, | |
321 | asimdmisc, | |
322 | asimdperm, | |
323 | asimdsame, | |
324 | asimdshf, | |
325 | asimdtbl, | |
326 | asisddiff, | |
327 | asisdelem, | |
328 | asisdlse, | |
329 | asisdlsep, | |
330 | asisdlso, | |
331 | asisdlsop, | |
332 | asisdmisc, | |
333 | asisdone, | |
334 | asisdpair, | |
335 | asisdsame, | |
336 | asisdshf, | |
337 | bitfield, | |
338 | branch_imm, | |
339 | branch_reg, | |
340 | compbranch, | |
341 | condbranch, | |
342 | condcmp_imm, | |
343 | condcmp_reg, | |
344 | condsel, | |
345 | cryptoaes, | |
346 | cryptosha2, | |
347 | cryptosha3, | |
348 | dp_1src, | |
349 | dp_2src, | |
350 | dp_3src, | |
351 | exception, | |
352 | extract, | |
353 | float2fix, | |
354 | float2int, | |
355 | floatccmp, | |
356 | floatcmp, | |
357 | floatdp1, | |
358 | floatdp2, | |
359 | floatdp3, | |
360 | floatimm, | |
361 | floatsel, | |
362 | ldst_immpost, | |
363 | ldst_immpre, | |
364 | ldst_imm9, /* immpost or immpre */ | |
365 | ldst_pos, | |
366 | ldst_regoff, | |
367 | ldst_unpriv, | |
368 | ldst_unscaled, | |
369 | ldstexcl, | |
370 | ldstnapair_offs, | |
371 | ldstpair_off, | |
372 | ldstpair_indexed, | |
373 | loadlit, | |
374 | log_imm, | |
375 | log_shift, | |
ee804238 | 376 | lse_atomic, |
a06ea964 NC |
377 | movewide, |
378 | pcreladdr, | |
379 | ic_system, | |
380 | testbranch, | |
381 | }; | |
382 | ||
383 | /* Opcode enumerators. */ | |
384 | ||
385 | enum aarch64_op | |
386 | { | |
387 | OP_NIL, | |
388 | OP_STRB_POS, | |
389 | OP_LDRB_POS, | |
390 | OP_LDRSB_POS, | |
391 | OP_STRH_POS, | |
392 | OP_LDRH_POS, | |
393 | OP_LDRSH_POS, | |
394 | OP_STR_POS, | |
395 | OP_LDR_POS, | |
396 | OP_STRF_POS, | |
397 | OP_LDRF_POS, | |
398 | OP_LDRSW_POS, | |
399 | OP_PRFM_POS, | |
400 | ||
401 | OP_STURB, | |
402 | OP_LDURB, | |
403 | OP_LDURSB, | |
404 | OP_STURH, | |
405 | OP_LDURH, | |
406 | OP_LDURSH, | |
407 | OP_STUR, | |
408 | OP_LDUR, | |
409 | OP_STURV, | |
410 | OP_LDURV, | |
411 | OP_LDURSW, | |
412 | OP_PRFUM, | |
413 | ||
414 | OP_LDR_LIT, | |
415 | OP_LDRV_LIT, | |
416 | OP_LDRSW_LIT, | |
417 | OP_PRFM_LIT, | |
418 | ||
419 | OP_ADD, | |
420 | OP_B, | |
421 | OP_BL, | |
422 | ||
423 | OP_MOVN, | |
424 | OP_MOVZ, | |
425 | OP_MOVK, | |
426 | ||
427 | OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */ | |
428 | OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */ | |
429 | OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */ | |
430 | ||
431 | OP_MOV_V, /* MOV alias for moving vector register. */ | |
432 | ||
433 | OP_ASR_IMM, | |
434 | OP_LSR_IMM, | |
435 | OP_LSL_IMM, | |
436 | ||
437 | OP_BIC, | |
438 | ||
439 | OP_UBFX, | |
440 | OP_BFXIL, | |
441 | OP_SBFX, | |
442 | OP_SBFIZ, | |
443 | OP_BFI, | |
d685192a | 444 | OP_BFC, /* ARMv8.2. */ |
a06ea964 NC |
445 | OP_UBFIZ, |
446 | OP_UXTB, | |
447 | OP_UXTH, | |
448 | OP_UXTW, | |
449 | ||
a06ea964 NC |
450 | OP_CINC, |
451 | OP_CINV, | |
452 | OP_CNEG, | |
453 | OP_CSET, | |
454 | OP_CSETM, | |
455 | ||
456 | OP_FCVT, | |
457 | OP_FCVTN, | |
458 | OP_FCVTN2, | |
459 | OP_FCVTL, | |
460 | OP_FCVTL2, | |
461 | OP_FCVTXN_S, /* Scalar version. */ | |
462 | ||
463 | OP_ROR_IMM, | |
464 | ||
e30181a5 YZ |
465 | OP_SXTL, |
466 | OP_SXTL2, | |
467 | OP_UXTL, | |
468 | OP_UXTL2, | |
469 | ||
a06ea964 NC |
470 | OP_TOTAL_NUM, /* Pseudo. */ |
471 | }; | |
472 | ||
473 | /* Maximum number of operands an instruction can have. */ | |
474 | #define AARCH64_MAX_OPND_NUM 6 | |
475 | /* Maximum number of qualifier sequences an instruction can have. */ | |
476 | #define AARCH64_MAX_QLF_SEQ_NUM 10 | |
477 | /* Operand qualifier typedef; optimized for the size. */ | |
478 | typedef unsigned char aarch64_opnd_qualifier_t; | |
479 | /* Operand qualifier sequence typedef. */ | |
480 | typedef aarch64_opnd_qualifier_t \ | |
481 | aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; | |
482 | ||
483 | /* FIXME: improve the efficiency. */ | |
484 | static inline bfd_boolean | |
485 | empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) | |
486 | { | |
487 | int i; | |
488 | for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) | |
489 | if (qualifiers[i] != AARCH64_OPND_QLF_NIL) | |
490 | return FALSE; | |
491 | return TRUE; | |
492 | } | |
493 | ||
494 | /* This structure holds information for a particular opcode. */ | |
495 | ||
496 | struct aarch64_opcode | |
497 | { | |
498 | /* The name of the mnemonic. */ | |
499 | const char *name; | |
500 | ||
501 | /* The opcode itself. Those bits which will be filled in with | |
502 | operands are zeroes. */ | |
503 | aarch64_insn opcode; | |
504 | ||
505 | /* The opcode mask. This is used by the disassembler. This is a | |
506 | mask containing ones indicating those bits which must match the | |
507 | opcode field, and zeroes indicating those bits which need not | |
508 | match (and are presumably filled in by operands). */ | |
509 | aarch64_insn mask; | |
510 | ||
511 | /* Instruction class. */ | |
512 | enum aarch64_insn_class iclass; | |
513 | ||
514 | /* Enumerator identifier. */ | |
515 | enum aarch64_op op; | |
516 | ||
517 | /* Which architecture variant provides this instruction. */ | |
518 | const aarch64_feature_set *avariant; | |
519 | ||
520 | /* An array of operand codes. Each code is an index into the | |
521 | operand table. They appear in the order which the operands must | |
522 | appear in assembly code, and are terminated by a zero. */ | |
523 | enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM]; | |
524 | ||
525 | /* A list of operand qualifier code sequence. Each operand qualifier | |
526 | code qualifies the corresponding operand code. Each operand | |
527 | qualifier sequence specifies a valid opcode variant and related | |
528 | constraint on operands. */ | |
529 | aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM]; | |
530 | ||
531 | /* Flags providing information about this instruction */ | |
532 | uint32_t flags; | |
533 | }; | |
534 | ||
535 | typedef struct aarch64_opcode aarch64_opcode; | |
536 | ||
537 | /* Table describing all the AArch64 opcodes. */ | |
538 | extern aarch64_opcode aarch64_opcode_table[]; | |
539 | ||
540 | /* Opcode flags. */ | |
541 | #define F_ALIAS (1 << 0) | |
542 | #define F_HAS_ALIAS (1 << 1) | |
543 | /* Disassembly preference priority 1-3 (the larger the higher). If nothing | |
544 | is specified, it is the priority 0 by default, i.e. the lowest priority. */ | |
545 | #define F_P1 (1 << 2) | |
546 | #define F_P2 (2 << 2) | |
547 | #define F_P3 (3 << 2) | |
548 | /* Flag an instruction that is truly conditional executed, e.g. b.cond. */ | |
549 | #define F_COND (1 << 4) | |
550 | /* Instruction has the field of 'sf'. */ | |
551 | #define F_SF (1 << 5) | |
552 | /* Instruction has the field of 'size:Q'. */ | |
553 | #define F_SIZEQ (1 << 6) | |
554 | /* Floating-point instruction has the field of 'type'. */ | |
555 | #define F_FPTYPE (1 << 7) | |
556 | /* AdvSIMD scalar instruction has the field of 'size'. */ | |
557 | #define F_SSIZE (1 << 8) | |
558 | /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */ | |
559 | #define F_T (1 << 9) | |
560 | /* Size of GPR operand in AdvSIMD instructions encoded in Q. */ | |
561 | #define F_GPRSIZE_IN_Q (1 << 10) | |
562 | /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */ | |
563 | #define F_LDS_SIZE (1 << 11) | |
564 | /* Optional operand; assume maximum of 1 operand can be optional. */ | |
565 | #define F_OPD0_OPT (1 << 12) | |
566 | #define F_OPD1_OPT (2 << 12) | |
567 | #define F_OPD2_OPT (3 << 12) | |
568 | #define F_OPD3_OPT (4 << 12) | |
569 | #define F_OPD4_OPT (5 << 12) | |
570 | /* Default value for the optional operand when omitted from the assembly. */ | |
571 | #define F_DEFAULT(X) (((X) & 0x1f) << 15) | |
572 | /* Instruction that is an alias of another instruction needs to be | |
573 | encoded/decoded by converting it to/from the real form, followed by | |
574 | the encoding/decoding according to the rules of the real opcode. | |
575 | This compares to the direct coding using the alias's information. | |
576 | N.B. this flag requires F_ALIAS to be used together. */ | |
577 | #define F_CONV (1 << 20) | |
578 | /* Use together with F_ALIAS to indicate an alias opcode is a programmer | |
579 | friendly pseudo instruction available only in the assembly code (thus will | |
580 | not show up in the disassembly). */ | |
581 | #define F_PSEUDO (1 << 21) | |
582 | /* Instruction has miscellaneous encoding/decoding rules. */ | |
583 | #define F_MISC (1 << 22) | |
584 | /* Instruction has the field of 'N'; used in conjunction with F_SF. */ | |
585 | #define F_N (1 << 23) | |
586 | /* Opcode dependent field. */ | |
587 | #define F_OD(X) (((X) & 0x7) << 24) | |
ee804238 JW |
588 | /* Instruction has the field of 'sz'. */ |
589 | #define F_LSE_SZ (1 << 27) | |
590 | /* Next bit is 28. */ | |
a06ea964 NC |
591 | |
592 | static inline bfd_boolean | |
593 | alias_opcode_p (const aarch64_opcode *opcode) | |
594 | { | |
595 | return (opcode->flags & F_ALIAS) ? TRUE : FALSE; | |
596 | } | |
597 | ||
598 | static inline bfd_boolean | |
599 | opcode_has_alias (const aarch64_opcode *opcode) | |
600 | { | |
601 | return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE; | |
602 | } | |
603 | ||
604 | /* Priority for disassembling preference. */ | |
605 | static inline int | |
606 | opcode_priority (const aarch64_opcode *opcode) | |
607 | { | |
608 | return (opcode->flags >> 2) & 0x3; | |
609 | } | |
610 | ||
611 | static inline bfd_boolean | |
612 | pseudo_opcode_p (const aarch64_opcode *opcode) | |
613 | { | |
614 | return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE; | |
615 | } | |
616 | ||
617 | static inline bfd_boolean | |
618 | optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) | |
619 | { | |
620 | return (((opcode->flags >> 12) & 0x7) == idx + 1) | |
621 | ? TRUE : FALSE; | |
622 | } | |
623 | ||
624 | static inline aarch64_insn | |
625 | get_optional_operand_default_value (const aarch64_opcode *opcode) | |
626 | { | |
627 | return (opcode->flags >> 15) & 0x1f; | |
628 | } | |
629 | ||
630 | static inline unsigned int | |
631 | get_opcode_dependent_value (const aarch64_opcode *opcode) | |
632 | { | |
633 | return (opcode->flags >> 24) & 0x7; | |
634 | } | |
635 | ||
636 | static inline bfd_boolean | |
637 | opcode_has_special_coder (const aarch64_opcode *opcode) | |
638 | { | |
ee804238 | 639 | return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T |
a06ea964 NC |
640 | | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE |
641 | : FALSE; | |
642 | } | |
643 | \f | |
644 | struct aarch64_name_value_pair | |
645 | { | |
646 | const char * name; | |
647 | aarch64_insn value; | |
648 | }; | |
649 | ||
650 | extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; | |
a06ea964 NC |
651 | extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; |
652 | extern const struct aarch64_name_value_pair aarch64_prfops [32]; | |
653 | ||
49eec193 YZ |
654 | typedef struct |
655 | { | |
656 | const char * name; | |
657 | aarch64_insn value; | |
658 | uint32_t flags; | |
659 | } aarch64_sys_reg; | |
660 | ||
661 | extern const aarch64_sys_reg aarch64_sys_regs []; | |
87b8eed7 | 662 | extern const aarch64_sys_reg aarch64_pstatefields []; |
49eec193 | 663 | extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *); |
f21cce2c MW |
664 | extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set, |
665 | const aarch64_sys_reg *); | |
666 | extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set, | |
667 | const aarch64_sys_reg *); | |
49eec193 | 668 | |
a06ea964 NC |
669 | typedef struct |
670 | { | |
875880c6 | 671 | const char *name; |
a06ea964 NC |
672 | uint32_t value; |
673 | int has_xt; | |
674 | } aarch64_sys_ins_reg; | |
675 | ||
676 | extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; | |
677 | extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; | |
678 | extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; | |
679 | extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi []; | |
680 | ||
681 | /* Shift/extending operator kinds. | |
682 | N.B. order is important; keep aarch64_operand_modifiers synced. */ | |
683 | enum aarch64_modifier_kind | |
684 | { | |
685 | AARCH64_MOD_NONE, | |
686 | AARCH64_MOD_MSL, | |
687 | AARCH64_MOD_ROR, | |
688 | AARCH64_MOD_ASR, | |
689 | AARCH64_MOD_LSR, | |
690 | AARCH64_MOD_LSL, | |
691 | AARCH64_MOD_UXTB, | |
692 | AARCH64_MOD_UXTH, | |
693 | AARCH64_MOD_UXTW, | |
694 | AARCH64_MOD_UXTX, | |
695 | AARCH64_MOD_SXTB, | |
696 | AARCH64_MOD_SXTH, | |
697 | AARCH64_MOD_SXTW, | |
698 | AARCH64_MOD_SXTX, | |
699 | }; | |
700 | ||
701 | bfd_boolean | |
702 | aarch64_extend_operator_p (enum aarch64_modifier_kind); | |
703 | ||
704 | enum aarch64_modifier_kind | |
705 | aarch64_get_operand_modifier (const struct aarch64_name_value_pair *); | |
706 | /* Condition. */ | |
707 | ||
708 | typedef struct | |
709 | { | |
710 | /* A list of names with the first one as the disassembly preference; | |
711 | terminated by NULL if fewer than 3. */ | |
712 | const char *names[3]; | |
713 | aarch64_insn value; | |
714 | } aarch64_cond; | |
715 | ||
716 | extern const aarch64_cond aarch64_conds[16]; | |
717 | ||
718 | const aarch64_cond* get_cond_from_value (aarch64_insn value); | |
719 | const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); | |
720 | \f | |
721 | /* Structure representing an operand. */ | |
722 | ||
723 | struct aarch64_opnd_info | |
724 | { | |
725 | enum aarch64_opnd type; | |
726 | aarch64_opnd_qualifier_t qualifier; | |
727 | int idx; | |
728 | ||
729 | union | |
730 | { | |
731 | struct | |
732 | { | |
733 | unsigned regno; | |
734 | } reg; | |
735 | struct | |
736 | { | |
737 | unsigned regno : 5; | |
738 | unsigned index : 4; | |
739 | } reglane; | |
740 | /* e.g. LVn. */ | |
741 | struct | |
742 | { | |
743 | unsigned first_regno : 5; | |
744 | unsigned num_regs : 3; | |
745 | /* 1 if it is a list of reg element. */ | |
746 | unsigned has_index : 1; | |
747 | /* Lane index; valid only when has_index is 1. */ | |
748 | unsigned index : 4; | |
749 | } reglist; | |
750 | /* e.g. immediate or pc relative address offset. */ | |
751 | struct | |
752 | { | |
753 | int64_t value; | |
754 | unsigned is_fp : 1; | |
755 | } imm; | |
756 | /* e.g. address in STR (register offset). */ | |
757 | struct | |
758 | { | |
759 | unsigned base_regno; | |
760 | struct | |
761 | { | |
762 | union | |
763 | { | |
764 | int imm; | |
765 | unsigned regno; | |
766 | }; | |
767 | unsigned is_reg; | |
768 | } offset; | |
769 | unsigned pcrel : 1; /* PC-relative. */ | |
770 | unsigned writeback : 1; | |
771 | unsigned preind : 1; /* Pre-indexed. */ | |
772 | unsigned postind : 1; /* Post-indexed. */ | |
773 | } addr; | |
774 | const aarch64_cond *cond; | |
775 | /* The encoding of the system register. */ | |
776 | aarch64_insn sysreg; | |
777 | /* The encoding of the PSTATE field. */ | |
778 | aarch64_insn pstatefield; | |
779 | const aarch64_sys_ins_reg *sysins_op; | |
780 | const struct aarch64_name_value_pair *barrier; | |
781 | const struct aarch64_name_value_pair *prfop; | |
782 | }; | |
783 | ||
784 | /* Operand shifter; in use when the operand is a register offset address, | |
785 | add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */ | |
786 | struct | |
787 | { | |
788 | enum aarch64_modifier_kind kind; | |
789 | int amount; | |
790 | unsigned operator_present: 1; /* Only valid during encoding. */ | |
791 | /* Value of the 'S' field in ld/st reg offset; used only in decoding. */ | |
792 | unsigned amount_present: 1; | |
793 | } shifter; | |
794 | ||
795 | unsigned skip:1; /* Operand is not completed if there is a fixup needed | |
796 | to be done on it. In some (but not all) of these | |
797 | cases, we need to tell libopcodes to skip the | |
798 | constraint checking and the encoding for this | |
799 | operand, so that the libopcodes can pick up the | |
800 | right opcode before the operand is fixed-up. This | |
801 | flag should only be used during the | |
802 | assembling/encoding. */ | |
803 | unsigned present:1; /* Whether this operand is present in the assembly | |
804 | line; not used during the disassembly. */ | |
805 | }; | |
806 | ||
807 | typedef struct aarch64_opnd_info aarch64_opnd_info; | |
808 | ||
809 | /* Structure representing an instruction. | |
810 | ||
811 | It is used during both the assembling and disassembling. The assembler | |
812 | fills an aarch64_inst after a successful parsing and then passes it to the | |
813 | encoding routine to do the encoding. During the disassembling, the | |
814 | disassembler calls the decoding routine to decode a binary instruction; on a | |
815 | successful return, such a structure will be filled with information of the | |
816 | instruction; then the disassembler uses the information to print out the | |
817 | instruction. */ | |
818 | ||
819 | struct aarch64_inst | |
820 | { | |
821 | /* The value of the binary instruction. */ | |
822 | aarch64_insn value; | |
823 | ||
824 | /* Corresponding opcode entry. */ | |
825 | const aarch64_opcode *opcode; | |
826 | ||
827 | /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ | |
828 | const aarch64_cond *cond; | |
829 | ||
830 | /* Operands information. */ | |
831 | aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; | |
832 | }; | |
833 | ||
834 | typedef struct aarch64_inst aarch64_inst; | |
835 | \f | |
836 | /* Diagnosis related declaration and interface. */ | |
837 | ||
838 | /* Operand error kind enumerators. | |
839 | ||
840 | AARCH64_OPDE_RECOVERABLE | |
841 | Less severe error found during the parsing, very possibly because that | |
842 | GAS has picked up a wrong instruction template for the parsing. | |
843 | ||
844 | AARCH64_OPDE_SYNTAX_ERROR | |
845 | General syntax error; it can be either a user error, or simply because | |
846 | that GAS is trying a wrong instruction template. | |
847 | ||
848 | AARCH64_OPDE_FATAL_SYNTAX_ERROR | |
849 | Definitely a user syntax error. | |
850 | ||
851 | AARCH64_OPDE_INVALID_VARIANT | |
852 | No syntax error, but the operands are not a valid combination, e.g. | |
853 | FMOV D0,S0 | |
854 | ||
855 | AARCH64_OPDE_OUT_OF_RANGE | |
856 | Error about some immediate value out of a valid range. | |
857 | ||
858 | AARCH64_OPDE_UNALIGNED | |
859 | Error about some immediate value not properly aligned (i.e. not being a | |
860 | multiple times of a certain value). | |
861 | ||
862 | AARCH64_OPDE_REG_LIST | |
863 | Error about the register list operand having unexpected number of | |
864 | registers. | |
865 | ||
866 | AARCH64_OPDE_OTHER_ERROR | |
867 | Error of the highest severity and used for any severe issue that does not | |
868 | fall into any of the above categories. | |
869 | ||
870 | The enumerators are only interesting to GAS. They are declared here (in | |
871 | libopcodes) because that some errors are detected (and then notified to GAS) | |
872 | by libopcodes (rather than by GAS solely). | |
873 | ||
874 | The first three errors are only deteced by GAS while the | |
875 | AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as | |
876 | only libopcodes has the information about the valid variants of each | |
877 | instruction. | |
878 | ||
879 | The enumerators have an increasing severity. This is helpful when there are | |
880 | multiple instruction templates available for a given mnemonic name (e.g. | |
881 | FMOV); this mechanism will help choose the most suitable template from which | |
882 | the generated diagnostics can most closely describe the issues, if any. */ | |
883 | ||
884 | enum aarch64_operand_error_kind | |
885 | { | |
886 | AARCH64_OPDE_NIL, | |
887 | AARCH64_OPDE_RECOVERABLE, | |
888 | AARCH64_OPDE_SYNTAX_ERROR, | |
889 | AARCH64_OPDE_FATAL_SYNTAX_ERROR, | |
890 | AARCH64_OPDE_INVALID_VARIANT, | |
891 | AARCH64_OPDE_OUT_OF_RANGE, | |
892 | AARCH64_OPDE_UNALIGNED, | |
893 | AARCH64_OPDE_REG_LIST, | |
894 | AARCH64_OPDE_OTHER_ERROR | |
895 | }; | |
896 | ||
897 | /* N.B. GAS assumes that this structure work well with shallow copy. */ | |
898 | struct aarch64_operand_error | |
899 | { | |
900 | enum aarch64_operand_error_kind kind; | |
901 | int index; | |
902 | const char *error; | |
903 | int data[3]; /* Some data for extra information. */ | |
904 | }; | |
905 | ||
906 | typedef struct aarch64_operand_error aarch64_operand_error; | |
907 | ||
908 | /* Encoding entrypoint. */ | |
909 | ||
910 | extern int | |
911 | aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, | |
912 | aarch64_insn *, aarch64_opnd_qualifier_t *, | |
913 | aarch64_operand_error *); | |
914 | ||
915 | extern const aarch64_opcode * | |
916 | aarch64_replace_opcode (struct aarch64_inst *, | |
917 | const aarch64_opcode *); | |
918 | ||
919 | /* Given the opcode enumerator OP, return the pointer to the corresponding | |
920 | opcode entry. */ | |
921 | ||
922 | extern const aarch64_opcode * | |
923 | aarch64_get_opcode (enum aarch64_op); | |
924 | ||
925 | /* Generate the string representation of an operand. */ | |
926 | extern void | |
927 | aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, | |
928 | const aarch64_opnd_info *, int, int *, bfd_vma *); | |
929 | ||
930 | /* Miscellaneous interface. */ | |
931 | ||
932 | extern int | |
933 | aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd); | |
934 | ||
935 | extern aarch64_opnd_qualifier_t | |
936 | aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, | |
937 | const aarch64_opnd_qualifier_t, int); | |
938 | ||
939 | extern int | |
940 | aarch64_num_of_operands (const aarch64_opcode *); | |
941 | ||
942 | extern int | |
943 | aarch64_stack_pointer_p (const aarch64_opnd_info *); | |
944 | ||
e141d84e YQ |
945 | extern int |
946 | aarch64_zero_register_p (const aarch64_opnd_info *); | |
a06ea964 | 947 | |
36f4aab1 | 948 | extern int |
43cdf5ae | 949 | aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean); |
36f4aab1 | 950 | |
a06ea964 NC |
951 | /* Given an operand qualifier, return the expected data element size |
952 | of a qualified operand. */ | |
953 | extern unsigned char | |
954 | aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t); | |
955 | ||
956 | extern enum aarch64_operand_class | |
957 | aarch64_get_operand_class (enum aarch64_opnd); | |
958 | ||
959 | extern const char * | |
960 | aarch64_get_operand_name (enum aarch64_opnd); | |
961 | ||
962 | extern const char * | |
963 | aarch64_get_operand_desc (enum aarch64_opnd); | |
964 | ||
965 | #ifdef DEBUG_AARCH64 | |
966 | extern int debug_dump; | |
967 | ||
968 | extern void | |
969 | aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); | |
970 | ||
971 | #define DEBUG_TRACE(M, ...) \ | |
972 | { \ | |
973 | if (debug_dump) \ | |
974 | aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ | |
975 | } | |
976 | ||
977 | #define DEBUG_TRACE_IF(C, M, ...) \ | |
978 | { \ | |
979 | if (debug_dump && (C)) \ | |
980 | aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ | |
981 | } | |
982 | #else /* !DEBUG_AARCH64 */ | |
983 | #define DEBUG_TRACE(M, ...) ; | |
984 | #define DEBUG_TRACE_IF(C, M, ...) ; | |
985 | #endif /* DEBUG_AARCH64 */ | |
986 | ||
d3e12b29 YQ |
987 | #ifdef __cplusplus |
988 | } | |
989 | #endif | |
990 | ||
a06ea964 | 991 | #endif /* OPCODE_AARCH64_H */ |