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[binutils][aarch64] New sve_size_013 iclass.
[deliverable/binutils-gdb.git] / include / opcode / aarch64.h
CommitLineData
a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
82704155 3 Copyright (C) 2009-2019 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
c0e7cef7
NC		 40#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
41#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
b6b9ca0c
TC		 42#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
43#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
44#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
a06ea964 45#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
acb787b0 46#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
1924ff75 47#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
a06ea964
NC		 48#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
49#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
50#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
e60bb1dd 51#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
ee804238 52#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
f21cce2c 53#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
290806fd 54#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
9e1f0fa7 55#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
250aafa4 56#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
af117b3c 57#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
c8a6db6f 58#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
73af8ed6 59#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
c0890d26 60#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
d74d4880 61#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
f482d304 62#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
65a55fbb 63#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
d0f7791c 64#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */
70d56181 65#define AARCH64_FEATURE_V8_5 0x2000000000ULL /* ARMv8.5 processors. */
a06ea964 66
13c60ad7
SD		 67/* Flag Manipulation insns. */
68#define AARCH64_FEATURE_FLAGMANIP 0x4000000000ULL
69/* FRINT[32,64][Z,X] insns. */
70#define AARCH64_FEATURE_FRINTTS 0x8000000000ULL
68dfbb92
SD		 71/* SB instruction. */
72#define AARCH64_FEATURE_SB 0x10000000000ULL
2ac435d4
SD		 73/* Execution and Data Prediction Restriction instructions. */
74#define AARCH64_FEATURE_PREDRES 0x20000000000ULL
3fd229a4
SD		 75/* DC CVADP. */
76#define AARCH64_FEATURE_CVADP 0x40000000000ULL
af4bcb4c
SD		 77/* Random Number instructions. */
78#define AARCH64_FEATURE_RNG 0x80000000000ULL
ff605452
SD		 79/* BTI instructions. */
80#define AARCH64_FEATURE_BTI 0x100000000000ULL
a97330e7
SD		 81/* SCXTNUM_ELx. */
82#define AARCH64_FEATURE_SCXTNUM 0x200000000000ULL
83/* ID_PFR2 instructions. */
84#define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL
104fefee
SD		 85/* SSBS mechanism enabled. */
86#define AARCH64_FEATURE_SSBS 0x800000000000ULL
73b605ec
SD		 87/* Memory Tagging Extension. */
88#define AARCH64_FEATURE_MEMTAG 0x1000000000000ULL
b83b4b13
SD		 89/* Transactional Memory Extension. */
90#define AARCH64_FEATURE_TME 0x2000000000000ULL
13c60ad7 91
7ce2460a
MM		 92/* SVE2 instructions. */
93#define AARCH64_FEATURE_SVE2 0x000000010
94#define AARCH64_FEATURE_SVE2_AES 0x000000080
95#define AARCH64_FEATURE_SVE2_BITPERM 0x000000100
96#define AARCH64_FEATURE_SVE2_SM4 0x000000200
97#define AARCH64_FEATURE_SVE2_SHA3 0x000000400
98
a06ea964
NC		 99/* Architectures are the sum of the base and extensions. */
100#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
101 AARCH64_FEATURE_FP \
102 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 103#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
104 AARCH64_FEATURE_CRC \
250aafa4 105 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 106 | AARCH64_FEATURE_LSE \
107 | AARCH64_FEATURE_PAN \
108 | AARCH64_FEATURE_LOR \
109 | AARCH64_FEATURE_RDMA)
1924ff75 110#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 111 AARCH64_FEATURE_V8_2 \
1924ff75
SN		 112 | AARCH64_FEATURE_RAS)
113#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
d74d4880 114 AARCH64_FEATURE_V8_3 \
f482d304
RS		 115 | AARCH64_FEATURE_RCPC \
116 | AARCH64_FEATURE_COMPNUM)
b6b9ca0c 117#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
981b557a 118 AARCH64_FEATURE_V8_4 \
d0f7791c
TC		 119 | AARCH64_FEATURE_DOTPROD \
120 | AARCH64_FEATURE_F16_FML)
70d56181 121#define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
13c60ad7
SD		 122 AARCH64_FEATURE_V8_5 \
123 | AARCH64_FEATURE_FLAGMANIP \
68dfbb92 124 | AARCH64_FEATURE_FRINTTS \
2ac435d4 125 | AARCH64_FEATURE_SB \
3fd229a4 126 | AARCH64_FEATURE_PREDRES \
ff605452 127 | AARCH64_FEATURE_CVADP \
a97330e7
SD		 128 | AARCH64_FEATURE_BTI \
129 | AARCH64_FEATURE_SCXTNUM \
104fefee
SD		 130 | AARCH64_FEATURE_ID_PFR2 \
131 | AARCH64_FEATURE_SSBS)
70d56181 132
88f0ea34 133
a06ea964
NC		 134#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
135#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
136
137/* CPU-specific features. */
21b81e67 138typedef unsigned long long aarch64_feature_set;
a06ea964 139
93d8990c
SN		 140#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
141 ((~(CPU) & (FEAT)) == 0)
142
143#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 144 (((CPU) & (FEAT)) != 0)
145
93d8990c
SN		 146#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
147 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
148
a06ea964
NC		 149#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
150 do \
151 { \
152 (TARG) = (F1) | (F2); \
153 } \
154 while (0)
155
156#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
157 do \
158 { \
159 (TARG) = (F1) &~ (F2); \
160 } \
161 while (0)
162
163#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
164
a06ea964
NC		 165enum aarch64_operand_class
166{
167 AARCH64_OPND_CLASS_NIL,
168 AARCH64_OPND_CLASS_INT_REG,
169 AARCH64_OPND_CLASS_MODIFIED_REG,
170 AARCH64_OPND_CLASS_FP_REG,
171 AARCH64_OPND_CLASS_SIMD_REG,
172 AARCH64_OPND_CLASS_SIMD_ELEMENT,
173 AARCH64_OPND_CLASS_SISD_REG,
174 AARCH64_OPND_CLASS_SIMD_REGLIST,
f11ad6bc
RS		 175 AARCH64_OPND_CLASS_SVE_REG,
176 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 177 AARCH64_OPND_CLASS_ADDRESS,
178 AARCH64_OPND_CLASS_IMMEDIATE,
179 AARCH64_OPND_CLASS_SYSTEM,
68a64283 180 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 181};
182
183/* Operand code that helps both parsing and coding.
184 Keep AARCH64_OPERANDS synced. */
185
186enum aarch64_opnd
187{
188 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
189
190 AARCH64_OPND_Rd, /* Integer register as destination. */
191 AARCH64_OPND_Rn, /* Integer register as source. */
192 AARCH64_OPND_Rm, /* Integer register as source. */
193 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
194 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
bd7ceb8d 195 AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */
a06ea964
NC		 196 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
197 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
198 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
199
200 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
201 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 202 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 203 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 204 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
205 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
206
207 AARCH64_OPND_Fd, /* Floating-point Fd. */
208 AARCH64_OPND_Fn, /* Floating-point Fn. */
209 AARCH64_OPND_Fm, /* Floating-point Fm. */
210 AARCH64_OPND_Fa, /* Floating-point Fa. */
211 AARCH64_OPND_Ft, /* Floating-point Ft. */
212 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
213
214 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
215 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
216 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
217
f42f1a1d 218 AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
a06ea964
NC		 219 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
220 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
221 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
222 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
223 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
224 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
225 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
226 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
369c9167
TC		 227 AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
228 qualifier is S_H. */
a06ea964
NC		 229 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
230 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
231 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
232 structure to all lanes. */
233 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
234
a6a51754
RL		 235 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
236 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
a06ea964
NC		 237
238 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
f42f1a1d 239 AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */
a06ea964
NC		 240 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
241 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
242 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
243 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
244 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
245 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
246 (no encoding). */
247 AARCH64_OPND_IMM0, /* Immediate for #0. */
248 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
249 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
250 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
251 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
252 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
253 AARCH64_OPND_IMM, /* Immediate. */
f42f1a1d 254 AARCH64_OPND_IMM_2, /* Immediate. */
a06ea964
NC		 255 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
256 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
257 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
193614f2 258 AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */
a06ea964 259 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
193614f2 260 AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */
a06ea964
NC		 261 AARCH64_OPND_BIT_NUM, /* Immediate. */
262 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
263 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 264 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 265 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
266 each condition flag. */
267
268 AARCH64_OPND_LIMM, /* Logical Immediate. */
269 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
270 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
271 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
272 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
c2c4ff8d
SN		 273 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
274 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
275 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
a06ea964
NC		 276
277 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 278 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 279
280 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
281 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
282 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
283 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
284 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
285
286 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
287 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
288 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
289 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
290 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
291 negative or unaligned and there is
292 no writeback allowed. This operand code
293 is only used to support the programmer-
294 friendly feature of using LDR/STR as the
295 the mnemonic name for LDUR/STUR instructions
296 wherever there is no ambiguity. */
3f06e550 297 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
fb3265b3
SD		 298 AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of
299 16) immediate. */
a06ea964 300 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
fb3265b3
SD		 301 AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of
302 16) immediate. */
a06ea964 303 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
f42f1a1d 304 AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
a06ea964
NC		 305 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
306
307 AARCH64_OPND_SYSREG, /* System register operand. */
308 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
309 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
310 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
311 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
312 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
2ac435d4 313 AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
a06ea964
NC		 314 AARCH64_OPND_BARRIER, /* Barrier operand. */
315 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
316 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 317 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
ff605452 318 AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
f11ad6bc 319
582e12bf 320 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
98907a70
RS		 321 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
322 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
323 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
324 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
325 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
326 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 327 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
328 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
329 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
330 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
c8d59609 331 AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */
4df068de
RS		 332 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
333 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
334 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
335 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
336 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
337 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
338 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
339 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
c469c864 340 AARCH64_OPND_SVE_ADDR_ZX, /* SVE [Zn.<T>{, <Xm>}]. */
4df068de
RS		 341 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
342 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
343 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
344 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
345 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
346 Bit 14 controls S/U choice. */
347 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
348 Bit 22 controls S/U choice. */
349 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
350 Bit 14 controls S/U choice. */
351 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
352 Bit 22 controls S/U choice. */
353 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
354 Bit 14 controls S/U choice. */
355 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
356 Bit 22 controls S/U choice. */
357 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
358 Bit 14 controls S/U choice. */
359 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
360 Bit 22 controls S/U choice. */
361 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
362 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
363 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
364 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
365 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
366 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
367 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 368 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
369 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 370 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
371 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
372 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
373 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
582e12bf
RS		 374 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
375 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
adccc507 376 AARCH64_OPND_SVE_IMM_ROT3, /* SVE cadd 1-bit rotate (90 or 270). */
e950b345
RS		 377 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
378 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
379 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 380 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 381 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 382 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 383 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
384 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
385 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
386 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
387 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
388 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
389 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
390 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 391 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
392 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 393 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
394 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
395 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
396 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
397 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
398 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
399 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
400 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
401 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
402 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
403 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
404 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 405 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
406 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
407 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
408 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 409 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
410 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
411 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
412 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
413 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
582e12bf
RS		 414 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
415 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
116adc27 416 AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */
582e12bf 417 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
f11ad6bc
RS		 418 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
419 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
420 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
421 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
422 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
b83b4b13 423 AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
f42f1a1d 424 AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
a06ea964
NC		 425};
426
427/* Qualifier constrains an operand. It either specifies a variant of an
428 operand type or limits values available to an operand type.
429
430 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
431
432enum aarch64_opnd_qualifier
433{
434 /* Indicating no further qualification on an operand. */
435 AARCH64_OPND_QLF_NIL,
436
437 /* Qualifying an operand which is a general purpose (integer) register;
438 indicating the operand data size or a specific register. */
439 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
440 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
441 AARCH64_OPND_QLF_WSP, /* WSP. */
442 AARCH64_OPND_QLF_SP, /* SP. */
443
444 /* Qualifying an operand which is a floating-point register, a SIMD
445 vector element or a SIMD vector element list; indicating operand data
446 size or the size of each SIMD vector element in the case of a SIMD
447 vector element list.
448 These qualifiers are also used to qualify an address operand to
449 indicate the size of data element a load/store instruction is
450 accessing.
451 They are also used for the immediate shift operand in e.g. SSHR. Such
452 a use is only for the ease of operand encoding/decoding and qualifier
453 sequence matching; such a use should not be applied widely; use the value
454 constraint qualifiers for immediate operands wherever possible. */
455 AARCH64_OPND_QLF_S_B,
456 AARCH64_OPND_QLF_S_H,
457 AARCH64_OPND_QLF_S_S,
458 AARCH64_OPND_QLF_S_D,
459 AARCH64_OPND_QLF_S_Q,
00c2093f
TC		 460 /* This type qualifier has a special meaning in that it means that 4 x 1 byte
461 are selected by the instruction. Other than that it has no difference
462 with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical
463 reasons and is an exception from normal AArch64 disassembly scheme. */
464 AARCH64_OPND_QLF_S_4B,
a06ea964
NC		 465
466 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
467 register list; indicating register shape.
468 They are also used for the immediate shift operand in e.g. SSHR. Such
469 a use is only for the ease of operand encoding/decoding and qualifier
470 sequence matching; such a use should not be applied widely; use the value
471 constraint qualifiers for immediate operands wherever possible. */
a3b3345a 472 AARCH64_OPND_QLF_V_4B,
a06ea964
NC		 473 AARCH64_OPND_QLF_V_8B,
474 AARCH64_OPND_QLF_V_16B,
3067d3b9 475 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 476 AARCH64_OPND_QLF_V_4H,
477 AARCH64_OPND_QLF_V_8H,
478 AARCH64_OPND_QLF_V_2S,
479 AARCH64_OPND_QLF_V_4S,
480 AARCH64_OPND_QLF_V_1D,
481 AARCH64_OPND_QLF_V_2D,
482 AARCH64_OPND_QLF_V_1Q,
483
d50c751e
RS		 484 AARCH64_OPND_QLF_P_Z,
485 AARCH64_OPND_QLF_P_M,
fb3265b3
SD		 486
487 /* Used in scaled signed immediate that are scaled by a Tag granule
488 like in stg, st2g, etc. */
489 AARCH64_OPND_QLF_imm_tag,
d50c751e 490
a06ea964 491 /* Constraint on value. */
a6a51754 492 AARCH64_OPND_QLF_CR, /* CRn, CRm. */
a06ea964
NC		 493 AARCH64_OPND_QLF_imm_0_7,
494 AARCH64_OPND_QLF_imm_0_15,
495 AARCH64_OPND_QLF_imm_0_31,
496 AARCH64_OPND_QLF_imm_0_63,
497 AARCH64_OPND_QLF_imm_1_32,
498 AARCH64_OPND_QLF_imm_1_64,
499
500 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
501 or shift-ones. */
502 AARCH64_OPND_QLF_LSL,
503 AARCH64_OPND_QLF_MSL,
504
505 /* Special qualifier helping retrieve qualifier information during the
506 decoding time (currently not in use). */
507 AARCH64_OPND_QLF_RETRIEVE,
508};
509\f
510/* Instruction class. */
511
512enum aarch64_insn_class
513{
514 addsub_carry,
515 addsub_ext,
516 addsub_imm,
517 addsub_shift,
518 asimdall,
519 asimddiff,
520 asimdelem,
521 asimdext,
522 asimdimm,
523 asimdins,
524 asimdmisc,
525 asimdperm,
526 asimdsame,
527 asimdshf,
528 asimdtbl,
529 asisddiff,
530 asisdelem,
531 asisdlse,
532 asisdlsep,
533 asisdlso,
534 asisdlsop,
535 asisdmisc,
536 asisdone,
537 asisdpair,
538 asisdsame,
539 asisdshf,
540 bitfield,
541 branch_imm,
542 branch_reg,
543 compbranch,
544 condbranch,
545 condcmp_imm,
546 condcmp_reg,
547 condsel,
548 cryptoaes,
549 cryptosha2,
550 cryptosha3,
551 dp_1src,
552 dp_2src,
553 dp_3src,
554 exception,
555 extract,
556 float2fix,
557 float2int,
558 floatccmp,
559 floatcmp,
560 floatdp1,
561 floatdp2,
562 floatdp3,
563 floatimm,
564 floatsel,
565 ldst_immpost,
566 ldst_immpre,
567 ldst_imm9, /* immpost or immpre */
3f06e550 568 ldst_imm10, /* LDRAA/LDRAB */
a06ea964
NC		 569 ldst_pos,
570 ldst_regoff,
571 ldst_unpriv,
572 ldst_unscaled,
573 ldstexcl,
574 ldstnapair_offs,
575 ldstpair_off,
576 ldstpair_indexed,
577 loadlit,
578 log_imm,
579 log_shift,
ee804238 580 lse_atomic,
a06ea964
NC		 581 movewide,
582 pcreladdr,
583 ic_system,
116b6019
RS		 584 sve_cpy,
585 sve_index,
586 sve_limm,
587 sve_misc,
588 sve_movprfx,
589 sve_pred_zm,
590 sve_shift_pred,
591 sve_shift_unpred,
592 sve_size_bhs,
593 sve_size_bhsd,
594 sve_size_hsd,
3bd82c86 595 sve_size_hsd2,
116b6019 596 sve_size_sd,
3c705960 597 sve_size_bh,
0a57e14f 598 sve_size_sd2,
cd50a87a 599 sve_size_013,
a06ea964 600 testbranch,
f42f1a1d
TC		 601 cryptosm3,
602 cryptosm4,
65a55fbb 603 dotproduct,
a06ea964
NC		 604};
605
606/* Opcode enumerators. */
607
608enum aarch64_op
609{
610 OP_NIL,
611 OP_STRB_POS,
612 OP_LDRB_POS,
613 OP_LDRSB_POS,
614 OP_STRH_POS,
615 OP_LDRH_POS,
616 OP_LDRSH_POS,
617 OP_STR_POS,
618 OP_LDR_POS,
619 OP_STRF_POS,
620 OP_LDRF_POS,
621 OP_LDRSW_POS,
622 OP_PRFM_POS,
623
624 OP_STURB,
625 OP_LDURB,
626 OP_LDURSB,
627 OP_STURH,
628 OP_LDURH,
629 OP_LDURSH,
630 OP_STUR,
631 OP_LDUR,
632 OP_STURV,
633 OP_LDURV,
634 OP_LDURSW,
635 OP_PRFUM,
636
637 OP_LDR_LIT,
638 OP_LDRV_LIT,
639 OP_LDRSW_LIT,
640 OP_PRFM_LIT,
641
642 OP_ADD,
643 OP_B,
644 OP_BL,
645
646 OP_MOVN,
647 OP_MOVZ,
648 OP_MOVK,
649
650 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
651 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
652 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
653
654 OP_MOV_V, /* MOV alias for moving vector register. */
655
656 OP_ASR_IMM,
657 OP_LSR_IMM,
658 OP_LSL_IMM,
659
660 OP_BIC,
661
662 OP_UBFX,
663 OP_BFXIL,
664 OP_SBFX,
665 OP_SBFIZ,
666 OP_BFI,
d685192a 667 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 668 OP_UBFIZ,
669 OP_UXTB,
670 OP_UXTH,
671 OP_UXTW,
672
a06ea964
NC		 673 OP_CINC,
674 OP_CINV,
675 OP_CNEG,
676 OP_CSET,
677 OP_CSETM,
678
679 OP_FCVT,
680 OP_FCVTN,
681 OP_FCVTN2,
682 OP_FCVTL,
683 OP_FCVTL2,
684 OP_FCVTXN_S, /* Scalar version. */
685
686 OP_ROR_IMM,
687
e30181a5
YZ		 688 OP_SXTL,
689 OP_SXTL2,
690 OP_UXTL,
691 OP_UXTL2,
692
c0890d26
RS		 693 OP_MOV_P_P,
694 OP_MOV_Z_P_Z,
695 OP_MOV_Z_V,
696 OP_MOV_Z_Z,
697 OP_MOV_Z_Zi,
698 OP_MOVM_P_P_P,
699 OP_MOVS_P_P,
700 OP_MOVZS_P_P_P,
701 OP_MOVZ_P_P_P,
702 OP_NOTS_P_P_P_Z,
703 OP_NOT_P_P_P_Z,
704
c2c4ff8d
SN		 705 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
706
a06ea964
NC		 707 OP_TOTAL_NUM, /* Pseudo. */
708};
709
1d482394
TC		 710/* Error types. */
711enum err_type
712{
713 ERR_OK,
714 ERR_UND,
715 ERR_UNP,
716 ERR_NYI,
a68f4cd2 717 ERR_VFI,
1d482394
TC		 718 ERR_NR_ENTRIES
719};
720
a06ea964
NC		 721/* Maximum number of operands an instruction can have. */
722#define AARCH64_MAX_OPND_NUM 6
723/* Maximum number of qualifier sequences an instruction can have. */
724#define AARCH64_MAX_QLF_SEQ_NUM 10
725/* Operand qualifier typedef; optimized for the size. */
726typedef unsigned char aarch64_opnd_qualifier_t;
727/* Operand qualifier sequence typedef. */
728typedef aarch64_opnd_qualifier_t \
729 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
730
731/* FIXME: improve the efficiency. */
732static inline bfd_boolean
733empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
734{
735 int i;
736 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
737 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
738 return FALSE;
739 return TRUE;
740}
741
7e84b55d
TC		 742/* Forward declare error reporting type. */
743typedef struct aarch64_operand_error aarch64_operand_error;
744/* Forward declare instruction sequence type. */
745typedef struct aarch64_instr_sequence aarch64_instr_sequence;
746/* Forward declare instruction definition. */
747typedef struct aarch64_inst aarch64_inst;
748
a06ea964
NC		 749/* This structure holds information for a particular opcode. */
750
751struct aarch64_opcode
752{
753 /* The name of the mnemonic. */
754 const char *name;
755
756 /* The opcode itself. Those bits which will be filled in with
757 operands are zeroes. */
758 aarch64_insn opcode;
759
760 /* The opcode mask. This is used by the disassembler. This is a
761 mask containing ones indicating those bits which must match the
762 opcode field, and zeroes indicating those bits which need not
763 match (and are presumably filled in by operands). */
764 aarch64_insn mask;
765
766 /* Instruction class. */
767 enum aarch64_insn_class iclass;
768
769 /* Enumerator identifier. */
770 enum aarch64_op op;
771
772 /* Which architecture variant provides this instruction. */
773 const aarch64_feature_set *avariant;
774
775 /* An array of operand codes. Each code is an index into the
776 operand table. They appear in the order which the operands must
777 appear in assembly code, and are terminated by a zero. */
778 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
779
780 /* A list of operand qualifier code sequence. Each operand qualifier
781 code qualifies the corresponding operand code. Each operand
782 qualifier sequence specifies a valid opcode variant and related
783 constraint on operands. */
784 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
785
786 /* Flags providing information about this instruction */
eae424ae
TC		 787 uint64_t flags;
788
789 /* Extra constraints on the instruction that the verifier checks. */
790 uint32_t constraints;
4bd13cde 791
0c608d6b
RS		 792 /* If nonzero, this operand and operand 0 are both registers and
793 are required to have the same register number. */
794 unsigned char tied_operand;
795
4bd13cde 796 /* If non-NULL, a function to verify that a given instruction is valid. */
755b748f
TC		 797 enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
798 bfd_vma, bfd_boolean, aarch64_operand_error *,
799 struct aarch64_instr_sequence *);
a06ea964
NC		 800};
801
802typedef struct aarch64_opcode aarch64_opcode;
803
804/* Table describing all the AArch64 opcodes. */
805extern aarch64_opcode aarch64_opcode_table[];
806
807/* Opcode flags. */
808#define F_ALIAS (1 << 0)
809#define F_HAS_ALIAS (1 << 1)
810/* Disassembly preference priority 1-3 (the larger the higher). If nothing
811 is specified, it is the priority 0 by default, i.e. the lowest priority. */
812#define F_P1 (1 << 2)
813#define F_P2 (2 << 2)
814#define F_P3 (3 << 2)
815/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
816#define F_COND (1 << 4)
817/* Instruction has the field of 'sf'. */
818#define F_SF (1 << 5)
819/* Instruction has the field of 'size:Q'. */
820#define F_SIZEQ (1 << 6)
821/* Floating-point instruction has the field of 'type'. */
822#define F_FPTYPE (1 << 7)
823/* AdvSIMD scalar instruction has the field of 'size'. */
824#define F_SSIZE (1 << 8)
825/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
826#define F_T (1 << 9)
827/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
828#define F_GPRSIZE_IN_Q (1 << 10)
829/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
830#define F_LDS_SIZE (1 << 11)
831/* Optional operand; assume maximum of 1 operand can be optional. */
832#define F_OPD0_OPT (1 << 12)
833#define F_OPD1_OPT (2 << 12)
834#define F_OPD2_OPT (3 << 12)
835#define F_OPD3_OPT (4 << 12)
836#define F_OPD4_OPT (5 << 12)
837/* Default value for the optional operand when omitted from the assembly. */
838#define F_DEFAULT(X) (((X) & 0x1f) << 15)
839/* Instruction that is an alias of another instruction needs to be
840 encoded/decoded by converting it to/from the real form, followed by
841 the encoding/decoding according to the rules of the real opcode.
842 This compares to the direct coding using the alias's information.
843 N.B. this flag requires F_ALIAS to be used together. */
844#define F_CONV (1 << 20)
845/* Use together with F_ALIAS to indicate an alias opcode is a programmer
846 friendly pseudo instruction available only in the assembly code (thus will
847 not show up in the disassembly). */
848#define F_PSEUDO (1 << 21)
849/* Instruction has miscellaneous encoding/decoding rules. */
850#define F_MISC (1 << 22)
851/* Instruction has the field of 'N'; used in conjunction with F_SF. */
852#define F_N (1 << 23)
853/* Opcode dependent field. */
854#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 855/* Instruction has the field of 'sz'. */
856#define F_LSE_SZ (1 << 27)
4989adac
RS		 857/* Require an exact qualifier match, even for NIL qualifiers. */
858#define F_STRICT (1ULL << 28)
f9830ec1
TC		 859/* This system instruction is used to read system registers. */
860#define F_SYS_READ (1ULL << 29)
861/* This system instruction is used to write system registers. */
862#define F_SYS_WRITE (1ULL << 30)
eae424ae
TC		 863/* This instruction has an extra constraint on it that imposes a requirement on
864 subsequent instructions. */
865#define F_SCAN (1ULL << 31)
866/* Next bit is 32. */
867
868/* Instruction constraints. */
869/* This instruction has a predication constraint on the instruction at PC+4. */
870#define C_SCAN_MOVPRFX (1U << 0)
871/* This instruction's operation width is determined by the operand with the
872 largest element size. */
873#define C_MAX_ELEM (1U << 1)
874/* Next bit is 2. */
a06ea964
NC		 875
876static inline bfd_boolean
877alias_opcode_p (const aarch64_opcode *opcode)
878{
879 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
880}
881
882static inline bfd_boolean
883opcode_has_alias (const aarch64_opcode *opcode)
884{
885 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
886}
887
888/* Priority for disassembling preference. */
889static inline int
890opcode_priority (const aarch64_opcode *opcode)
891{
892 return (opcode->flags >> 2) & 0x3;
893}
894
895static inline bfd_boolean
896pseudo_opcode_p (const aarch64_opcode *opcode)
897{
898 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
899}
900
901static inline bfd_boolean
902optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
903{
904 return (((opcode->flags >> 12) & 0x7) == idx + 1)
905 ? TRUE : FALSE;
906}
907
908static inline aarch64_insn
909get_optional_operand_default_value (const aarch64_opcode *opcode)
910{
911 return (opcode->flags >> 15) & 0x1f;
912}
913
914static inline unsigned int
915get_opcode_dependent_value (const aarch64_opcode *opcode)
916{
917 return (opcode->flags >> 24) & 0x7;
918}
919
920static inline bfd_boolean
921opcode_has_special_coder (const aarch64_opcode *opcode)
922{
ee804238 923 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 924 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
925 : FALSE;
926}
927\f
928struct aarch64_name_value_pair
929{
930 const char * name;
931 aarch64_insn value;
932};
933
934extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964
NC		 935extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
936extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 937extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 938
49eec193
YZ		 939typedef struct
940{
941 const char * name;
942 aarch64_insn value;
943 uint32_t flags;
944} aarch64_sys_reg;
945
946extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 947extern const aarch64_sys_reg aarch64_pstatefields [];
49eec193 948extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
f21cce2c
MW		 949extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
950 const aarch64_sys_reg *);
951extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
952 const aarch64_sys_reg *);
49eec193 953
a06ea964
NC		 954typedef struct
955{
875880c6 956 const char *name;
a06ea964 957 uint32_t value;
ea2deeec 958 uint32_t flags ;
a06ea964
NC		 959} aarch64_sys_ins_reg;
960
ea2deeec 961extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6
MW		 962extern bfd_boolean
963aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
964 const aarch64_sys_ins_reg *);
ea2deeec 965
a06ea964
NC		 966extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
967extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
968extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
969extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
2ac435d4 970extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
a06ea964
NC		 971
972/* Shift/extending operator kinds.
973 N.B. order is important; keep aarch64_operand_modifiers synced. */
974enum aarch64_modifier_kind
975{
976 AARCH64_MOD_NONE,
977 AARCH64_MOD_MSL,
978 AARCH64_MOD_ROR,
979 AARCH64_MOD_ASR,
980 AARCH64_MOD_LSR,
981 AARCH64_MOD_LSL,
982 AARCH64_MOD_UXTB,
983 AARCH64_MOD_UXTH,
984 AARCH64_MOD_UXTW,
985 AARCH64_MOD_UXTX,
986 AARCH64_MOD_SXTB,
987 AARCH64_MOD_SXTH,
988 AARCH64_MOD_SXTW,
989 AARCH64_MOD_SXTX,
2442d846 990 AARCH64_MOD_MUL,
98907a70 991 AARCH64_MOD_MUL_VL,
a06ea964
NC		 992};
993
994bfd_boolean
995aarch64_extend_operator_p (enum aarch64_modifier_kind);
996
997enum aarch64_modifier_kind
998aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
999/* Condition. */
1000
1001typedef struct
1002{
1003 /* A list of names with the first one as the disassembly preference;
1004 terminated by NULL if fewer than 3. */
bb7eff52 1005 const char *names[4];
a06ea964
NC		 1006 aarch64_insn value;
1007} aarch64_cond;
1008
1009extern const aarch64_cond aarch64_conds[16];
1010
1011const aarch64_cond* get_cond_from_value (aarch64_insn value);
1012const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
1013\f
1014/* Structure representing an operand. */
1015
1016struct aarch64_opnd_info
1017{
1018 enum aarch64_opnd type;
1019 aarch64_opnd_qualifier_t qualifier;
1020 int idx;
1021
1022 union
1023 {
1024 struct
1025 {
1026 unsigned regno;
1027 } reg;
1028 struct
1029 {
dab26bf4
RS		 1030 unsigned int regno;
1031 int64_t index;
a06ea964
NC		 1032 } reglane;
1033 /* e.g. LVn. */
1034 struct
1035 {
1036 unsigned first_regno : 5;
1037 unsigned num_regs : 3;
1038 /* 1 if it is a list of reg element. */
1039 unsigned has_index : 1;
1040 /* Lane index; valid only when has_index is 1. */
dab26bf4 1041 int64_t index;
a06ea964
NC		 1042 } reglist;
1043 /* e.g. immediate or pc relative address offset. */
1044 struct
1045 {
1046 int64_t value;
1047 unsigned is_fp : 1;
1048 } imm;
1049 /* e.g. address in STR (register offset). */
1050 struct
1051 {
1052 unsigned base_regno;
1053 struct
1054 {
1055 union
1056 {
1057 int imm;
1058 unsigned regno;
1059 };
1060 unsigned is_reg;
1061 } offset;
1062 unsigned pcrel : 1; /* PC-relative. */
1063 unsigned writeback : 1;
1064 unsigned preind : 1; /* Pre-indexed. */
1065 unsigned postind : 1; /* Post-indexed. */
1066 } addr;
561a72d4
TC		 1067
1068 struct
1069 {
1070 /* The encoding of the system register. */
1071 aarch64_insn value;
1072
1073 /* The system register flags. */
1074 uint32_t flags;
1075 } sysreg;
1076
a06ea964 1077 const aarch64_cond *cond;
a06ea964
NC		 1078 /* The encoding of the PSTATE field. */
1079 aarch64_insn pstatefield;
1080 const aarch64_sys_ins_reg *sysins_op;
1081 const struct aarch64_name_value_pair *barrier;
9ed608f9 1082 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 1083 const struct aarch64_name_value_pair *prfop;
1084 };
1085
1086 /* Operand shifter; in use when the operand is a register offset address,
1087 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
1088 struct
1089 {
1090 enum aarch64_modifier_kind kind;
a06ea964
NC		 1091 unsigned operator_present: 1; /* Only valid during encoding. */
1092 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
1093 unsigned amount_present: 1;
2442d846 1094 int64_t amount;
a06ea964
NC		 1095 } shifter;
1096
1097 unsigned skip:1; /* Operand is not completed if there is a fixup needed
1098 to be done on it. In some (but not all) of these
1099 cases, we need to tell libopcodes to skip the
1100 constraint checking and the encoding for this
1101 operand, so that the libopcodes can pick up the
1102 right opcode before the operand is fixed-up. This
1103 flag should only be used during the
1104 assembling/encoding. */
1105 unsigned present:1; /* Whether this operand is present in the assembly
1106 line; not used during the disassembly. */
1107};
1108
1109typedef struct aarch64_opnd_info aarch64_opnd_info;
1110
1111/* Structure representing an instruction.
1112
1113 It is used during both the assembling and disassembling. The assembler
1114 fills an aarch64_inst after a successful parsing and then passes it to the
1115 encoding routine to do the encoding. During the disassembling, the
1116 disassembler calls the decoding routine to decode a binary instruction; on a
1117 successful return, such a structure will be filled with information of the
1118 instruction; then the disassembler uses the information to print out the
1119 instruction. */
1120
1121struct aarch64_inst
1122{
1123 /* The value of the binary instruction. */
1124 aarch64_insn value;
1125
1126 /* Corresponding opcode entry. */
1127 const aarch64_opcode *opcode;
1128
1129 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
1130 const aarch64_cond *cond;
1131
1132 /* Operands information. */
1133 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1134};
1135
ff605452
SD		 1136/* Defining the HINT #imm values for the aarch64_hint_options. */
1137#define HINT_OPD_CSYNC 0x11
1138#define HINT_OPD_C 0x22
1139#define HINT_OPD_J 0x24
1140#define HINT_OPD_JC 0x26
1141#define HINT_OPD_NULL 0x00
1142
a06ea964
NC		 1143\f
1144/* Diagnosis related declaration and interface. */
1145
1146/* Operand error kind enumerators.
1147
1148 AARCH64_OPDE_RECOVERABLE
1149 Less severe error found during the parsing, very possibly because that
1150 GAS has picked up a wrong instruction template for the parsing.
1151
1152 AARCH64_OPDE_SYNTAX_ERROR
1153 General syntax error; it can be either a user error, or simply because
1154 that GAS is trying a wrong instruction template.
1155
1156 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1157 Definitely a user syntax error.
1158
1159 AARCH64_OPDE_INVALID_VARIANT
1160 No syntax error, but the operands are not a valid combination, e.g.
1161 FMOV D0,S0
1162
0c608d6b
RS		 1163 AARCH64_OPDE_UNTIED_OPERAND
1164 The asm failed to use the same register for a destination operand
1165 and a tied source operand.
1166
a06ea964
NC		 1167 AARCH64_OPDE_OUT_OF_RANGE
1168 Error about some immediate value out of a valid range.
1169
1170 AARCH64_OPDE_UNALIGNED
1171 Error about some immediate value not properly aligned (i.e. not being a
1172 multiple times of a certain value).
1173
1174 AARCH64_OPDE_REG_LIST
1175 Error about the register list operand having unexpected number of
1176 registers.
1177
1178 AARCH64_OPDE_OTHER_ERROR
1179 Error of the highest severity and used for any severe issue that does not
1180 fall into any of the above categories.
1181
1182 The enumerators are only interesting to GAS. They are declared here (in
1183 libopcodes) because that some errors are detected (and then notified to GAS)
1184 by libopcodes (rather than by GAS solely).
1185
1186 The first three errors are only deteced by GAS while the
1187 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1188 only libopcodes has the information about the valid variants of each
1189 instruction.
1190
1191 The enumerators have an increasing severity. This is helpful when there are
1192 multiple instruction templates available for a given mnemonic name (e.g.
1193 FMOV); this mechanism will help choose the most suitable template from which
1194 the generated diagnostics can most closely describe the issues, if any. */
1195
1196enum aarch64_operand_error_kind
1197{
1198 AARCH64_OPDE_NIL,
1199 AARCH64_OPDE_RECOVERABLE,
1200 AARCH64_OPDE_SYNTAX_ERROR,
1201 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1202 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1203 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1204 AARCH64_OPDE_OUT_OF_RANGE,
1205 AARCH64_OPDE_UNALIGNED,
1206 AARCH64_OPDE_REG_LIST,
1207 AARCH64_OPDE_OTHER_ERROR
1208};
1209
1210/* N.B. GAS assumes that this structure work well with shallow copy. */
1211struct aarch64_operand_error
1212{
1213 enum aarch64_operand_error_kind kind;
1214 int index;
1215 const char *error;
1216 int data[3]; /* Some data for extra information. */
7d02540a 1217 bfd_boolean non_fatal;
a06ea964
NC		 1218};
1219
7e84b55d
TC		 1220/* AArch64 sequence structure used to track instructions with F_SCAN
1221 dependencies for both assembler and disassembler. */
1222struct aarch64_instr_sequence
1223{
1224 /* The instruction that caused this sequence to be opened. */
1225 aarch64_inst *instr;
1226 /* The number of instructions the above instruction allows to be kept in the
1227 sequence before an automatic close is done. */
1228 int num_insns;
1229 /* The instructions currently added to the sequence. */
1230 aarch64_inst **current_insns;
1231 /* The number of instructions already in the sequence. */
1232 int next_insn;
1233};
a06ea964
NC		 1234
1235/* Encoding entrypoint. */
1236
1237extern int
1238aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1239 aarch64_insn *, aarch64_opnd_qualifier_t *,
7e84b55d 1240 aarch64_operand_error *, aarch64_instr_sequence *);
a06ea964
NC		 1241
1242extern const aarch64_opcode *
1243aarch64_replace_opcode (struct aarch64_inst *,
1244 const aarch64_opcode *);
1245
1246/* Given the opcode enumerator OP, return the pointer to the corresponding
1247 opcode entry. */
1248
1249extern const aarch64_opcode *
1250aarch64_get_opcode (enum aarch64_op);
1251
1252/* Generate the string representation of an operand. */
1253extern void
1254aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
7d02540a
TC		 1255 const aarch64_opnd_info *, int, int *, bfd_vma *,
1256 char **);
a06ea964
NC		 1257
1258/* Miscellaneous interface. */
1259
1260extern int
1261aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1262
1263extern aarch64_opnd_qualifier_t
1264aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1265 const aarch64_opnd_qualifier_t, int);
1266
a68f4cd2
TC		 1267extern bfd_boolean
1268aarch64_is_destructive_by_operands (const aarch64_opcode *);
1269
a06ea964
NC		 1270extern int
1271aarch64_num_of_operands (const aarch64_opcode *);
1272
1273extern int
1274aarch64_stack_pointer_p (const aarch64_opnd_info *);
1275
e141d84e
YQ		 1276extern int
1277aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1278
1d482394 1279extern enum err_type
561a72d4 1280aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
a68f4cd2
TC		 1281 aarch64_operand_error *);
1282
1283extern void
1284init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
36f4aab1 1285
a06ea964
NC		 1286/* Given an operand qualifier, return the expected data element size
1287 of a qualified operand. */
1288extern unsigned char
1289aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1290
1291extern enum aarch64_operand_class
1292aarch64_get_operand_class (enum aarch64_opnd);
1293
1294extern const char *
1295aarch64_get_operand_name (enum aarch64_opnd);
1296
1297extern const char *
1298aarch64_get_operand_desc (enum aarch64_opnd);
1299
e950b345
RS		 1300extern bfd_boolean
1301aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1302
a06ea964
NC		 1303#ifdef DEBUG_AARCH64
1304extern int debug_dump;
1305
1306extern void
1307aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1308
1309#define DEBUG_TRACE(M, ...) \
1310 { \
1311 if (debug_dump) \
1312 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1313 }
1314
1315#define DEBUG_TRACE_IF(C, M, ...) \
1316 { \
1317 if (debug_dump && (C)) \
1318 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1319 }
1320#else /* !DEBUG_AARCH64 */
1321#define DEBUG_TRACE(M, ...) ;
1322#define DEBUG_TRACE_IF(C, M, ...) ;
1323#endif /* DEBUG_AARCH64 */
1324
245d2e3f
RS		 1325extern const char *const aarch64_sve_pattern_array[32];
1326extern const char *const aarch64_sve_prfop_array[16];
1327
d3e12b29
YQ		 1328#ifdef __cplusplus
1329}
1330#endif
1331
a06ea964 1332#endif /* OPCODE_AARCH64_H */
GDB Binutils - Deliverables
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