[deliverable/binutils-gdb.git] / include / opcode / arc.h

/* Opcode table for the ARC.
   Copyright (C) 1994-2016 Free Software Foundation, Inc.

   Contributed by Claudiu Zissulescu (claziss@synopsys.com)

   This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   the GNU Binutils.

   GAS/GDB is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   GAS/GDB is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS or GDB; see the file COPYING3.  If not, write to
   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

#ifndef OPCODE_ARC_H
#define OPCODE_ARC_H

#ifndef MAX_INSN_ARGS
#define MAX_INSN_ARGS	     6
#endif

#ifndef MAX_INSN_FLGS
#define MAX_INSN_FLGS	     3
#endif

/* Instruction Class.  */
typedef enum
  {
    ARITH,
    AUXREG,
    BRANCH,
    CONTROL,
    DSP,
    FLOAT,
    INVALID,
    JUMP,
    KERNEL,
    LOGICAL,
    MEMORY,
  } insn_class_t;

/* Instruction Subclass.  */
typedef enum
  {
    NONE,
    CVT,
    BTSCN,
    CD1,
    CD2,
    DIV,
    DP,
    MPY1E,
    MPY6E,
    MPY7E,
    MPY8E,
    MPY9E,
    SHFT1,
    SHFT2,
    SWAP,
    SP
  } insn_subclass_t;

/* Flags class.  */
typedef enum
  {
    FNONE,
    CND,  /* Conditional flags.  */
    WBM,  /* Write-back modes.  */
    FLG,  /* F Flag.  */
    SBP,  /* Static branch prediction.  */
    DLY,  /* Delay slot.  */
    DIF,  /* Bypass caches.  */
    SGX,  /* Sign extend modes.  */
    SZM   /* Data size modes.  */
  } flag_class_t;

/* The opcode table is an array of struct arc_opcode.  */
struct arc_opcode
{
  /* The opcode name.  */
  const char *name;

  /* The opcode itself.  Those bits which will be filled in with
     operands are zeroes.  */
  unsigned opcode;

  /* The opcode mask.  This is used by the disassembler.  This is a
     mask containing ones indicating those bits which must match the
     opcode field, and zeroes indicating those bits which need not
     match (and are presumably filled in by operands).  */
  unsigned mask;

  /* One bit flags for the opcode.  These are primarily used to
     indicate specific processors and environments support the
     instructions.  The defined values are listed below.  */
  unsigned cpu;

  /* The instruction class.  This is used by gdb.  */
  insn_class_t class;

  /* The instruction subclass.  */
  insn_subclass_t subclass;

  /* An array of operand codes.  Each code is an index into the
     operand table.  They appear in the order which the operands must
     appear in assembly code, and are terminated by a zero.  */
  unsigned char operands[MAX_INSN_ARGS + 1];

  /* An array of flag codes.  Each code is an index into the flag
     table.  They appear in the order which the flags must appear in
     assembly code, and are terminated by a zero.  */
  unsigned char flags[MAX_INSN_FLGS + 1];
};

/* The table itself is sorted by major opcode number, and is otherwise
   in the order in which the disassembler should consider
   instructions.  */
extern const struct arc_opcode arc_opcodes[];
extern const unsigned arc_num_opcodes;

/* CPU Availability.  */
#define ARC_OPCODE_ARC600   0x0001  /* ARC 600 specific insns.  */
#define ARC_OPCODE_ARC700   0x0002  /* ARC 700 specific insns.  */
#define ARC_OPCODE_ARCv2EM  0x0004  /* ARCv2 EM specific insns.  */
#define ARC_OPCODE_ARCv2HS  0x0008  /* ARCv2 HS specific insns.  */

/* CPU extensions.  */
#define ARC_EA       0x0001
#define ARC_CD       0x0001    /* Mutual exclusive with EA.  */
#define ARC_LLOCK    0x0002
#define ARC_ATOMIC   0x0002    /* Mutual exclusive with LLOCK.  */
#define ARC_MPY      0x0004
#define ARC_MULT     0x0004

/* Floating point support.  */
#define ARC_DPFP     0x0010
#define ARC_SPFP     0x0020
#define ARC_FPU      0x0030

/* NORM & SWAP.  */
#define ARC_SWAP     0x0100
#define ARC_NORM     0x0200
#define ARC_BSCAN    0x0200

/* A7 specific.  */
#define ARC_UIX      0x1000
#define ARC_TSTAMP   0x1000

/* A6 specific.  */
#define ARC_VBFDW    0x1000
#define ARC_BARREL   0x1000
#define ARC_DSPA     0x1000

/* EM specific.  */
#define ARC_SHIFT    0x1000

/* V2 specific.  */
#define ARC_INTR     0x1000
#define ARC_DIV      0x1000

/* V1 specific.  */
#define ARC_XMAC     0x1000
#define ARC_CRC      0x1000

/* Base architecture -- all cpus.  */
#define ARC_OPCODE_BASE				\
  (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700	\
   | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)

/* A macro to check for short instructions.  */
#define ARC_SHORT(mask)				\
  (((mask) & 0xFFFF0000) ? 0 : 1)

/* The operands table is an array of struct arc_operand.  */
struct arc_operand
{
  /* The number of bits in the operand.  */
  unsigned int bits;

  /* How far the operand is left shifted in the instruction.  */
  unsigned int shift;

  /* The default relocation type for this operand.  */
  signed int default_reloc;

  /* One bit syntax flags.  */
  unsigned int flags;

  /* Insertion function.  This is used by the assembler.  To insert an
     operand value into an instruction, check this field.

     If it is NULL, execute
	 i |= (op & ((1 << o->bits) - 1)) << o->shift;
     (i is the instruction which we are filling in, o is a pointer to
     this structure, and op is the opcode value; this assumes twos
     complement arithmetic).

     If this field is not NULL, then simply call it with the
     instruction and the operand value.	 It will return the new value
     of the instruction.  If the ERRMSG argument is not NULL, then if
     the operand value is illegal, *ERRMSG will be set to a warning
     string (the operand will be inserted in any case).	 If the
     operand value is legal, *ERRMSG will be unchanged (most operands
     can accept any value).  */
  unsigned (*insert) (unsigned instruction, int op, const char **errmsg);

  /* Extraction function.  This is used by the disassembler.  To
     extract this operand type from an instruction, check this field.

     If it is NULL, compute
	 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
	 if ((o->flags & ARC_OPERAND_SIGNED) != 0
	     && (op & (1 << (o->bits - 1))) != 0)
	   op -= 1 << o->bits;
     (i is the instruction, o is a pointer to this structure, and op
     is the result; this assumes twos complement arithmetic).

     If this field is not NULL, then simply call it with the
     instruction value.	 It will return the value of the operand.  If
     the INVALID argument is not NULL, *INVALID will be set to
     TRUE if this operand type can not actually be extracted from
     this operand (i.e., the instruction does not match).  If the
     operand is valid, *INVALID will not be changed.  */
  int (*extract) (unsigned instruction, bfd_boolean *invalid);
};

/* Elements in the table are retrieved by indexing with values from
   the operands field of the arc_opcodes table.  */
extern const struct arc_operand arc_operands[];
extern const unsigned arc_num_operands;
extern const unsigned arc_Toperand;
extern const unsigned arc_NToperand;

/* Values defined for the flags field of a struct arc_operand.  */

/* This operand does not actually exist in the assembler input.  This
   is used to support extended mnemonics, for which two operands fields
   are identical.  The assembler should call the insert function with
   any op value.  The disassembler should call the extract function,
   ignore the return value, and check the value placed in the invalid
   argument.  */
#define ARC_OPERAND_FAKE	0x0001

/* This operand names an integer register.  */
#define ARC_OPERAND_IR		0x0002

/* This operand takes signed values.  */
#define ARC_OPERAND_SIGNED	0x0004

/* This operand takes unsigned values.  This exists primarily so that
   a flags value of 0 can be treated as end-of-arguments.  */
#define ARC_OPERAND_UNSIGNED	0x0008

/* This operand takes long immediate values.  */
#define ARC_OPERAND_LIMM	0x0010

/* This operand is identical like the previous one.  */
#define ARC_OPERAND_DUPLICATE   0x0020

/* This operand is PC relative.  Used for internal relocs.  */
#define ARC_OPERAND_PCREL       0x0040

/* This operand is truncated.  The truncation is done accordingly to
   operand alignment attribute.  */
#define ARC_OPERAND_TRUNCATE    0x0080

/* This operand is 16bit aligned.  */
#define ARC_OPERAND_ALIGNED16   0x0100

/* This operand is 32bit aligned.  */
#define ARC_OPERAND_ALIGNED32   0x0200

/* This operand can be ignored by matching process if it is not
   present.  */
#define ARC_OPERAND_IGNORE      0x0400

/* Don't check the range when matching.	 */
#define ARC_OPERAND_NCHK	0x0800

/* Mark the braket possition.  */
#define ARC_OPERAND_BRAKET      0x1000

/* Mask for selecting the type for typecheck purposes.  */
#define ARC_OPERAND_TYPECHECK_MASK		\
  (ARC_OPERAND_IR |				\
   ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | 	\
   ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET)

/* The flags structure.  */
struct arc_flag_operand
{
  /* The flag name.  */
  const char *name;

  /* The flag code.  */
  unsigned code;

  /* The number of bits in the operand.  */
  unsigned int bits;

  /* How far the operand is left shifted in the instruction.  */
  unsigned int shift;

  /* Available for disassembler.  */
  unsigned char favail;
};

/* The flag operands table.  */
extern const struct arc_flag_operand arc_flag_operands[];
extern const unsigned arc_num_flag_operands;

/* The flag's class structure.  */
struct arc_flag_class
{
  /* Flag class.  */
  flag_class_t class;

  /* List of valid flags (codes).  */
  unsigned flags[256];
};

extern const struct arc_flag_class arc_flag_classes[];

/* Structure for special cases.  */
struct arc_flag_special
{
  /* Name of special case instruction.  */
  const char *name;

  /* List of flags applicable for special case instruction.  */
  unsigned flags[32];
};

extern const struct arc_flag_special arc_flag_special_cases[];
extern const unsigned arc_num_flag_special;

/* Relocation equivalence structure.  */
struct arc_reloc_equiv_tab
{
  const char * name;	   /* String to lookup.  */
  const char * mnemonic;   /* Extra matching condition.  */
  unsigned     flags[32];  /* Extra matching condition.  */
  signed int   oldreloc;   /* Old relocation.  */
  signed int   newreloc;   /* New relocation.  */
};

extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
extern const unsigned arc_num_equiv_tab;

/* Structure for operand operations for pseudo/alias instructions.  */
struct arc_operand_operation
{
  /* The index for operand from operand array.  */
  unsigned operand_idx;

  /* Defines if it needs the operand inserted by the assembler or
     whether this operand comes from the pseudo instruction's
     operands.  */
  unsigned char needs_insert;

  /* Count we have to add to the operand.  Use negative number to
     subtract from the operand.  Also use this number to add to 0 if
     the operand needs to be inserted (i.e. needs_insert == 1).  */
  int count;

  /* Index of the operand to swap with.  To be done AFTER applying
     inc_count.  */
  unsigned swap_operand_idx;
};

/* Structure for pseudo/alias instructions.  */
struct arc_pseudo_insn
{
  /* Mnemonic for pseudo/alias insn.  */
  const char *mnemonic_p;

  /* Mnemonic for real instruction.  */
  const char *mnemonic_r;

  /* Flag that will have to be added (if any).  */
  const char *flag_r;

  /* Amount of operands.  */
  unsigned operand_cnt;

  /* Array of operand operations.  */
  struct arc_operand_operation operand[6];
};

extern const struct arc_pseudo_insn arc_pseudo_insns[];
extern const unsigned arc_num_pseudo_insn;

/* Structure for AUXILIARY registers.  */
struct arc_aux_reg
{
  /* Register address.  */
  int address;

 /* Register name.  */
  const char *name;

  /* Size of the string.  */
  size_t length;
};

extern const struct arc_aux_reg arc_aux_regs[];
extern const unsigned arc_num_aux_regs;

extern const struct arc_opcode arc_relax_opcodes[];
extern const unsigned arc_num_relax_opcodes;

#endif /* OPCODE_ARC_H */
Commit	Line	Data
252b5132	1	/* Opcode table for the ARC.
6f2750fe	2	Copyright (C) 1994-2016 Free Software Foundation, Inc.
886a2506 NC	3
886a2506 NC	4	Contributed by Claudiu Zissulescu (claziss@synopsys.com)
252b5132	5
0d2bcfaf NC	6	This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
0d2bcfaf NC	7	the GNU Binutils.
252b5132	8
0d2bcfaf NC	9	GAS/GDB is free software; you can redistribute it and/or modify
0d2bcfaf NC	10	it under the terms of the GNU General Public License as published by
e4e42b45	11	the Free Software Foundation; either version 3, or (at your option)
0d2bcfaf	12	any later version.
252b5132	13
0d2bcfaf NC	14	GAS/GDB is distributed in the hope that it will be useful,
0d2bcfaf NC	15	but WITHOUT ANY WARRANTY; without even the implied warranty of
886a2506	16	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0d2bcfaf NC	17	GNU General Public License for more details.
	18
	19	You should have received a copy of the GNU General Public License
e4e42b45	20	along with GAS or GDB; see the file COPYING3. If not, write to
e172dbf8 NC	21	the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
e172dbf8 NC	22	MA 02110-1301, USA. */
252b5132	23
886a2506 NC	24	#ifndef OPCODE_ARC_H
	25	#define OPCODE_ARC_H
	26
4670103e	27	#ifndef MAX_INSN_ARGS
886a2506	28	#define MAX_INSN_ARGS 6
4670103e CZ	29	#endif
	30
	31	#ifndef MAX_INSN_FLGS
886a2506	32	#define MAX_INSN_FLGS 3
4670103e	33	#endif
886a2506 NC	34
	35	/* Instruction Class. */
	36	typedef enum
	37	{
	38	ARITH,
	39	AUXREG,
	40	BRANCH,
	41	CONTROL,
	42	DSP,
	43	FLOAT,
	44	INVALID,
	45	JUMP,
	46	KERNEL,
	47	LOGICAL,
	48	MEMORY,
	49	} insn_class_t;
	50
	51	/* Instruction Subclass. */
	52	typedef enum
	53	{
	54	NONE,
	55	CVT,
	56	BTSCN,
	57	CD1,
	58	CD2,
	59	DIV,
	60	DP,
	61	MPY1E,
	62	MPY6E,
	63	MPY7E,
	64	MPY8E,
	65	MPY9E,
	66	SHFT1,
	67	SHFT2,
	68	SWAP,
	69	SP
	70	} insn_subclass_t;
	71
	72	/* Flags class. */
	73	typedef enum
	74	{
	75	FNONE,
	76	CND, /* Conditional flags. */
	77	WBM, /* Write-back modes. */
	78	FLG, /* F Flag. */
	79	SBP, /* Static branch prediction. */
	80	DLY, /* Delay slot. */
	81	DIF, /* Bypass caches. */
	82	SGX, /* Sign extend modes. */
	83	SZM /* Data size modes. */
	84	} flag_class_t;
	85
	86	/* The opcode table is an array of struct arc_opcode. */
	87	struct arc_opcode
	88	{
	89	/* The opcode name. */
	90	const char *name;
	91
	92	/* The opcode itself. Those bits which will be filled in with
	93	operands are zeroes. */
	94	unsigned opcode;
	95
	96	/* The opcode mask. This is used by the disassembler. This is a
	97	mask containing ones indicating those bits which must match the
98	opcode field, and zeroes indicating those bits which need not
99	match (and are presumably filled in by operands). */
100	unsigned mask;
101
102	/* One bit flags for the opcode. These are primarily used to
103	indicate specific processors and environments support the
104	instructions. The defined values are listed below. */
105	unsigned cpu;
106
107	/* The instruction class. This is used by gdb. */
108	insn_class_t class;
109
110	/* The instruction subclass. */
111	insn_subclass_t subclass;
112
113	/* An array of operand codes. Each code is an index into the
114	operand table. They appear in the order which the operands must
115	appear in assembly code, and are terminated by a zero. */
116	unsigned char operands[MAX_INSN_ARGS + 1];
117
118	/* An array of flag codes. Each code is an index into the flag
119	table. They appear in the order which the flags must appear in
120	assembly code, and are terminated by a zero. */
121	unsigned char flags[MAX_INSN_FLGS + 1];
122	};
252b5132	123
886a2506 NC	124	/* The table itself is sorted by major opcode number, and is otherwise
	125	in the order in which the disassembler should consider
	126	instructions. */
	127	extern const struct arc_opcode arc_opcodes[];
	128	extern const unsigned arc_num_opcodes;
	129
	130	/* CPU Availability. */
	131	#define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
	132	#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
	133	#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
	134	#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
	135
	136	/* CPU extensions. */
	137	#define ARC_EA 0x0001
	138	#define ARC_CD 0x0001 /* Mutual exclusive with EA. */
	139	#define ARC_LLOCK 0x0002
	140	#define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */
	141	#define ARC_MPY 0x0004
	142	#define ARC_MULT 0x0004
	143
	144	/* Floating point support. */
	145	#define ARC_DPFP 0x0010
	146	#define ARC_SPFP 0x0020
	147	#define ARC_FPU 0x0030
	148
	149	/* NORM & SWAP. */
	150	#define ARC_SWAP 0x0100
	151	#define ARC_NORM 0x0200
	152	#define ARC_BSCAN 0x0200
	153
	154	/* A7 specific. */
	155	#define ARC_UIX 0x1000
	156	#define ARC_TSTAMP 0x1000
	157
	158	/* A6 specific. */
	159	#define ARC_VBFDW 0x1000
	160	#define ARC_BARREL 0x1000
	161	#define ARC_DSPA 0x1000
	162
	163	/* EM specific. */
	164	#define ARC_SHIFT 0x1000
	165
	166	/* V2 specific. */
	167	#define ARC_INTR 0x1000
	168	#define ARC_DIV 0x1000
	169
	170	/* V1 specific. */
	171	#define ARC_XMAC 0x1000
	172	#define ARC_CRC 0x1000
	173
	174	/* Base architecture -- all cpus. */
	175	#define ARC_OPCODE_BASE \
	176	(ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \
	177	\| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS)
	178
	179	/* A macro to check for short instructions. */
	180	#define ARC_SHORT(mask) \
	181	(((mask) & 0xFFFF0000) ? 0 : 1)
	182
	183	/* The operands table is an array of struct arc_operand. */
	184	struct arc_operand
	185	{
	186	/* The number of bits in the operand. */
	187	unsigned int bits;
188
189	/* How far the operand is left shifted in the instruction. */
190	unsigned int shift;
191
192	/* The default relocation type for this operand. */
193	signed int default_reloc;
194
195	/* One bit syntax flags. */
196	unsigned int flags;
197
198	/* Insertion function. This is used by the assembler. To insert an
199	operand value into an instruction, check this field.
200
201	If it is NULL, execute
202	i \|= (op & ((1 << o->bits) - 1)) << o->shift;
203	(i is the instruction which we are filling in, o is a pointer to
204	this structure, and op is the opcode value; this assumes twos
205	complement arithmetic).
206
207	If this field is not NULL, then simply call it with the
208	instruction and the operand value. It will return the new value
209	of the instruction. If the ERRMSG argument is not NULL, then if
210	the operand value is illegal, *ERRMSG will be set to a warning
211	string (the operand will be inserted in any case). If the
212	operand value is legal, *ERRMSG will be unchanged (most operands
213	can accept any value). */
214	unsigned (insert) (unsigned instruction, int op, const char *errmsg);
215
216	/* Extraction function. This is used by the disassembler. To
217	extract this operand type from an instruction, check this field.
218
219	If it is NULL, compute
220	op = ((i) >> o->shift) & ((1 << o->bits) - 1);
221	if ((o->flags & ARC_OPERAND_SIGNED) != 0
222	&& (op & (1 << (o->bits - 1))) != 0)
223	op -= 1 << o->bits;
224	(i is the instruction, o is a pointer to this structure, and op
225	is the result; this assumes twos complement arithmetic).
226
227	If this field is not NULL, then simply call it with the
228	instruction value. It will return the value of the operand. If
229	the INVALID argument is not NULL, *INVALID will be set to
230	TRUE if this operand type can not actually be extracted from
231	this operand (i.e., the instruction does not match). If the
232	operand is valid, INVALID will not be changed. /
233	int (extract) (unsigned instruction, bfd_boolean invalid);
234	};
0d2bcfaf	235
886a2506 NC	236	/* Elements in the table are retrieved by indexing with values from
	237	the operands field of the arc_opcodes table. */
	238	extern const struct arc_operand arc_operands[];
	239	extern const unsigned arc_num_operands;
	240	extern const unsigned arc_Toperand;
	241	extern const unsigned arc_NToperand;
252b5132	242
886a2506	243	/* Values defined for the flags field of a struct arc_operand. */
0d2bcfaf	244
886a2506 NC	245	/* This operand does not actually exist in the assembler input. This
	246	is used to support extended mnemonics, for which two operands fields
	247	are identical. The assembler should call the insert function with
	248	any op value. The disassembler should call the extract function,
	249	ignore the return value, and check the value placed in the invalid
	250	argument. */
	251	#define ARC_OPERAND_FAKE 0x0001
252b5132	252
886a2506 NC	253	/* This operand names an integer register. */
886a2506 NC	254	#define ARC_OPERAND_IR 0x0002
0d2bcfaf	255
886a2506 NC	256	/* This operand takes signed values. */
886a2506 NC	257	#define ARC_OPERAND_SIGNED 0x0004
252b5132	258
886a2506 NC	259	/* This operand takes unsigned values. This exists primarily so that
	260	a flags value of 0 can be treated as end-of-arguments. */
	261	#define ARC_OPERAND_UNSIGNED 0x0008
252b5132	262
886a2506 NC	263	/* This operand takes long immediate values. */
886a2506 NC	264	#define ARC_OPERAND_LIMM 0x0010
252b5132	265
886a2506 NC	266	/* This operand is identical like the previous one. */
886a2506 NC	267	#define ARC_OPERAND_DUPLICATE 0x0020
0d2bcfaf	268
886a2506 NC	269	/* This operand is PC relative. Used for internal relocs. */
886a2506 NC	270	#define ARC_OPERAND_PCREL 0x0040
0d2bcfaf	271
886a2506 NC	272	/* This operand is truncated. The truncation is done accordingly to
	273	operand alignment attribute. */
	274	#define ARC_OPERAND_TRUNCATE 0x0080
0d2bcfaf	275
886a2506 NC	276	/* This operand is 16bit aligned. */
886a2506 NC	277	#define ARC_OPERAND_ALIGNED16 0x0100
0d2bcfaf	278
886a2506 NC	279	/* This operand is 32bit aligned. */
886a2506 NC	280	#define ARC_OPERAND_ALIGNED32 0x0200
0d2bcfaf	281
886a2506 NC	282	/* This operand can be ignored by matching process if it is not
	283	present. */
	284	#define ARC_OPERAND_IGNORE 0x0400
0d2bcfaf	285
886a2506 NC	286	/* Don't check the range when matching. */
886a2506 NC	287	#define ARC_OPERAND_NCHK 0x0800
0d2bcfaf	288
886a2506 NC	289	/* Mark the braket possition. */
886a2506 NC	290	#define ARC_OPERAND_BRAKET 0x1000
252b5132	291
886a2506 NC	292	/* Mask for selecting the type for typecheck purposes. */
	293	#define ARC_OPERAND_TYPECHECK_MASK \
	294	(ARC_OPERAND_IR \| \
	295	ARC_OPERAND_LIMM \| ARC_OPERAND_SIGNED \| \
	296	ARC_OPERAND_UNSIGNED \| ARC_OPERAND_BRAKET)
252b5132	297
886a2506 NC	298	/* The flags structure. */
	299	struct arc_flag_operand
	300	{
	301	/* The flag name. */
	302	const char *name;
0d2bcfaf	303
886a2506 NC	304	/* The flag code. */
886a2506 NC	305	unsigned code;
252b5132	306
886a2506 NC	307	/* The number of bits in the operand. */
886a2506 NC	308	unsigned int bits;
252b5132	309
886a2506 NC	310	/* How far the operand is left shifted in the instruction. */
886a2506 NC	311	unsigned int shift;
252b5132	312
886a2506 NC	313	/* Available for disassembler. */
886a2506 NC	314	unsigned char favail;
84037f8c KD	315	};
84037f8c KD	316
886a2506 NC	317	/* The flag operands table. */
	318	extern const struct arc_flag_operand arc_flag_operands[];
	319	extern const unsigned arc_num_flag_operands;
0d2bcfaf	320
886a2506 NC	321	/* The flag's class structure. */
	322	struct arc_flag_class
	323	{
	324	/* Flag class. */
	325	flag_class_t class;
252b5132	326
886a2506 NC	327	/* List of valid flags (codes). */
	328	unsigned flags[256];
	329	};
252b5132	330
886a2506	331	extern const struct arc_flag_class arc_flag_classes[];
252b5132	332
886a2506 NC	333	/* Structure for special cases. */
	334	struct arc_flag_special
	335	{
	336	/* Name of special case instruction. */
	337	const char *name;
252b5132	338
886a2506 NC	339	/* List of flags applicable for special case instruction. */
	340	unsigned flags[32];
	341	};
252b5132	342
886a2506 NC	343	extern const struct arc_flag_special arc_flag_special_cases[];
	344	extern const unsigned arc_num_flag_special;
	345
	346	/* Relocation equivalence structure. */
	347	struct arc_reloc_equiv_tab
	348	{
	349	const char * name; /* String to lookup. */
	350	const char * mnemonic; /* Extra matching condition. */
24b368f8	351	unsigned flags[32]; /* Extra matching condition. */
886a2506 NC	352	signed int oldreloc; /* Old relocation. */
	353	signed int newreloc; /* New relocation. */
	354	};
252b5132	355
886a2506 NC	356	extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
886a2506 NC	357	extern const unsigned arc_num_equiv_tab;
252b5132	358
886a2506 NC	359	/* Structure for operand operations for pseudo/alias instructions. */
	360	struct arc_operand_operation
	361	{
	362	/* The index for operand from operand array. */
	363	unsigned operand_idx;
252b5132	364
886a2506 NC	365	/* Defines if it needs the operand inserted by the assembler or
	366	whether this operand comes from the pseudo instruction's
	367	operands. */
	368	unsigned char needs_insert;
252b5132	369
886a2506 NC	370	/* Count we have to add to the operand. Use negative number to
	371	subtract from the operand. Also use this number to add to 0 if
	372	the operand needs to be inserted (i.e. needs_insert == 1). */
	373	int count;
252b5132	374
886a2506 NC	375	/* Index of the operand to swap with. To be done AFTER applying
	376	inc_count. */
	377	unsigned swap_operand_idx;
252b5132 RH	378	};
252b5132 RH	379
886a2506 NC	380	/* Structure for pseudo/alias instructions. */
	381	struct arc_pseudo_insn
	382	{
	383	/* Mnemonic for pseudo/alias insn. */
	384	const char *mnemonic_p;
252b5132	385
886a2506 NC	386	/* Mnemonic for real instruction. */
886a2506 NC	387	const char *mnemonic_r;
252b5132	388
886a2506 NC	389	/* Flag that will have to be added (if any). */
886a2506 NC	390	const char *flag_r;
252b5132	391
886a2506 NC	392	/* Amount of operands. */
886a2506 NC	393	unsigned operand_cnt;
252b5132	394
886a2506 NC	395	/* Array of operand operations. */
	396	struct arc_operand_operation operand[6];
	397	};
252b5132	398
886a2506 NC	399	extern const struct arc_pseudo_insn arc_pseudo_insns[];
886a2506 NC	400	extern const unsigned arc_num_pseudo_insn;
252b5132	401
886a2506 NC	402	/* Structure for AUXILIARY registers. */
	403	struct arc_aux_reg
	404	{
	405	/* Register address. */
	406	int address;
252b5132	407
886a2506 NC	408	/* Register name. */
	409	const char *name;
	410
	411	/* Size of the string. */
	412	size_t length;
	413	};
	414
	415	extern const struct arc_aux_reg arc_aux_regs[];
	416	extern const unsigned arc_num_aux_regs;
	417
4670103e CZ	418	extern const struct arc_opcode arc_relax_opcodes[];
	419	extern const unsigned arc_num_relax_opcodes;
	420
886a2506	421	#endif /* OPCODE_ARC_H */