[deliverable/binutils-gdb.git] / include / opcode / arc.h

/* Opcode table for the ARC.
   Copyright (C) 1994-2016 Free Software Foundation, Inc.

   Contributed by Claudiu Zissulescu (claziss@synopsys.com)

   This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   the GNU Binutils.

   GAS/GDB is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   GAS/GDB is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS or GDB; see the file COPYING3.  If not, write to
   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

#ifndef OPCODE_ARC_H
#define OPCODE_ARC_H

#ifndef MAX_INSN_ARGS
#define MAX_INSN_ARGS	     6
#endif

#ifndef MAX_INSN_FLGS
#define MAX_INSN_FLGS	     3
#endif

/* Instruction Class.  */
typedef enum
  {
    ARITH,
    AUXREG,
    BRANCH,
    CONTROL,
    DSP,
    FLOAT,
    INVALID,
    JUMP,
    KERNEL,
    LOGICAL,
    MEMORY,
    BITOP,
  } insn_class_t;

/* Instruction Subclass.  */
typedef enum
  {
    NONE,
    CVT,
    BTSCN,
    CD1,
    CD2,
    DIV,
    DP,
    MPY1E,
    MPY6E,
    MPY7E,
    MPY8E,
    MPY9E,
    QUARKSE,
    SHFT1,
    SHFT2,
    SWAP,
    SP
  } insn_subclass_t;

/* Flags class.  */
typedef enum
  {
    F_CLASS_NONE,

    /* At most one flag from the set of flags can appear in the
       instruction.  */
    F_CLASS_OPTIONAL,

    /* Exactly one from from the set of flags must appear in the
       instruction.  */
    F_CLASS_REQUIRED,
  } flag_class_t;

/* The opcode table is an array of struct arc_opcode.  */
struct arc_opcode
{
  /* The opcode name.  */
  const char *name;

  /* The opcode itself.  Those bits which will be filled in with
     operands are zeroes.  */
  unsigned opcode;

  /* The opcode mask.  This is used by the disassembler.  This is a
     mask containing ones indicating those bits which must match the
     opcode field, and zeroes indicating those bits which need not
     match (and are presumably filled in by operands).  */
  unsigned mask;

  /* One bit flags for the opcode.  These are primarily used to
     indicate specific processors and environments support the
     instructions.  The defined values are listed below.  */
  unsigned cpu;

  /* The instruction class.  This is used by gdb.  */
  insn_class_t class;

  /* The instruction subclass.  */
  insn_subclass_t subclass;

  /* An array of operand codes.  Each code is an index into the
     operand table.  They appear in the order which the operands must
     appear in assembly code, and are terminated by a zero.  */
  unsigned char operands[MAX_INSN_ARGS + 1];

  /* An array of flag codes.  Each code is an index into the flag
     table.  They appear in the order which the flags must appear in
     assembly code, and are terminated by a zero.  */
  unsigned char flags[MAX_INSN_FLGS + 1];
};

/* The table itself is sorted by major opcode number, and is otherwise
   in the order in which the disassembler should consider
   instructions.  */
extern const struct arc_opcode arc_opcodes[];
extern const unsigned arc_num_opcodes;

/* CPU Availability.  */
#define ARC_OPCODE_ARC600   0x0001  /* ARC 600 specific insns.  */
#define ARC_OPCODE_ARC700   0x0002  /* ARC 700 specific insns.  */
#define ARC_OPCODE_ARCv2EM  0x0004  /* ARCv2 EM specific insns.  */
#define ARC_OPCODE_ARCv2HS  0x0008  /* ARCv2 HS specific insns.  */
#define ARC_OPCODE_NPS400   0x0010  /* NPS400 specific insns.  */

/* CPU extensions.  */
#define ARC_EA       0x0001
#define ARC_CD       0x0001    /* Mutual exclusive with EA.  */
#define ARC_LLOCK    0x0002
#define ARC_ATOMIC   0x0002    /* Mutual exclusive with LLOCK.  */
#define ARC_MPY      0x0004
#define ARC_MULT     0x0004

/* Floating point support.  */
#define ARC_DPFP     0x0010
#define ARC_SPFP     0x0020
#define ARC_FPU      0x0030

/* NORM & SWAP.  */
#define ARC_SWAP     0x0100
#define ARC_NORM     0x0200
#define ARC_BSCAN    0x0200

/* A7 specific.  */
#define ARC_UIX      0x1000
#define ARC_TSTAMP   0x1000

/* A6 specific.  */
#define ARC_VBFDW    0x1000
#define ARC_BARREL   0x1000
#define ARC_DSPA     0x1000

/* EM specific.  */
#define ARC_SHIFT    0x1000

/* V2 specific.  */
#define ARC_INTR     0x1000
#define ARC_DIV      0x1000

/* V1 specific.  */
#define ARC_XMAC     0x1000
#define ARC_CRC      0x1000

/* A macro to check for short instructions.  */
#define ARC_SHORT(mask)				\
  (((mask) & 0xFFFF0000) ? 0 : 1)

/* The operands table is an array of struct arc_operand.  */
struct arc_operand
{
  /* The number of bits in the operand.  */
  unsigned int bits;

  /* How far the operand is left shifted in the instruction.  */
  unsigned int shift;

  /* The default relocation type for this operand.  */
  signed int default_reloc;

  /* One bit syntax flags.  */
  unsigned int flags;

  /* Insertion function.  This is used by the assembler.  To insert an
     operand value into an instruction, check this field.

     If it is NULL, execute
	 i |= (op & ((1 << o->bits) - 1)) << o->shift;
     (i is the instruction which we are filling in, o is a pointer to
     this structure, and op is the opcode value; this assumes twos
     complement arithmetic).

     If this field is not NULL, then simply call it with the
     instruction and the operand value.	 It will return the new value
     of the instruction.  If the ERRMSG argument is not NULL, then if
     the operand value is illegal, *ERRMSG will be set to a warning
     string (the operand will be inserted in any case).	 If the
     operand value is legal, *ERRMSG will be unchanged (most operands
     can accept any value).  */
  unsigned (*insert) (unsigned instruction, int op, const char **errmsg);

  /* Extraction function.  This is used by the disassembler.  To
     extract this operand type from an instruction, check this field.

     If it is NULL, compute
	 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
	 if ((o->flags & ARC_OPERAND_SIGNED) != 0
	     && (op & (1 << (o->bits - 1))) != 0)
	   op -= 1 << o->bits;
     (i is the instruction, o is a pointer to this structure, and op
     is the result; this assumes twos complement arithmetic).

     If this field is not NULL, then simply call it with the
     instruction value.	 It will return the value of the operand.  If
     the INVALID argument is not NULL, *INVALID will be set to
     TRUE if this operand type can not actually be extracted from
     this operand (i.e., the instruction does not match).  If the
     operand is valid, *INVALID will not be changed.  */
  int (*extract) (unsigned instruction, bfd_boolean *invalid);
};

/* Elements in the table are retrieved by indexing with values from
   the operands field of the arc_opcodes table.  */
extern const struct arc_operand arc_operands[];
extern const unsigned arc_num_operands;
extern const unsigned arc_Toperand;
extern const unsigned arc_NToperand;

/* Values defined for the flags field of a struct arc_operand.  */

/* This operand does not actually exist in the assembler input.  This
   is used to support extended mnemonics, for which two operands fields
   are identical.  The assembler should call the insert function with
   any op value.  The disassembler should call the extract function,
   ignore the return value, and check the value placed in the invalid
   argument.  */
#define ARC_OPERAND_FAKE	0x0001

/* This operand names an integer register.  */
#define ARC_OPERAND_IR		0x0002

/* This operand takes signed values.  */
#define ARC_OPERAND_SIGNED	0x0004

/* This operand takes unsigned values.  This exists primarily so that
   a flags value of 0 can be treated as end-of-arguments.  */
#define ARC_OPERAND_UNSIGNED	0x0008

/* This operand takes long immediate values.  */
#define ARC_OPERAND_LIMM	0x0010

/* This operand is identical like the previous one.  */
#define ARC_OPERAND_DUPLICATE   0x0020

/* This operand is PC relative.  Used for internal relocs.  */
#define ARC_OPERAND_PCREL       0x0040

/* This operand is truncated.  The truncation is done accordingly to
   operand alignment attribute.  */
#define ARC_OPERAND_TRUNCATE    0x0080

/* This operand is 16bit aligned.  */
#define ARC_OPERAND_ALIGNED16   0x0100

/* This operand is 32bit aligned.  */
#define ARC_OPERAND_ALIGNED32   0x0200

/* This operand can be ignored by matching process if it is not
   present.  */
#define ARC_OPERAND_IGNORE      0x0400

/* Don't check the range when matching.	 */
#define ARC_OPERAND_NCHK	0x0800

/* Mark the braket possition.  */
#define ARC_OPERAND_BRAKET      0x1000

/* Mask for selecting the type for typecheck purposes.  */
#define ARC_OPERAND_TYPECHECK_MASK		\
  (ARC_OPERAND_IR |				\
   ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | 	\
   ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET)

/* The flags structure.  */
struct arc_flag_operand
{
  /* The flag name.  */
  const char *name;

  /* The flag code.  */
  unsigned code;

  /* The number of bits in the operand.  */
  unsigned int bits;

  /* How far the operand is left shifted in the instruction.  */
  unsigned int shift;

  /* Available for disassembler.  */
  unsigned char favail;
};

/* The flag operands table.  */
extern const struct arc_flag_operand arc_flag_operands[];
extern const unsigned arc_num_flag_operands;

/* The flag's class structure.  */
struct arc_flag_class
{
  /* Flag class.  */
  flag_class_t class;

  /* List of valid flags (codes).  */
  unsigned flags[256];
};

extern const struct arc_flag_class arc_flag_classes[];

/* Structure for special cases.  */
struct arc_flag_special
{
  /* Name of special case instruction.  */
  const char *name;

  /* List of flags applicable for special case instruction.  */
  unsigned flags[32];
};

extern const struct arc_flag_special arc_flag_special_cases[];
extern const unsigned arc_num_flag_special;

/* Relocation equivalence structure.  */
struct arc_reloc_equiv_tab
{
  const char * name;	   /* String to lookup.  */
  const char * mnemonic;   /* Extra matching condition.  */
  unsigned     flags[32];  /* Extra matching condition.  */
  signed int   oldreloc;   /* Old relocation.  */
  signed int   newreloc;   /* New relocation.  */
};

extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
extern const unsigned arc_num_equiv_tab;

/* Structure for operand operations for pseudo/alias instructions.  */
struct arc_operand_operation
{
  /* The index for operand from operand array.  */
  unsigned operand_idx;

  /* Defines if it needs the operand inserted by the assembler or
     whether this operand comes from the pseudo instruction's
     operands.  */
  unsigned char needs_insert;

  /* Count we have to add to the operand.  Use negative number to
     subtract from the operand.  Also use this number to add to 0 if
     the operand needs to be inserted (i.e. needs_insert == 1).  */
  int count;

  /* Index of the operand to swap with.  To be done AFTER applying
     inc_count.  */
  unsigned swap_operand_idx;
};

/* Structure for pseudo/alias instructions.  */
struct arc_pseudo_insn
{
  /* Mnemonic for pseudo/alias insn.  */
  const char *mnemonic_p;

  /* Mnemonic for real instruction.  */
  const char *mnemonic_r;

  /* Flag that will have to be added (if any).  */
  const char *flag_r;

  /* Amount of operands.  */
  unsigned operand_cnt;

  /* Array of operand operations.  */
  struct arc_operand_operation operand[6];
};

extern const struct arc_pseudo_insn arc_pseudo_insns[];
extern const unsigned arc_num_pseudo_insn;

/* Structure for AUXILIARY registers.  */
struct arc_aux_reg
{
  /* Register address.  */
  int address;

 /* Register name.  */
  const char *name;

  /* Size of the string.  */
  size_t length;
};

extern const struct arc_aux_reg arc_aux_regs[];
extern const unsigned arc_num_aux_regs;

extern const struct arc_opcode arc_relax_opcodes[];
extern const unsigned arc_num_relax_opcodes;

/* Macros to help generating regular pattern instructions.  */
#define FIELDA(word) (word & 0x3F)
#define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
#define FIELDC(word) ((word & 0x3F) << 6)
#define FIELDF	     (0x01 << 15)
#define FIELDQ	     (0x1F)

#define INSN3OP(MOP,SOP)	(((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
#define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
#define INSN2OP(MOP,SOP)	(INSN2OPX (MOP,0x2F,SOP))

#define INSN3OP_ABC(MOP,SOP)  (INSN3OP (MOP,SOP))
#define INSN3OP_ALC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62))
#define INSN3OP_ABL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDC (62))
#define INSN3OP_ALL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
#define INSN3OP_0BC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62))
#define INSN3OP_0LC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
#define INSN3OP_0BL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
#define INSN3OP_0LL(MOP,SOP)					\
  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
#define INSN3OP_ABU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22))
#define INSN3OP_ALU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
#define INSN3OP_0BU(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
#define INSN3OP_0LU(MOP,SOP)					\
  (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
#define INSN3OP_BBS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22))
#define INSN3OP_0LS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
#define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
#define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
#define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
#define INSN3OP_C0LL(MOP,SOP)					\
  (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
#define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
#define INSN3OP_C0LU(MOP,SOP)					\
  (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))

#define MINSN3OP_ABC  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
#define MINSN3OP_ALC  (~(FIELDF | FIELDA (63) | FIELDC (63)))
#define MINSN3OP_ABL  (~(FIELDF | FIELDA (63) | FIELDB (63)))
#define MINSN3OP_ALL  (~(FIELDF | FIELDA (63)))
#define MINSN3OP_0BC  (~(FIELDF | FIELDB (63) | FIELDC (63)))
#define MINSN3OP_0LC  (~(FIELDF | FIELDC (63)))
#define MINSN3OP_0BL  (~(FIELDF | FIELDB (63)))
#define MINSN3OP_0LL  (~(FIELDF))
#define MINSN3OP_ABU  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
#define MINSN3OP_ALU  (~(FIELDF | FIELDA (63) | FIELDC (63)))
#define MINSN3OP_0BU  (~(FIELDF | FIELDB (63) | FIELDC (63)))
#define MINSN3OP_0LU  (~(FIELDF | FIELDC (63)))
#define MINSN3OP_BBS  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
#define MINSN3OP_0LS  (~(FIELDF | FIELDA (63) | FIELDC (63)))
#define MINSN3OP_CBBC (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
#define MINSN3OP_CBBL (~(FIELDF | FIELDQ | FIELDB (63)))
#define MINSN3OP_C0LC (~(FIELDF | FIELDQ | FIELDC (63)))
#define MINSN3OP_C0LL (~(FIELDF | FIELDQ))
#define MINSN3OP_CBBU (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
#define MINSN3OP_C0LU (~(FIELDF | FIELDQ | FIELDC (63)))

#define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
#define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
#define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
#define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62)  | FIELDC (62))
#define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
#define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))

#define MINSN2OP_BC  (~(FIELDF | FIELDB (63) | FIELDC (63)))
#define MINSN2OP_BL  (~(FIELDF | FIELDB (63)))
#define MINSN2OP_0C  (~(FIELDF | FIELDC (63)))
#define MINSN2OP_0L  (~(FIELDF))
#define MINSN2OP_BU  (~(FIELDF | FIELDB (63) | FIELDC (63)))
#define MINSN2OP_0U  (~(FIELDF | FIELDC (63)))

#endif /* OPCODE_ARC_H */
Commit	Line	Data
252b5132	1	/* Opcode table for the ARC.
6f2750fe	2	Copyright (C) 1994-2016 Free Software Foundation, Inc.
886a2506 NC	3
886a2506 NC	4	Contributed by Claudiu Zissulescu (claziss@synopsys.com)
252b5132	5
0d2bcfaf NC	6	This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
0d2bcfaf NC	7	the GNU Binutils.
252b5132	8
0d2bcfaf NC	9	GAS/GDB is free software; you can redistribute it and/or modify
0d2bcfaf NC	10	it under the terms of the GNU General Public License as published by
e4e42b45	11	the Free Software Foundation; either version 3, or (at your option)
0d2bcfaf	12	any later version.
252b5132	13
0d2bcfaf NC	14	GAS/GDB is distributed in the hope that it will be useful,
0d2bcfaf NC	15	but WITHOUT ANY WARRANTY; without even the implied warranty of
886a2506	16	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0d2bcfaf NC	17	GNU General Public License for more details.
	18
	19	You should have received a copy of the GNU General Public License
e4e42b45	20	along with GAS or GDB; see the file COPYING3. If not, write to
e172dbf8 NC	21	the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
e172dbf8 NC	22	MA 02110-1301, USA. */
252b5132	23
886a2506 NC	24	#ifndef OPCODE_ARC_H
	25	#define OPCODE_ARC_H
	26
4670103e	27	#ifndef MAX_INSN_ARGS
886a2506	28	#define MAX_INSN_ARGS 6
4670103e CZ	29	#endif
	30
	31	#ifndef MAX_INSN_FLGS
886a2506	32	#define MAX_INSN_FLGS 3
4670103e	33	#endif
886a2506 NC	34
	35	/* Instruction Class. */
	36	typedef enum
	37	{
	38	ARITH,
	39	AUXREG,
	40	BRANCH,
	41	CONTROL,
	42	DSP,
	43	FLOAT,
	44	INVALID,
	45	JUMP,
	46	KERNEL,
	47	LOGICAL,
	48	MEMORY,
e23e8ebe	49	BITOP,
886a2506 NC	50	} insn_class_t;
	51
	52	/* Instruction Subclass. */
	53	typedef enum
	54	{
	55	NONE,
	56	CVT,
	57	BTSCN,
	58	CD1,
	59	CD2,
	60	DIV,
	61	DP,
	62	MPY1E,
	63	MPY6E,
	64	MPY7E,
	65	MPY8E,
	66	MPY9E,
f2dd8838	67	QUARKSE,
886a2506 NC	68	SHFT1,
	69	SHFT2,
	70	SWAP,
	71	SP
	72	} insn_subclass_t;
	73
	74	/* Flags class. */
	75	typedef enum
	76	{
1ae8ab47 AB	77	F_CLASS_NONE,
	78
	79	/* At most one flag from the set of flags can appear in the
	80	instruction. */
	81	F_CLASS_OPTIONAL,
	82
	83	/* Exactly one from from the set of flags must appear in the
	84	instruction. */
	85	F_CLASS_REQUIRED,
886a2506 NC	86	} flag_class_t;
	87
	88	/* The opcode table is an array of struct arc_opcode. */
	89	struct arc_opcode
	90	{
	91	/* The opcode name. */
	92	const char *name;
	93
	94	/* The opcode itself. Those bits which will be filled in with
	95	operands are zeroes. */
	96	unsigned opcode;
	97
	98	/* The opcode mask. This is used by the disassembler. This is a
	99	mask containing ones indicating those bits which must match the
	100	opcode field, and zeroes indicating those bits which need not
	101	match (and are presumably filled in by operands). */
	102	unsigned mask;
	103
	104	/* One bit flags for the opcode. These are primarily used to
	105	indicate specific processors and environments support the
	106	instructions. The defined values are listed below. */
	107	unsigned cpu;
	108
	109	/* The instruction class. This is used by gdb. */
	110	insn_class_t class;
	111
	112	/* The instruction subclass. */
	113	insn_subclass_t subclass;
	114
	115	/* An array of operand codes. Each code is an index into the
	116	operand table. They appear in the order which the operands must
	117	appear in assembly code, and are terminated by a zero. */
	118	unsigned char operands[MAX_INSN_ARGS + 1];
	119
	120	/* An array of flag codes. Each code is an index into the flag
	121	table. They appear in the order which the flags must appear in
	122	assembly code, and are terminated by a zero. */
	123	unsigned char flags[MAX_INSN_FLGS + 1];
	124	};
252b5132	125
886a2506 NC	126	/* The table itself is sorted by major opcode number, and is otherwise
	127	in the order in which the disassembler should consider
	128	instructions. */
	129	extern const struct arc_opcode arc_opcodes[];
	130	extern const unsigned arc_num_opcodes;
	131
	132	/* CPU Availability. */
	133	#define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
	134	#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
	135	#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
	136	#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
8699fc3e	137	#define ARC_OPCODE_NPS400 0x0010 /* NPS400 specific insns. */
886a2506 NC	138
	139	/* CPU extensions. */
	140	#define ARC_EA 0x0001
	141	#define ARC_CD 0x0001 /* Mutual exclusive with EA. */
	142	#define ARC_LLOCK 0x0002
	143	#define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */
	144	#define ARC_MPY 0x0004
	145	#define ARC_MULT 0x0004
	146
	147	/* Floating point support. */
	148	#define ARC_DPFP 0x0010
	149	#define ARC_SPFP 0x0020
	150	#define ARC_FPU 0x0030
	151
	152	/* NORM & SWAP. */
	153	#define ARC_SWAP 0x0100
	154	#define ARC_NORM 0x0200
	155	#define ARC_BSCAN 0x0200
	156
	157	/* A7 specific. */
	158	#define ARC_UIX 0x1000
	159	#define ARC_TSTAMP 0x1000
	160
	161	/* A6 specific. */
	162	#define ARC_VBFDW 0x1000
	163	#define ARC_BARREL 0x1000
	164	#define ARC_DSPA 0x1000
	165
	166	/* EM specific. */
	167	#define ARC_SHIFT 0x1000
	168
	169	/* V2 specific. */
	170	#define ARC_INTR 0x1000
	171	#define ARC_DIV 0x1000
	172
	173	/* V1 specific. */
	174	#define ARC_XMAC 0x1000
	175	#define ARC_CRC 0x1000
	176
886a2506 NC	177	/* A macro to check for short instructions. */
	178	#define ARC_SHORT(mask) \
	179	(((mask) & 0xFFFF0000) ? 0 : 1)
	180
	181	/* The operands table is an array of struct arc_operand. */
	182	struct arc_operand
	183	{
	184	/* The number of bits in the operand. */
	185	unsigned int bits;
	186
	187	/* How far the operand is left shifted in the instruction. */
	188	unsigned int shift;
	189
	190	/* The default relocation type for this operand. */
	191	signed int default_reloc;
	192
	193	/* One bit syntax flags. */
	194	unsigned int flags;
	195
	196	/* Insertion function. This is used by the assembler. To insert an
	197	operand value into an instruction, check this field.
	198
	199	If it is NULL, execute
	200	i \|= (op & ((1 << o->bits) - 1)) << o->shift;
	201	(i is the instruction which we are filling in, o is a pointer to
	202	this structure, and op is the opcode value; this assumes twos
	203	complement arithmetic).
	204
	205	If this field is not NULL, then simply call it with the
	206	instruction and the operand value. It will return the new value
	207	of the instruction. If the ERRMSG argument is not NULL, then if
	208	the operand value is illegal, *ERRMSG will be set to a warning
	209	string (the operand will be inserted in any case). If the
	210	operand value is legal, *ERRMSG will be unchanged (most operands
	211	can accept any value). */
	212	unsigned (insert) (unsigned instruction, int op, const char *errmsg);
	213
	214	/* Extraction function. This is used by the disassembler. To
	215	extract this operand type from an instruction, check this field.
	216
	217	If it is NULL, compute
	218	op = ((i) >> o->shift) & ((1 << o->bits) - 1);
	219	if ((o->flags & ARC_OPERAND_SIGNED) != 0
	220	&& (op & (1 << (o->bits - 1))) != 0)
	221	op -= 1 << o->bits;
	222	(i is the instruction, o is a pointer to this structure, and op
	223	is the result; this assumes twos complement arithmetic).
	224
	225	If this field is not NULL, then simply call it with the
	226	instruction value. It will return the value of the operand. If
	227	the INVALID argument is not NULL, *INVALID will be set to
	228	TRUE if this operand type can not actually be extracted from
	229	this operand (i.e., the instruction does not match). If the
	230	operand is valid, INVALID will not be changed. /
	231	int (extract) (unsigned instruction, bfd_boolean invalid);
	232	};
0d2bcfaf	233
886a2506 NC	234	/* Elements in the table are retrieved by indexing with values from
	235	the operands field of the arc_opcodes table. */
	236	extern const struct arc_operand arc_operands[];
	237	extern const unsigned arc_num_operands;
	238	extern const unsigned arc_Toperand;
	239	extern const unsigned arc_NToperand;
252b5132	240
886a2506	241	/* Values defined for the flags field of a struct arc_operand. */
0d2bcfaf	242
886a2506 NC	243	/* This operand does not actually exist in the assembler input. This
	244	is used to support extended mnemonics, for which two operands fields
	245	are identical. The assembler should call the insert function with
	246	any op value. The disassembler should call the extract function,
	247	ignore the return value, and check the value placed in the invalid
	248	argument. */
	249	#define ARC_OPERAND_FAKE 0x0001
252b5132	250
886a2506 NC	251	/* This operand names an integer register. */
886a2506 NC	252	#define ARC_OPERAND_IR 0x0002
0d2bcfaf	253
886a2506 NC	254	/* This operand takes signed values. */
886a2506 NC	255	#define ARC_OPERAND_SIGNED 0x0004
252b5132	256
886a2506 NC	257	/* This operand takes unsigned values. This exists primarily so that
	258	a flags value of 0 can be treated as end-of-arguments. */
	259	#define ARC_OPERAND_UNSIGNED 0x0008
252b5132	260
886a2506 NC	261	/* This operand takes long immediate values. */
886a2506 NC	262	#define ARC_OPERAND_LIMM 0x0010
252b5132	263
886a2506 NC	264	/* This operand is identical like the previous one. */
886a2506 NC	265	#define ARC_OPERAND_DUPLICATE 0x0020
0d2bcfaf	266
886a2506 NC	267	/* This operand is PC relative. Used for internal relocs. */
886a2506 NC	268	#define ARC_OPERAND_PCREL 0x0040
0d2bcfaf	269
886a2506 NC	270	/* This operand is truncated. The truncation is done accordingly to
	271	operand alignment attribute. */
	272	#define ARC_OPERAND_TRUNCATE 0x0080
0d2bcfaf	273
886a2506 NC	274	/* This operand is 16bit aligned. */
886a2506 NC	275	#define ARC_OPERAND_ALIGNED16 0x0100
0d2bcfaf	276
886a2506 NC	277	/* This operand is 32bit aligned. */
886a2506 NC	278	#define ARC_OPERAND_ALIGNED32 0x0200
0d2bcfaf	279
886a2506 NC	280	/* This operand can be ignored by matching process if it is not
	281	present. */
	282	#define ARC_OPERAND_IGNORE 0x0400
0d2bcfaf	283
886a2506 NC	284	/* Don't check the range when matching. */
886a2506 NC	285	#define ARC_OPERAND_NCHK 0x0800
0d2bcfaf	286
886a2506 NC	287	/* Mark the braket possition. */
886a2506 NC	288	#define ARC_OPERAND_BRAKET 0x1000
252b5132	289
886a2506 NC	290	/* Mask for selecting the type for typecheck purposes. */
	291	#define ARC_OPERAND_TYPECHECK_MASK \
	292	(ARC_OPERAND_IR \| \
	293	ARC_OPERAND_LIMM \| ARC_OPERAND_SIGNED \| \
	294	ARC_OPERAND_UNSIGNED \| ARC_OPERAND_BRAKET)
252b5132	295
886a2506 NC	296	/* The flags structure. */
	297	struct arc_flag_operand
	298	{
	299	/* The flag name. */
	300	const char *name;
0d2bcfaf	301
886a2506 NC	302	/* The flag code. */
886a2506 NC	303	unsigned code;
252b5132	304
886a2506 NC	305	/* The number of bits in the operand. */
886a2506 NC	306	unsigned int bits;
252b5132	307
886a2506 NC	308	/* How far the operand is left shifted in the instruction. */
886a2506 NC	309	unsigned int shift;
252b5132	310
886a2506 NC	311	/* Available for disassembler. */
886a2506 NC	312	unsigned char favail;
84037f8c KD	313	};
84037f8c KD	314
886a2506 NC	315	/* The flag operands table. */
	316	extern const struct arc_flag_operand arc_flag_operands[];
	317	extern const unsigned arc_num_flag_operands;
0d2bcfaf	318
886a2506 NC	319	/* The flag's class structure. */
	320	struct arc_flag_class
	321	{
	322	/* Flag class. */
	323	flag_class_t class;
252b5132	324
886a2506 NC	325	/* List of valid flags (codes). */
	326	unsigned flags[256];
	327	};
252b5132	328
886a2506	329	extern const struct arc_flag_class arc_flag_classes[];
252b5132	330
886a2506 NC	331	/* Structure for special cases. */
	332	struct arc_flag_special
	333	{
	334	/* Name of special case instruction. */
	335	const char *name;
252b5132	336
886a2506 NC	337	/* List of flags applicable for special case instruction. */
	338	unsigned flags[32];
	339	};
252b5132	340
886a2506 NC	341	extern const struct arc_flag_special arc_flag_special_cases[];
	342	extern const unsigned arc_num_flag_special;
	343
	344	/* Relocation equivalence structure. */
	345	struct arc_reloc_equiv_tab
	346	{
	347	const char * name; /* String to lookup. */
	348	const char * mnemonic; /* Extra matching condition. */
24b368f8	349	unsigned flags[32]; /* Extra matching condition. */
886a2506 NC	350	signed int oldreloc; /* Old relocation. */
	351	signed int newreloc; /* New relocation. */
	352	};
252b5132	353
886a2506 NC	354	extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
886a2506 NC	355	extern const unsigned arc_num_equiv_tab;
252b5132	356
886a2506 NC	357	/* Structure for operand operations for pseudo/alias instructions. */
	358	struct arc_operand_operation
	359	{
	360	/* The index for operand from operand array. */
	361	unsigned operand_idx;
252b5132	362
886a2506 NC	363	/* Defines if it needs the operand inserted by the assembler or
	364	whether this operand comes from the pseudo instruction's
	365	operands. */
	366	unsigned char needs_insert;
252b5132	367
886a2506 NC	368	/* Count we have to add to the operand. Use negative number to
	369	subtract from the operand. Also use this number to add to 0 if
	370	the operand needs to be inserted (i.e. needs_insert == 1). */
	371	int count;
252b5132	372
886a2506 NC	373	/* Index of the operand to swap with. To be done AFTER applying
	374	inc_count. */
	375	unsigned swap_operand_idx;
252b5132 RH	376	};
252b5132 RH	377
886a2506 NC	378	/* Structure for pseudo/alias instructions. */
	379	struct arc_pseudo_insn
	380	{
	381	/* Mnemonic for pseudo/alias insn. */
	382	const char *mnemonic_p;
252b5132	383
886a2506 NC	384	/* Mnemonic for real instruction. */
886a2506 NC	385	const char *mnemonic_r;
252b5132	386
886a2506 NC	387	/* Flag that will have to be added (if any). */
886a2506 NC	388	const char *flag_r;
252b5132	389
886a2506 NC	390	/* Amount of operands. */
886a2506 NC	391	unsigned operand_cnt;
252b5132	392
886a2506 NC	393	/* Array of operand operations. */
	394	struct arc_operand_operation operand[6];
	395	};
252b5132	396
886a2506 NC	397	extern const struct arc_pseudo_insn arc_pseudo_insns[];
886a2506 NC	398	extern const unsigned arc_num_pseudo_insn;
252b5132	399
886a2506 NC	400	/* Structure for AUXILIARY registers. */
	401	struct arc_aux_reg
	402	{
	403	/* Register address. */
	404	int address;
252b5132	405
886a2506 NC	406	/* Register name. */
	407	const char *name;
	408
	409	/* Size of the string. */
	410	size_t length;
	411	};
	412
	413	extern const struct arc_aux_reg arc_aux_regs[];
	414	extern const unsigned arc_num_aux_regs;
	415
4670103e CZ	416	extern const struct arc_opcode arc_relax_opcodes[];
	417	extern const unsigned arc_num_relax_opcodes;
	418
f2dd8838 CZ	419	/* Macros to help generating regular pattern instructions. */
	420	#define FIELDA(word) (word & 0x3F)
	421	#define FIELDB(word) (((word & 0x07) << 24) \| (((word >> 3) & 0x07) << 12))
	422	#define FIELDC(word) ((word & 0x3F) << 6)
	423	#define FIELDF (0x01 << 15)
	424	#define FIELDQ (0x1F)
	425
	426	#define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) \| ((SOP & 0x3F) << 16))
	427	#define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) \| (SOP2 & 0x3F))
	428	#define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP))
	429
	430	#define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP))
	431	#define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) \| FIELDB (62))
	432	#define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) \| FIELDC (62))
	433	#define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) \| FIELDB (62) \| FIELDC (62))
	434	#define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) \| FIELDA (62))
	435	#define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) \| FIELDA (62) \| FIELDB (62))
	436	#define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) \| FIELDA (62) \| FIELDC (62))
	437	#define INSN3OP_0LL(MOP,SOP) \
	438	(INSN3OP (MOP,SOP) \| FIELDA (62) \| FIELDB (62) \| FIELDC (62))
	439	#define INSN3OP_ABU(MOP,SOP) (INSN3OP (MOP,SOP) \| (0x01 << 22))
	440	#define INSN3OP_ALU(MOP,SOP) (INSN3OP (MOP,SOP) \| (0x01 << 22) \| FIELDB (62))
	441	#define INSN3OP_0BU(MOP,SOP) (INSN3OP (MOP,SOP) \| FIELDA (62) \| (0x01 << 22))
	442	#define INSN3OP_0LU(MOP,SOP) \
	443	(INSN3OP (MOP,SOP) \| FIELDA (62) \| (0x01 << 22) \| FIELDB (62))
	444	#define INSN3OP_BBS(MOP,SOP) (INSN3OP (MOP,SOP) \| (0x02 << 22))
	445	#define INSN3OP_0LS(MOP,SOP) (INSN3OP (MOP,SOP) \| (0x02 << 22) \| FIELDB (62))
	446	#define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) \| (0x03 << 22))
	447	#define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) \| (0x03 << 22) \| FIELDC (62))
	448	#define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) \| (0x03 << 22) \| FIELDB (62))
	449	#define INSN3OP_C0LL(MOP,SOP) \
	450	(INSN3OP (MOP,SOP) \| (0x03 << 22) \| FIELDC (62) \| FIELDB (62))
	451	#define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) \| (0x03 << 22) \| (0x01 << 5))
	452	#define INSN3OP_C0LU(MOP,SOP) \
	453	(INSN3OP (MOP,SOP) \| (0x03 << 22) \| (0x01 << 5) \| FIELDB (62))
	454
	455	#define MINSN3OP_ABC (~(FIELDF \| FIELDA (63) \| FIELDB (63) \| FIELDC (63)))
	456	#define MINSN3OP_ALC (~(FIELDF \| FIELDA (63) \| FIELDC (63)))
	457	#define MINSN3OP_ABL (~(FIELDF \| FIELDA (63) \| FIELDB (63)))
	458	#define MINSN3OP_ALL (~(FIELDF \| FIELDA (63)))
	459	#define MINSN3OP_0BC (~(FIELDF \| FIELDB (63) \| FIELDC (63)))
	460	#define MINSN3OP_0LC (~(FIELDF \| FIELDC (63)))
	461	#define MINSN3OP_0BL (~(FIELDF \| FIELDB (63)))
	462	#define MINSN3OP_0LL (~(FIELDF))
	463	#define MINSN3OP_ABU (~(FIELDF \| FIELDA (63) \| FIELDB (63) \| FIELDC (63)))
	464	#define MINSN3OP_ALU (~(FIELDF \| FIELDA (63) \| FIELDC (63)))
	465	#define MINSN3OP_0BU (~(FIELDF \| FIELDB (63) \| FIELDC (63)))
	466	#define MINSN3OP_0LU (~(FIELDF \| FIELDC (63)))
	467	#define MINSN3OP_BBS (~(FIELDF \| FIELDA (63) \| FIELDB (63) \| FIELDC (63)))
	468	#define MINSN3OP_0LS (~(FIELDF \| FIELDA (63) \| FIELDC (63)))
	469	#define MINSN3OP_CBBC (~(FIELDF \| FIELDQ \| FIELDB (63) \| FIELDC (63)))
	470	#define MINSN3OP_CBBL (~(FIELDF \| FIELDQ \| FIELDB (63)))
	471	#define MINSN3OP_C0LC (~(FIELDF \| FIELDQ \| FIELDC (63)))
	472	#define MINSN3OP_C0LL (~(FIELDF \| FIELDQ))
	473	#define MINSN3OP_CBBU (~(FIELDF \| FIELDQ \| FIELDB (63) \| FIELDC (63)))
	474	#define MINSN3OP_C0LU (~(FIELDF \| FIELDQ \| FIELDC (63)))
	475
	476	#define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
	477	#define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) \| FIELDC (62))
	478	#define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) \| FIELDB (62))
	479	#define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) \| FIELDB (62) \| FIELDC (62))
	480	#define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) \| (0x01 << 22))
	481	#define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) \| (0x01 << 22) \| FIELDB (62))
	482
483	#define MINSN2OP_BC (~(FIELDF \| FIELDB (63) \| FIELDC (63)))
484	#define MINSN2OP_BL (~(FIELDF \| FIELDB (63)))
485	#define MINSN2OP_0C (~(FIELDF \| FIELDC (63)))
486	#define MINSN2OP_0L (~(FIELDF))
487	#define MINSN2OP_BU (~(FIELDF \| FIELDB (63) \| FIELDC (63)))
488	#define MINSN2OP_0U (~(FIELDF \| FIELDC (63)))
489
886a2506	490	#endif /* OPCODE_ARC_H */