[deliverable/binutils-gdb.git] / include / opcode / arc.h

/* Opcode table for the ARC.
   Copyright (C) 1994-2016 Free Software Foundation, Inc.

   Contributed by Claudiu Zissulescu (claziss@synopsys.com)

   This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   the GNU Binutils.

   GAS/GDB is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   GAS/GDB is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS or GDB; see the file COPYING3.  If not, write to
   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

#ifndef OPCODE_ARC_H
#define OPCODE_ARC_H

#ifndef MAX_INSN_ARGS
#define MAX_INSN_ARGS	     6
#endif

#ifndef MAX_INSN_FLGS
#define MAX_INSN_FLGS	     3
#endif

/* Instruction Class.  */
typedef enum
  {
    ARITH,
    AUXREG,
    BRANCH,
    CONTROL,
    DSP,
    FLOAT,
    INVALID,
    JUMP,
    KERNEL,
    LOGICAL,
    MEMORY,
    BITOP,
  } insn_class_t;

/* Instruction Subclass.  */
typedef enum
  {
    NONE,
    CVT,
    BTSCN,
    CD1,
    CD2,
    DIV,
    DP,
    DPA,
    DPX,
    MPY1E,
    MPY6E,
    MPY7E,
    MPY8E,
    MPY9E,
    QUARKSE,
    SHFT1,
    SHFT2,
    SWAP,
    SP,
    SPX
  } insn_subclass_t;

/* Flags class.  */
typedef enum
  {
    F_CLASS_NONE,

    /* At most one flag from the set of flags can appear in the
       instruction.  */
    F_CLASS_OPTIONAL,

    /* Exactly one from from the set of flags must appear in the
       instruction.  */
    F_CLASS_REQUIRED,
  } flag_class_t;

/* The opcode table is an array of struct arc_opcode.  */
struct arc_opcode
{
  /* The opcode name.  */
  const char *name;

  /* The opcode itself.  Those bits which will be filled in with
     operands are zeroes.  */
  unsigned opcode;

  /* The opcode mask.  This is used by the disassembler.  This is a
     mask containing ones indicating those bits which must match the
     opcode field, and zeroes indicating those bits which need not
     match (and are presumably filled in by operands).  */
  unsigned mask;

  /* One bit flags for the opcode.  These are primarily used to
     indicate specific processors and environments support the
     instructions.  The defined values are listed below.  */
  unsigned cpu;

  /* The instruction class.  This is used by gdb.  */
  insn_class_t class;

  /* The instruction subclass.  */
  insn_subclass_t subclass;

  /* An array of operand codes.  Each code is an index into the
     operand table.  They appear in the order which the operands must
     appear in assembly code, and are terminated by a zero.  */
  unsigned char operands[MAX_INSN_ARGS + 1];

  /* An array of flag codes.  Each code is an index into the flag
     table.  They appear in the order which the flags must appear in
     assembly code, and are terminated by a zero.  */
  unsigned char flags[MAX_INSN_FLGS + 1];
};

/* The table itself is sorted by major opcode number, and is otherwise
   in the order in which the disassembler should consider
   instructions.  */
extern const struct arc_opcode arc_opcodes[];
extern const unsigned arc_num_opcodes;

/* CPU Availability.  */
#define ARC_OPCODE_ARC600   0x0001  /* ARC 600 specific insns.  */
#define ARC_OPCODE_ARC700   0x0002  /* ARC 700 specific insns.  */
#define ARC_OPCODE_ARCv2EM  0x0004  /* ARCv2 EM specific insns.  */
#define ARC_OPCODE_ARCv2HS  0x0008  /* ARCv2 HS specific insns.  */
#define ARC_OPCODE_NPS400   0x0010  /* NPS400 specific insns.  */

/* CPU extensions.  */
#define ARC_EA       0x0001
#define ARC_CD       0x0001    /* Mutual exclusive with EA.  */
#define ARC_LLOCK    0x0002
#define ARC_ATOMIC   0x0002    /* Mutual exclusive with LLOCK.  */
#define ARC_MPY      0x0004
#define ARC_MULT     0x0004

/* Floating point support.  */
#define ARC_DPFP     0x0010
#define ARC_SPFP     0x0020
#define ARC_FPU      0x0030
#define ARC_FPUDA    0x0040

/* NORM & SWAP.  */
#define ARC_SWAP     0x0100
#define ARC_NORM     0x0200
#define ARC_BSCAN    0x0200

/* A7 specific.  */
#define ARC_UIX      0x1000
#define ARC_TSTAMP   0x1000

/* A6 specific.  */
#define ARC_VBFDW    0x1000
#define ARC_BARREL   0x1000
#define ARC_DSPA     0x1000

/* EM specific.  */
#define ARC_SHIFT    0x1000

/* V2 specific.  */
#define ARC_INTR     0x1000
#define ARC_DIV      0x1000

/* V1 specific.  */
#define ARC_XMAC     0x1000
#define ARC_CRC      0x1000

/* A macro to check for short instructions.  */
#define ARC_SHORT(mask)				\
  (((mask) & 0xFFFF0000) ? 0 : 1)

/* The operands table is an array of struct arc_operand.  */
struct arc_operand
{
  /* The number of bits in the operand.  */
  unsigned int bits;

  /* How far the operand is left shifted in the instruction.  */
  unsigned int shift;

  /* The default relocation type for this operand.  */
  signed int default_reloc;

  /* One bit syntax flags.  */
  unsigned int flags;

  /* Insertion function.  This is used by the assembler.  To insert an
     operand value into an instruction, check this field.

     If it is NULL, execute
	 i |= (op & ((1 << o->bits) - 1)) << o->shift;
     (i is the instruction which we are filling in, o is a pointer to
     this structure, and op is the opcode value; this assumes twos
     complement arithmetic).

     If this field is not NULL, then simply call it with the
     instruction and the operand value.	 It will return the new value
     of the instruction.  If the ERRMSG argument is not NULL, then if
     the operand value is illegal, *ERRMSG will be set to a warning
     string (the operand will be inserted in any case).	 If the
     operand value is legal, *ERRMSG will be unchanged (most operands
     can accept any value).  */
  unsigned (*insert) (unsigned instruction, int op, const char **errmsg);

  /* Extraction function.  This is used by the disassembler.  To
     extract this operand type from an instruction, check this field.

     If it is NULL, compute
	 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
	 if ((o->flags & ARC_OPERAND_SIGNED) != 0
	     && (op & (1 << (o->bits - 1))) != 0)
	   op -= 1 << o->bits;
     (i is the instruction, o is a pointer to this structure, and op
     is the result; this assumes twos complement arithmetic).

     If this field is not NULL, then simply call it with the
     instruction value.	 It will return the value of the operand.  If
     the INVALID argument is not NULL, *INVALID will be set to
     TRUE if this operand type can not actually be extracted from
     this operand (i.e., the instruction does not match).  If the
     operand is valid, *INVALID will not be changed.  */
  int (*extract) (unsigned instruction, bfd_boolean *invalid);
};

/* Elements in the table are retrieved by indexing with values from
   the operands field of the arc_opcodes table.  */
extern const struct arc_operand arc_operands[];
extern const unsigned arc_num_operands;
extern const unsigned arc_Toperand;
extern const unsigned arc_NToperand;

/* Values defined for the flags field of a struct arc_operand.  */

/* This operand does not actually exist in the assembler input.  This
   is used to support extended mnemonics, for which two operands fields
   are identical.  The assembler should call the insert function with
   any op value.  The disassembler should call the extract function,
   ignore the return value, and check the value placed in the invalid
   argument.  */
#define ARC_OPERAND_FAKE	0x0001

/* This operand names an integer register.  */
#define ARC_OPERAND_IR		0x0002

/* This operand takes signed values.  */
#define ARC_OPERAND_SIGNED	0x0004

/* This operand takes unsigned values.  This exists primarily so that
   a flags value of 0 can be treated as end-of-arguments.  */
#define ARC_OPERAND_UNSIGNED	0x0008

/* This operand takes long immediate values.  */
#define ARC_OPERAND_LIMM	0x0010

/* This operand is identical like the previous one.  */
#define ARC_OPERAND_DUPLICATE   0x0020

/* This operand is PC relative.  Used for internal relocs.  */
#define ARC_OPERAND_PCREL       0x0040

/* This operand is truncated.  The truncation is done accordingly to
   operand alignment attribute.  */
#define ARC_OPERAND_TRUNCATE    0x0080

/* This operand is 16bit aligned.  */
#define ARC_OPERAND_ALIGNED16   0x0100

/* This operand is 32bit aligned.  */
#define ARC_OPERAND_ALIGNED32   0x0200

/* This operand can be ignored by matching process if it is not
   present.  */
#define ARC_OPERAND_IGNORE      0x0400

/* Don't check the range when matching.	 */
#define ARC_OPERAND_NCHK	0x0800

/* Mark the braket possition.  */
#define ARC_OPERAND_BRAKET      0x1000

/* Mask for selecting the type for typecheck purposes.  */
#define ARC_OPERAND_TYPECHECK_MASK		\
  (ARC_OPERAND_IR |				\
   ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | 	\
   ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET)

/* The flags structure.  */
struct arc_flag_operand
{
  /* The flag name.  */
  const char *name;

  /* The flag code.  */
  unsigned code;

  /* The number of bits in the operand.  */
  unsigned int bits;

  /* How far the operand is left shifted in the instruction.  */
  unsigned int shift;

  /* Available for disassembler.  */
  unsigned char favail;
};

/* The flag operands table.  */
extern const struct arc_flag_operand arc_flag_operands[];
extern const unsigned arc_num_flag_operands;

/* The flag's class structure.  */
struct arc_flag_class
{
  /* Flag class.  */
  flag_class_t class;

  /* List of valid flags (codes).  */
  unsigned flags[256];
};

extern const struct arc_flag_class arc_flag_classes[];

/* Structure for special cases.  */
struct arc_flag_special
{
  /* Name of special case instruction.  */
  const char *name;

  /* List of flags applicable for special case instruction.  */
  unsigned flags[32];
};

extern const struct arc_flag_special arc_flag_special_cases[];
extern const unsigned arc_num_flag_special;

/* Relocation equivalence structure.  */
struct arc_reloc_equiv_tab
{
  const char * name;	   /* String to lookup.  */
  const char * mnemonic;   /* Extra matching condition.  */
  unsigned     flags[32];  /* Extra matching condition.  */
  signed int   oldreloc;   /* Old relocation.  */
  signed int   newreloc;   /* New relocation.  */
};

extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
extern const unsigned arc_num_equiv_tab;

/* Structure for operand operations for pseudo/alias instructions.  */
struct arc_operand_operation
{
  /* The index for operand from operand array.  */
  unsigned operand_idx;

  /* Defines if it needs the operand inserted by the assembler or
     whether this operand comes from the pseudo instruction's
     operands.  */
  unsigned char needs_insert;

  /* Count we have to add to the operand.  Use negative number to
     subtract from the operand.  Also use this number to add to 0 if
     the operand needs to be inserted (i.e. needs_insert == 1).  */
  int count;

  /* Index of the operand to swap with.  To be done AFTER applying
     inc_count.  */
  unsigned swap_operand_idx;
};

/* Structure for pseudo/alias instructions.  */
struct arc_pseudo_insn
{
  /* Mnemonic for pseudo/alias insn.  */
  const char *mnemonic_p;

  /* Mnemonic for real instruction.  */
  const char *mnemonic_r;

  /* Flag that will have to be added (if any).  */
  const char *flag_r;

  /* Amount of operands.  */
  unsigned operand_cnt;

  /* Array of operand operations.  */
  struct arc_operand_operation operand[6];
};

extern const struct arc_pseudo_insn arc_pseudo_insns[];
extern const unsigned arc_num_pseudo_insn;

/* Structure for AUXILIARY registers.  */
struct arc_aux_reg
{
  /* Register address.  */
  int address;

  /* AUX register subclass.  */
  insn_subclass_t subclass;

  /* Register name.  */
  const char *name;

  /* Size of the string.  */
  size_t length;
};

extern const struct arc_aux_reg arc_aux_regs[];
extern const unsigned arc_num_aux_regs;

extern const struct arc_opcode arc_relax_opcodes[];
extern const unsigned arc_num_relax_opcodes;

/* Macros to help generating regular pattern instructions.  */
#define FIELDA(word) (word & 0x3F)
#define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
#define FIELDC(word) ((word & 0x3F) << 6)
#define FIELDF	     (0x01 << 15)
#define FIELDQ	     (0x1F)

#define INSN3OP(MOP,SOP)	(((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
#define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
#define INSN2OP(MOP,SOP)	(INSN2OPX (MOP,0x2F,SOP))

#define INSN3OP_ABC(MOP,SOP)  (INSN3OP (MOP,SOP))
#define INSN3OP_ALC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62))
#define INSN3OP_ABL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDC (62))
#define INSN3OP_ALL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
#define INSN3OP_0BC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62))
#define INSN3OP_0LC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
#define INSN3OP_0BL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
#define INSN3OP_0LL(MOP,SOP)					\
  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
#define INSN3OP_ABU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22))
#define INSN3OP_ALU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
#define INSN3OP_0BU(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
#define INSN3OP_0LU(MOP,SOP)					\
  (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
#define INSN3OP_BBS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22))
#define INSN3OP_0LS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
#define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
#define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
#define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
#define INSN3OP_C0LL(MOP,SOP)					\
  (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
#define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
#define INSN3OP_C0LU(MOP,SOP)					\
  (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))

#define MINSN3OP_ABC  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
#define MINSN3OP_ALC  (~(FIELDF | FIELDA (63) | FIELDC (63)))
#define MINSN3OP_ABL  (~(FIELDF | FIELDA (63) | FIELDB (63)))
#define MINSN3OP_ALL  (~(FIELDF | FIELDA (63)))
#define MINSN3OP_0BC  (~(FIELDF | FIELDB (63) | FIELDC (63)))
#define MINSN3OP_0LC  (~(FIELDF | FIELDC (63)))
#define MINSN3OP_0BL  (~(FIELDF | FIELDB (63)))
#define MINSN3OP_0LL  (~(FIELDF))
#define MINSN3OP_ABU  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
#define MINSN3OP_ALU  (~(FIELDF | FIELDA (63) | FIELDC (63)))
#define MINSN3OP_0BU  (~(FIELDF | FIELDB (63) | FIELDC (63)))
#define MINSN3OP_0LU  (~(FIELDF | FIELDC (63)))
#define MINSN3OP_BBS  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
#define MINSN3OP_0LS  (~(FIELDF | FIELDA (63) | FIELDC (63)))
#define MINSN3OP_CBBC (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
#define MINSN3OP_CBBL (~(FIELDF | FIELDQ | FIELDB (63)))
#define MINSN3OP_C0LC (~(FIELDF | FIELDQ | FIELDC (63)))
#define MINSN3OP_C0LL (~(FIELDF | FIELDQ))
#define MINSN3OP_CBBU (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
#define MINSN3OP_C0LU (~(FIELDF | FIELDQ | FIELDC (63)))

#define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
#define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
#define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
#define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62)  | FIELDC (62))
#define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
#define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))

#define MINSN2OP_BC  (~(FIELDF | FIELDB (63) | FIELDC (63)))
#define MINSN2OP_BL  (~(FIELDF | FIELDB (63)))
#define MINSN2OP_0C  (~(FIELDF | FIELDC (63)))
#define MINSN2OP_0L  (~(FIELDF))
#define MINSN2OP_BU  (~(FIELDF | FIELDB (63) | FIELDC (63)))
#define MINSN2OP_0U  (~(FIELDF | FIELDC (63)))

#endif /* OPCODE_ARC_H */
Commit	Line	Data
252b5132	1	/* Opcode table for the ARC.
6f2750fe	2	Copyright (C) 1994-2016 Free Software Foundation, Inc.
886a2506 NC	3
886a2506 NC	4	Contributed by Claudiu Zissulescu (claziss@synopsys.com)
252b5132	5
0d2bcfaf NC	6	This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
0d2bcfaf NC	7	the GNU Binutils.
252b5132	8
0d2bcfaf NC	9	GAS/GDB is free software; you can redistribute it and/or modify
0d2bcfaf NC	10	it under the terms of the GNU General Public License as published by
e4e42b45	11	the Free Software Foundation; either version 3, or (at your option)
0d2bcfaf	12	any later version.
252b5132	13
0d2bcfaf NC	14	GAS/GDB is distributed in the hope that it will be useful,
0d2bcfaf NC	15	but WITHOUT ANY WARRANTY; without even the implied warranty of
886a2506	16	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0d2bcfaf NC	17	GNU General Public License for more details.
	18
	19	You should have received a copy of the GNU General Public License
e4e42b45	20	along with GAS or GDB; see the file COPYING3. If not, write to
e172dbf8 NC	21	the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
e172dbf8 NC	22	MA 02110-1301, USA. */
252b5132	23
886a2506 NC	24	#ifndef OPCODE_ARC_H
	25	#define OPCODE_ARC_H
	26
4670103e	27	#ifndef MAX_INSN_ARGS
886a2506	28	#define MAX_INSN_ARGS 6
4670103e CZ	29	#endif
	30
	31	#ifndef MAX_INSN_FLGS
886a2506	32	#define MAX_INSN_FLGS 3
4670103e	33	#endif
886a2506 NC	34
	35	/* Instruction Class. */
	36	typedef enum
	37	{
	38	ARITH,
	39	AUXREG,
	40	BRANCH,
	41	CONTROL,
	42	DSP,
	43	FLOAT,
	44	INVALID,
	45	JUMP,
	46	KERNEL,
	47	LOGICAL,
	48	MEMORY,
e23e8ebe	49	BITOP,
886a2506 NC	50	} insn_class_t;
	51
	52	/* Instruction Subclass. */
	53	typedef enum
	54	{
	55	NONE,
	56	CVT,
	57	BTSCN,
	58	CD1,
	59	CD2,
	60	DIV,
	61	DP,
8ddf6b2a CZ	62	DPA,
8ddf6b2a CZ	63	DPX,
886a2506 NC	64	MPY1E,
	65	MPY6E,
	66	MPY7E,
	67	MPY8E,
	68	MPY9E,
f2dd8838	69	QUARKSE,
886a2506 NC	70	SHFT1,
	71	SHFT2,
	72	SWAP,
8ddf6b2a CZ	73	SP,
8ddf6b2a CZ	74	SPX
886a2506 NC	75	} insn_subclass_t;
	76
	77	/* Flags class. */
	78	typedef enum
	79	{
1ae8ab47 AB	80	F_CLASS_NONE,
	81
	82	/* At most one flag from the set of flags can appear in the
	83	instruction. */
	84	F_CLASS_OPTIONAL,
	85
	86	/* Exactly one from from the set of flags must appear in the
	87	instruction. */
	88	F_CLASS_REQUIRED,
886a2506 NC	89	} flag_class_t;
	90
	91	/* The opcode table is an array of struct arc_opcode. */
	92	struct arc_opcode
	93	{
	94	/* The opcode name. */
	95	const char *name;
	96
	97	/* The opcode itself. Those bits which will be filled in with
	98	operands are zeroes. */
	99	unsigned opcode;
	100
	101	/* The opcode mask. This is used by the disassembler. This is a
	102	mask containing ones indicating those bits which must match the
	103	opcode field, and zeroes indicating those bits which need not
	104	match (and are presumably filled in by operands). */
	105	unsigned mask;
	106
	107	/* One bit flags for the opcode. These are primarily used to
	108	indicate specific processors and environments support the
	109	instructions. The defined values are listed below. */
	110	unsigned cpu;
	111
	112	/* The instruction class. This is used by gdb. */
	113	insn_class_t class;
	114
	115	/* The instruction subclass. */
	116	insn_subclass_t subclass;
	117
	118	/* An array of operand codes. Each code is an index into the
	119	operand table. They appear in the order which the operands must
	120	appear in assembly code, and are terminated by a zero. */
	121	unsigned char operands[MAX_INSN_ARGS + 1];
	122
	123	/* An array of flag codes. Each code is an index into the flag
	124	table. They appear in the order which the flags must appear in
	125	assembly code, and are terminated by a zero. */
	126	unsigned char flags[MAX_INSN_FLGS + 1];
	127	};
252b5132	128
886a2506 NC	129	/* The table itself is sorted by major opcode number, and is otherwise
	130	in the order in which the disassembler should consider
	131	instructions. */
	132	extern const struct arc_opcode arc_opcodes[];
	133	extern const unsigned arc_num_opcodes;
	134
	135	/* CPU Availability. */
	136	#define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
	137	#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
	138	#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
	139	#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
8699fc3e	140	#define ARC_OPCODE_NPS400 0x0010 /* NPS400 specific insns. */
886a2506 NC	141
	142	/* CPU extensions. */
	143	#define ARC_EA 0x0001
	144	#define ARC_CD 0x0001 /* Mutual exclusive with EA. */
	145	#define ARC_LLOCK 0x0002
	146	#define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */
	147	#define ARC_MPY 0x0004
	148	#define ARC_MULT 0x0004
	149
	150	/* Floating point support. */
	151	#define ARC_DPFP 0x0010
	152	#define ARC_SPFP 0x0020
	153	#define ARC_FPU 0x0030
8ddf6b2a	154	#define ARC_FPUDA 0x0040
886a2506 NC	155
	156	/* NORM & SWAP. */
	157	#define ARC_SWAP 0x0100
	158	#define ARC_NORM 0x0200
	159	#define ARC_BSCAN 0x0200
	160
	161	/* A7 specific. */
	162	#define ARC_UIX 0x1000
	163	#define ARC_TSTAMP 0x1000
	164
	165	/* A6 specific. */
	166	#define ARC_VBFDW 0x1000
	167	#define ARC_BARREL 0x1000
	168	#define ARC_DSPA 0x1000
	169
	170	/* EM specific. */
	171	#define ARC_SHIFT 0x1000
	172
	173	/* V2 specific. */
	174	#define ARC_INTR 0x1000
	175	#define ARC_DIV 0x1000
	176
	177	/* V1 specific. */
	178	#define ARC_XMAC 0x1000
	179	#define ARC_CRC 0x1000
	180
886a2506 NC	181	/* A macro to check for short instructions. */
	182	#define ARC_SHORT(mask) \
	183	(((mask) & 0xFFFF0000) ? 0 : 1)
	184
	185	/* The operands table is an array of struct arc_operand. */
	186	struct arc_operand
	187	{
	188	/* The number of bits in the operand. */
	189	unsigned int bits;
	190
	191	/* How far the operand is left shifted in the instruction. */
	192	unsigned int shift;
	193
	194	/* The default relocation type for this operand. */
	195	signed int default_reloc;
	196
	197	/* One bit syntax flags. */
	198	unsigned int flags;
	199
	200	/* Insertion function. This is used by the assembler. To insert an
	201	operand value into an instruction, check this field.
	202
	203	If it is NULL, execute
	204	i \|= (op & ((1 << o->bits) - 1)) << o->shift;
	205	(i is the instruction which we are filling in, o is a pointer to
	206	this structure, and op is the opcode value; this assumes twos
	207	complement arithmetic).
	208
	209	If this field is not NULL, then simply call it with the
	210	instruction and the operand value. It will return the new value
	211	of the instruction. If the ERRMSG argument is not NULL, then if
	212	the operand value is illegal, *ERRMSG will be set to a warning
	213	string (the operand will be inserted in any case). If the
	214	operand value is legal, *ERRMSG will be unchanged (most operands
	215	can accept any value). */
	216	unsigned (insert) (unsigned instruction, int op, const char *errmsg);
	217
	218	/* Extraction function. This is used by the disassembler. To
	219	extract this operand type from an instruction, check this field.
	220
	221	If it is NULL, compute
	222	op = ((i) >> o->shift) & ((1 << o->bits) - 1);
	223	if ((o->flags & ARC_OPERAND_SIGNED) != 0
	224	&& (op & (1 << (o->bits - 1))) != 0)
	225	op -= 1 << o->bits;
	226	(i is the instruction, o is a pointer to this structure, and op
	227	is the result; this assumes twos complement arithmetic).
	228
	229	If this field is not NULL, then simply call it with the
	230	instruction value. It will return the value of the operand. If
	231	the INVALID argument is not NULL, *INVALID will be set to
	232	TRUE if this operand type can not actually be extracted from
	233	this operand (i.e., the instruction does not match). If the
	234	operand is valid, INVALID will not be changed. /
	235	int (extract) (unsigned instruction, bfd_boolean invalid);
	236	};
0d2bcfaf	237
886a2506 NC	238	/* Elements in the table are retrieved by indexing with values from
	239	the operands field of the arc_opcodes table. */
	240	extern const struct arc_operand arc_operands[];
	241	extern const unsigned arc_num_operands;
	242	extern const unsigned arc_Toperand;
	243	extern const unsigned arc_NToperand;
252b5132	244
886a2506	245	/* Values defined for the flags field of a struct arc_operand. */
0d2bcfaf	246
886a2506 NC	247	/* This operand does not actually exist in the assembler input. This
	248	is used to support extended mnemonics, for which two operands fields
	249	are identical. The assembler should call the insert function with
	250	any op value. The disassembler should call the extract function,
	251	ignore the return value, and check the value placed in the invalid
	252	argument. */
	253	#define ARC_OPERAND_FAKE 0x0001
252b5132	254
886a2506 NC	255	/* This operand names an integer register. */
886a2506 NC	256	#define ARC_OPERAND_IR 0x0002
0d2bcfaf	257
886a2506 NC	258	/* This operand takes signed values. */
886a2506 NC	259	#define ARC_OPERAND_SIGNED 0x0004
252b5132	260
886a2506 NC	261	/* This operand takes unsigned values. This exists primarily so that
	262	a flags value of 0 can be treated as end-of-arguments. */
	263	#define ARC_OPERAND_UNSIGNED 0x0008
252b5132	264
886a2506 NC	265	/* This operand takes long immediate values. */
886a2506 NC	266	#define ARC_OPERAND_LIMM 0x0010
252b5132	267
886a2506 NC	268	/* This operand is identical like the previous one. */
886a2506 NC	269	#define ARC_OPERAND_DUPLICATE 0x0020
0d2bcfaf	270
886a2506 NC	271	/* This operand is PC relative. Used for internal relocs. */
886a2506 NC	272	#define ARC_OPERAND_PCREL 0x0040
0d2bcfaf	273
886a2506 NC	274	/* This operand is truncated. The truncation is done accordingly to
	275	operand alignment attribute. */
	276	#define ARC_OPERAND_TRUNCATE 0x0080
0d2bcfaf	277
886a2506 NC	278	/* This operand is 16bit aligned. */
886a2506 NC	279	#define ARC_OPERAND_ALIGNED16 0x0100
0d2bcfaf	280
886a2506 NC	281	/* This operand is 32bit aligned. */
886a2506 NC	282	#define ARC_OPERAND_ALIGNED32 0x0200
0d2bcfaf	283
886a2506 NC	284	/* This operand can be ignored by matching process if it is not
	285	present. */
	286	#define ARC_OPERAND_IGNORE 0x0400
0d2bcfaf	287
886a2506 NC	288	/* Don't check the range when matching. */
886a2506 NC	289	#define ARC_OPERAND_NCHK 0x0800
0d2bcfaf	290
886a2506 NC	291	/* Mark the braket possition. */
886a2506 NC	292	#define ARC_OPERAND_BRAKET 0x1000
252b5132	293
886a2506 NC	294	/* Mask for selecting the type for typecheck purposes. */
	295	#define ARC_OPERAND_TYPECHECK_MASK \
	296	(ARC_OPERAND_IR \| \
	297	ARC_OPERAND_LIMM \| ARC_OPERAND_SIGNED \| \
	298	ARC_OPERAND_UNSIGNED \| ARC_OPERAND_BRAKET)
252b5132	299
886a2506 NC	300	/* The flags structure. */
	301	struct arc_flag_operand
	302	{
	303	/* The flag name. */
	304	const char *name;
0d2bcfaf	305
886a2506 NC	306	/* The flag code. */
886a2506 NC	307	unsigned code;
252b5132	308
886a2506 NC	309	/* The number of bits in the operand. */
886a2506 NC	310	unsigned int bits;
252b5132	311
886a2506 NC	312	/* How far the operand is left shifted in the instruction. */
886a2506 NC	313	unsigned int shift;
252b5132	314
886a2506 NC	315	/* Available for disassembler. */
886a2506 NC	316	unsigned char favail;
84037f8c KD	317	};
84037f8c KD	318
886a2506 NC	319	/* The flag operands table. */
	320	extern const struct arc_flag_operand arc_flag_operands[];
	321	extern const unsigned arc_num_flag_operands;
0d2bcfaf	322
886a2506 NC	323	/* The flag's class structure. */
	324	struct arc_flag_class
	325	{
	326	/* Flag class. */
	327	flag_class_t class;
252b5132	328
886a2506 NC	329	/* List of valid flags (codes). */
	330	unsigned flags[256];
	331	};
252b5132	332
886a2506	333	extern const struct arc_flag_class arc_flag_classes[];
252b5132	334
886a2506 NC	335	/* Structure for special cases. */
	336	struct arc_flag_special
	337	{
	338	/* Name of special case instruction. */
	339	const char *name;
252b5132	340
886a2506 NC	341	/* List of flags applicable for special case instruction. */
	342	unsigned flags[32];
	343	};
252b5132	344
886a2506 NC	345	extern const struct arc_flag_special arc_flag_special_cases[];
	346	extern const unsigned arc_num_flag_special;
	347
	348	/* Relocation equivalence structure. */
	349	struct arc_reloc_equiv_tab
	350	{
	351	const char * name; /* String to lookup. */
	352	const char * mnemonic; /* Extra matching condition. */
24b368f8	353	unsigned flags[32]; /* Extra matching condition. */
886a2506 NC	354	signed int oldreloc; /* Old relocation. */
	355	signed int newreloc; /* New relocation. */
	356	};
252b5132	357
886a2506 NC	358	extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
886a2506 NC	359	extern const unsigned arc_num_equiv_tab;
252b5132	360
886a2506 NC	361	/* Structure for operand operations for pseudo/alias instructions. */
	362	struct arc_operand_operation
	363	{
	364	/* The index for operand from operand array. */
	365	unsigned operand_idx;
252b5132	366
886a2506 NC	367	/* Defines if it needs the operand inserted by the assembler or
	368	whether this operand comes from the pseudo instruction's
	369	operands. */
	370	unsigned char needs_insert;
252b5132	371
886a2506 NC	372	/* Count we have to add to the operand. Use negative number to
	373	subtract from the operand. Also use this number to add to 0 if
	374	the operand needs to be inserted (i.e. needs_insert == 1). */
	375	int count;
252b5132	376
886a2506 NC	377	/* Index of the operand to swap with. To be done AFTER applying
	378	inc_count. */
	379	unsigned swap_operand_idx;
252b5132 RH	380	};
252b5132 RH	381
886a2506 NC	382	/* Structure for pseudo/alias instructions. */
	383	struct arc_pseudo_insn
	384	{
	385	/* Mnemonic for pseudo/alias insn. */
	386	const char *mnemonic_p;
252b5132	387
886a2506 NC	388	/* Mnemonic for real instruction. */
886a2506 NC	389	const char *mnemonic_r;
252b5132	390
886a2506 NC	391	/* Flag that will have to be added (if any). */
886a2506 NC	392	const char *flag_r;
252b5132	393
886a2506 NC	394	/* Amount of operands. */
886a2506 NC	395	unsigned operand_cnt;
252b5132	396
886a2506 NC	397	/* Array of operand operations. */
	398	struct arc_operand_operation operand[6];
	399	};
252b5132	400
886a2506 NC	401	extern const struct arc_pseudo_insn arc_pseudo_insns[];
886a2506 NC	402	extern const unsigned arc_num_pseudo_insn;
252b5132	403
886a2506 NC	404	/* Structure for AUXILIARY registers. */
	405	struct arc_aux_reg
	406	{
	407	/* Register address. */
	408	int address;
252b5132	409
8ddf6b2a CZ	410	/* AUX register subclass. */
	411	insn_subclass_t subclass;
	412
	413	/* Register name. */
886a2506 NC	414	const char *name;
	415
	416	/* Size of the string. */
	417	size_t length;
	418	};
	419
	420	extern const struct arc_aux_reg arc_aux_regs[];
	421	extern const unsigned arc_num_aux_regs;
	422
4670103e CZ	423	extern const struct arc_opcode arc_relax_opcodes[];
	424	extern const unsigned arc_num_relax_opcodes;
	425
f2dd8838 CZ	426	/* Macros to help generating regular pattern instructions. */
	427	#define FIELDA(word) (word & 0x3F)
	428	#define FIELDB(word) (((word & 0x07) << 24) \| (((word >> 3) & 0x07) << 12))
	429	#define FIELDC(word) ((word & 0x3F) << 6)
	430	#define FIELDF (0x01 << 15)
	431	#define FIELDQ (0x1F)
	432
	433	#define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) \| ((SOP & 0x3F) << 16))
	434	#define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) \| (SOP2 & 0x3F))
	435	#define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP))
	436
	437	#define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP))
	438	#define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) \| FIELDB (62))
	439	#define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) \| FIELDC (62))
	440	#define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) \| FIELDB (62) \| FIELDC (62))
	441	#define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) \| FIELDA (62))
	442	#define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) \| FIELDA (62) \| FIELDB (62))
	443	#define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) \| FIELDA (62) \| FIELDC (62))
	444	#define INSN3OP_0LL(MOP,SOP) \
	445	(INSN3OP (MOP,SOP) \| FIELDA (62) \| FIELDB (62) \| FIELDC (62))
	446	#define INSN3OP_ABU(MOP,SOP) (INSN3OP (MOP,SOP) \| (0x01 << 22))
	447	#define INSN3OP_ALU(MOP,SOP) (INSN3OP (MOP,SOP) \| (0x01 << 22) \| FIELDB (62))
	448	#define INSN3OP_0BU(MOP,SOP) (INSN3OP (MOP,SOP) \| FIELDA (62) \| (0x01 << 22))
	449	#define INSN3OP_0LU(MOP,SOP) \
	450	(INSN3OP (MOP,SOP) \| FIELDA (62) \| (0x01 << 22) \| FIELDB (62))
	451	#define INSN3OP_BBS(MOP,SOP) (INSN3OP (MOP,SOP) \| (0x02 << 22))
	452	#define INSN3OP_0LS(MOP,SOP) (INSN3OP (MOP,SOP) \| (0x02 << 22) \| FIELDB (62))
	453	#define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) \| (0x03 << 22))
	454	#define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) \| (0x03 << 22) \| FIELDC (62))
	455	#define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) \| (0x03 << 22) \| FIELDB (62))
	456	#define INSN3OP_C0LL(MOP,SOP) \
	457	(INSN3OP (MOP,SOP) \| (0x03 << 22) \| FIELDC (62) \| FIELDB (62))
	458	#define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) \| (0x03 << 22) \| (0x01 << 5))
	459	#define INSN3OP_C0LU(MOP,SOP) \
	460	(INSN3OP (MOP,SOP) \| (0x03 << 22) \| (0x01 << 5) \| FIELDB (62))
	461
	462	#define MINSN3OP_ABC (~(FIELDF \| FIELDA (63) \| FIELDB (63) \| FIELDC (63)))
	463	#define MINSN3OP_ALC (~(FIELDF \| FIELDA (63) \| FIELDC (63)))
	464	#define MINSN3OP_ABL (~(FIELDF \| FIELDA (63) \| FIELDB (63)))
	465	#define MINSN3OP_ALL (~(FIELDF \| FIELDA (63)))
	466	#define MINSN3OP_0BC (~(FIELDF \| FIELDB (63) \| FIELDC (63)))
	467	#define MINSN3OP_0LC (~(FIELDF \| FIELDC (63)))
	468	#define MINSN3OP_0BL (~(FIELDF \| FIELDB (63)))
	469	#define MINSN3OP_0LL (~(FIELDF))
	470	#define MINSN3OP_ABU (~(FIELDF \| FIELDA (63) \| FIELDB (63) \| FIELDC (63)))
	471	#define MINSN3OP_ALU (~(FIELDF \| FIELDA (63) \| FIELDC (63)))
	472	#define MINSN3OP_0BU (~(FIELDF \| FIELDB (63) \| FIELDC (63)))
	473	#define MINSN3OP_0LU (~(FIELDF \| FIELDC (63)))
	474	#define MINSN3OP_BBS (~(FIELDF \| FIELDA (63) \| FIELDB (63) \| FIELDC (63)))
	475	#define MINSN3OP_0LS (~(FIELDF \| FIELDA (63) \| FIELDC (63)))
	476	#define MINSN3OP_CBBC (~(FIELDF \| FIELDQ \| FIELDB (63) \| FIELDC (63)))
	477	#define MINSN3OP_CBBL (~(FIELDF \| FIELDQ \| FIELDB (63)))
	478	#define MINSN3OP_C0LC (~(FIELDF \| FIELDQ \| FIELDC (63)))
	479	#define MINSN3OP_C0LL (~(FIELDF \| FIELDQ))
	480	#define MINSN3OP_CBBU (~(FIELDF \| FIELDQ \| FIELDB (63) \| FIELDC (63)))
	481	#define MINSN3OP_C0LU (~(FIELDF \| FIELDQ \| FIELDC (63)))
	482
	483	#define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
	484	#define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) \| FIELDC (62))
	485	#define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) \| FIELDB (62))
	486	#define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) \| FIELDB (62) \| FIELDC (62))
	487	#define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) \| (0x01 << 22))
	488	#define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) \| (0x01 << 22) \| FIELDB (62))
	489
490	#define MINSN2OP_BC (~(FIELDF \| FIELDB (63) \| FIELDC (63)))
491	#define MINSN2OP_BL (~(FIELDF \| FIELDB (63)))
492	#define MINSN2OP_0C (~(FIELDF \| FIELDC (63)))
493	#define MINSN2OP_0L (~(FIELDF))
494	#define MINSN2OP_BU (~(FIELDF \| FIELDB (63) \| FIELDC (63)))
495	#define MINSN2OP_0U (~(FIELDF \| FIELDC (63)))
496
886a2506	497	#endif /* OPCODE_ARC_H */