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Fix a bug displaying the interpretation of a CFA block that just contains DW_CFA_NOP...
[deliverable/binutils-gdb.git] / include / opcode / arc.h
CommitLineData
252b5132 1/* Opcode table for the ARC.
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
252b5132 5
0d2bcfaf
NC		 6 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
7 the GNU Binutils.
252b5132 8
0d2bcfaf
NC		 9 GAS/GDB is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
e4e42b45 11 the Free Software Foundation; either version 3, or (at your option)
0d2bcfaf 12 any later version.
252b5132 13
0d2bcfaf
NC		 14 GAS/GDB is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
886a2506 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0d2bcfaf
NC		 17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
e4e42b45 20 along with GAS or GDB; see the file COPYING3. If not, write to
e172dbf8
NC		 21 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
252b5132 23
886a2506
NC		 24#ifndef OPCODE_ARC_H
25#define OPCODE_ARC_H
26
4670103e 27#ifndef MAX_INSN_ARGS
537aefaf 28#define MAX_INSN_ARGS 8
4670103e
CZ		 29#endif
30
31#ifndef MAX_INSN_FLGS
886a2506 32#define MAX_INSN_FLGS 3
4670103e 33#endif
886a2506
NC		 34
35/* Instruction Class. */
36typedef enum
37 {
38 ARITH,
39 AUXREG,
40 BRANCH,
41 CONTROL,
42 DSP,
43 FLOAT,
44 INVALID,
45 JUMP,
46 KERNEL,
47 LOGICAL,
48 MEMORY,
e23e8ebe 49 BITOP,
c8f785f2
AB		 50 NET,
51 ACL,
886a2506
NC		 52 } insn_class_t;
53
54/* Instruction Subclass. */
55typedef enum
56 {
57 NONE,
58 CVT,
59 BTSCN,
60 CD1,
61 CD2,
d9eca1df 62 COND,
886a2506
NC		 63 DIV,
64 DP,
8ddf6b2a
CZ		 65 DPA,
66 DPX,
886a2506
NC		 67 MPY1E,
68 MPY6E,
69 MPY7E,
70 MPY8E,
71 MPY9E,
f2dd8838 72 QUARKSE,
886a2506
NC		 73 SHFT1,
74 SHFT2,
75 SWAP,
8ddf6b2a
CZ		 76 SP,
77 SPX
886a2506
NC		 78 } insn_subclass_t;
79
80/* Flags class. */
81typedef enum
82 {
f36e33da 83 F_CLASS_NONE = 0,
1ae8ab47
AB		 84
85 /* At most one flag from the set of flags can appear in the
86 instruction. */
f36e33da 87 F_CLASS_OPTIONAL = (1 << 0),
1ae8ab47
AB		 88
89 /* Exactly one from from the set of flags must appear in the
90 instruction. */
f36e33da
CZ		 91 F_CLASS_REQUIRED = (1 << 1),
92
93 /* The conditional code can be extended over the standard variants
94 via .extCondCode pseudo-op. */
d9eca1df
CZ		 95 F_CLASS_EXTEND = (1 << 2),
96
97 /* Condition code flag. */
98 F_CLASS_COND = (1 << 3)
886a2506
NC		 99 } flag_class_t;
100
101/* The opcode table is an array of struct arc_opcode. */
102struct arc_opcode
103{
104 /* The opcode name. */
105 const char *name;
106
107 /* The opcode itself. Those bits which will be filled in with
108 operands are zeroes. */
109 unsigned opcode;
110
111 /* The opcode mask. This is used by the disassembler. This is a
112 mask containing ones indicating those bits which must match the
113 opcode field, and zeroes indicating those bits which need not
114 match (and are presumably filled in by operands). */
115 unsigned mask;
116
117 /* One bit flags for the opcode. These are primarily used to
118 indicate specific processors and environments support the
119 instructions. The defined values are listed below. */
120 unsigned cpu;
121
122 /* The instruction class. This is used by gdb. */
c810e0b8 123 insn_class_t insn_class;
886a2506
NC		 124
125 /* The instruction subclass. */
126 insn_subclass_t subclass;
127
128 /* An array of operand codes. Each code is an index into the
129 operand table. They appear in the order which the operands must
130 appear in assembly code, and are terminated by a zero. */
131 unsigned char operands[MAX_INSN_ARGS + 1];
132
133 /* An array of flag codes. Each code is an index into the flag
134 table. They appear in the order which the flags must appear in
135 assembly code, and are terminated by a zero. */
136 unsigned char flags[MAX_INSN_FLGS + 1];
137};
252b5132 138
886a2506
NC		 139/* The table itself is sorted by major opcode number, and is otherwise
140 in the order in which the disassembler should consider
141 instructions. */
142extern const struct arc_opcode arc_opcodes[];
886a2506
NC		 143
144/* CPU Availability. */
f36e33da 145#define ARC_OPCODE_NONE 0x0000
886a2506
NC		 146#define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
147#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
148#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
149#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
8699fc3e 150#define ARC_OPCODE_NPS400 0x0010 /* NPS400 specific insns. */
886a2506 151
f36e33da
CZ		 152/* CPU combi. */
153#define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
154 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
155#define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
156
886a2506
NC		 157/* CPU extensions. */
158#define ARC_EA 0x0001
159#define ARC_CD 0x0001 /* Mutual exclusive with EA. */
160#define ARC_LLOCK 0x0002
161#define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */
162#define ARC_MPY 0x0004
163#define ARC_MULT 0x0004
164
165/* Floating point support. */
166#define ARC_DPFP 0x0010
167#define ARC_SPFP 0x0020
168#define ARC_FPU 0x0030
8ddf6b2a 169#define ARC_FPUDA 0x0040
886a2506
NC		 170
171/* NORM & SWAP. */
172#define ARC_SWAP 0x0100
173#define ARC_NORM 0x0200
174#define ARC_BSCAN 0x0200
175
176/* A7 specific. */
177#define ARC_UIX 0x1000
178#define ARC_TSTAMP 0x1000
179
180/* A6 specific. */
181#define ARC_VBFDW 0x1000
182#define ARC_BARREL 0x1000
183#define ARC_DSPA 0x1000
184
185/* EM specific. */
186#define ARC_SHIFT 0x1000
187
188/* V2 specific. */
189#define ARC_INTR 0x1000
190#define ARC_DIV 0x1000
191
192/* V1 specific. */
193#define ARC_XMAC 0x1000
194#define ARC_CRC 0x1000
195
886a2506
NC		 196/* A macro to check for short instructions. */
197#define ARC_SHORT(mask) \
198 (((mask) & 0xFFFF0000) ? 0 : 1)
199
200/* The operands table is an array of struct arc_operand. */
201struct arc_operand
202{
203 /* The number of bits in the operand. */
204 unsigned int bits;
205
206 /* How far the operand is left shifted in the instruction. */
207 unsigned int shift;
208
209 /* The default relocation type for this operand. */
210 signed int default_reloc;
211
212 /* One bit syntax flags. */
213 unsigned int flags;
214
215 /* Insertion function. This is used by the assembler. To insert an
216 operand value into an instruction, check this field.
217
218 If it is NULL, execute
219 i |= (op & ((1 << o->bits) - 1)) << o->shift;
220 (i is the instruction which we are filling in, o is a pointer to
221 this structure, and op is the opcode value; this assumes twos
222 complement arithmetic).
223
224 If this field is not NULL, then simply call it with the
225 instruction and the operand value. It will return the new value
226 of the instruction. If the ERRMSG argument is not NULL, then if
227 the operand value is illegal, *ERRMSG will be set to a warning
228 string (the operand will be inserted in any case). If the
229 operand value is legal, *ERRMSG will be unchanged (most operands
230 can accept any value). */
231 unsigned (*insert) (unsigned instruction, int op, const char **errmsg);
232
233 /* Extraction function. This is used by the disassembler. To
234 extract this operand type from an instruction, check this field.
235
236 If it is NULL, compute
237 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
238 if ((o->flags & ARC_OPERAND_SIGNED) != 0
239 && (op & (1 << (o->bits - 1))) != 0)
240 op -= 1 << o->bits;
241 (i is the instruction, o is a pointer to this structure, and op
242 is the result; this assumes twos complement arithmetic).
243
244 If this field is not NULL, then simply call it with the
245 instruction value. It will return the value of the operand. If
246 the INVALID argument is not NULL, *INVALID will be set to
247 TRUE if this operand type can not actually be extracted from
248 this operand (i.e., the instruction does not match). If the
249 operand is valid, *INVALID will not be changed. */
250 int (*extract) (unsigned instruction, bfd_boolean *invalid);
251};
0d2bcfaf 252
886a2506
NC		 253/* Elements in the table are retrieved by indexing with values from
254 the operands field of the arc_opcodes table. */
255extern const struct arc_operand arc_operands[];
256extern const unsigned arc_num_operands;
257extern const unsigned arc_Toperand;
258extern const unsigned arc_NToperand;
252b5132 259
886a2506 260/* Values defined for the flags field of a struct arc_operand. */
0d2bcfaf 261
886a2506
NC		 262/* This operand does not actually exist in the assembler input. This
263 is used to support extended mnemonics, for which two operands fields
264 are identical. The assembler should call the insert function with
265 any op value. The disassembler should call the extract function,
266 ignore the return value, and check the value placed in the invalid
267 argument. */
268#define ARC_OPERAND_FAKE 0x0001
252b5132 269
886a2506
NC		 270/* This operand names an integer register. */
271#define ARC_OPERAND_IR 0x0002
0d2bcfaf 272
886a2506
NC		 273/* This operand takes signed values. */
274#define ARC_OPERAND_SIGNED 0x0004
252b5132 275
886a2506
NC		 276/* This operand takes unsigned values. This exists primarily so that
277 a flags value of 0 can be treated as end-of-arguments. */
278#define ARC_OPERAND_UNSIGNED 0x0008
252b5132 279
886a2506
NC		 280/* This operand takes long immediate values. */
281#define ARC_OPERAND_LIMM 0x0010
252b5132 282
886a2506
NC		 283/* This operand is identical like the previous one. */
284#define ARC_OPERAND_DUPLICATE 0x0020
0d2bcfaf 285
886a2506
NC		 286/* This operand is PC relative. Used for internal relocs. */
287#define ARC_OPERAND_PCREL 0x0040
0d2bcfaf 288
886a2506
NC		 289/* This operand is truncated. The truncation is done accordingly to
290 operand alignment attribute. */
291#define ARC_OPERAND_TRUNCATE 0x0080
0d2bcfaf 292
886a2506
NC		 293/* This operand is 16bit aligned. */
294#define ARC_OPERAND_ALIGNED16 0x0100
0d2bcfaf 295
886a2506
NC		 296/* This operand is 32bit aligned. */
297#define ARC_OPERAND_ALIGNED32 0x0200
0d2bcfaf 298
886a2506
NC		 299/* This operand can be ignored by matching process if it is not
300 present. */
301#define ARC_OPERAND_IGNORE 0x0400
0d2bcfaf 302
886a2506
NC		 303/* Don't check the range when matching. */
304#define ARC_OPERAND_NCHK 0x0800
0d2bcfaf 305
886a2506
NC		 306/* Mark the braket possition. */
307#define ARC_OPERAND_BRAKET 0x1000
252b5132 308
886a2506
NC		 309/* Mask for selecting the type for typecheck purposes. */
310#define ARC_OPERAND_TYPECHECK_MASK \
311 (ARC_OPERAND_IR | \
312 ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | \
313 ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET)
252b5132 314
886a2506
NC		 315/* The flags structure. */
316struct arc_flag_operand
317{
318 /* The flag name. */
319 const char *name;
0d2bcfaf 320
886a2506
NC		 321 /* The flag code. */
322 unsigned code;
252b5132 323
886a2506
NC		 324 /* The number of bits in the operand. */
325 unsigned int bits;
252b5132 326
886a2506
NC		 327 /* How far the operand is left shifted in the instruction. */
328 unsigned int shift;
252b5132 329
886a2506
NC		 330 /* Available for disassembler. */
331 unsigned char favail;
84037f8c
KD		 332};
333
886a2506
NC		 334/* The flag operands table. */
335extern const struct arc_flag_operand arc_flag_operands[];
336extern const unsigned arc_num_flag_operands;
0d2bcfaf 337
886a2506
NC		 338/* The flag's class structure. */
339struct arc_flag_class
340{
341 /* Flag class. */
c810e0b8 342 flag_class_t flag_class;
252b5132 343
886a2506
NC		 344 /* List of valid flags (codes). */
345 unsigned flags[256];
346};
252b5132 347
886a2506 348extern const struct arc_flag_class arc_flag_classes[];
252b5132 349
886a2506
NC		 350/* Structure for special cases. */
351struct arc_flag_special
352{
353 /* Name of special case instruction. */
354 const char *name;
252b5132 355
886a2506
NC		 356 /* List of flags applicable for special case instruction. */
357 unsigned flags[32];
358};
252b5132 359
886a2506
NC		 360extern const struct arc_flag_special arc_flag_special_cases[];
361extern const unsigned arc_num_flag_special;
362
363/* Relocation equivalence structure. */
364struct arc_reloc_equiv_tab
365{
366 const char * name; /* String to lookup. */
367 const char * mnemonic; /* Extra matching condition. */
24b368f8 368 unsigned flags[32]; /* Extra matching condition. */
886a2506
NC		 369 signed int oldreloc; /* Old relocation. */
370 signed int newreloc; /* New relocation. */
371};
252b5132 372
886a2506
NC		 373extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
374extern const unsigned arc_num_equiv_tab;
252b5132 375
886a2506
NC		 376/* Structure for operand operations for pseudo/alias instructions. */
377struct arc_operand_operation
378{
379 /* The index for operand from operand array. */
380 unsigned operand_idx;
252b5132 381
886a2506
NC		 382 /* Defines if it needs the operand inserted by the assembler or
383 whether this operand comes from the pseudo instruction's
384 operands. */
385 unsigned char needs_insert;
252b5132 386
886a2506
NC		 387 /* Count we have to add to the operand. Use negative number to
388 subtract from the operand. Also use this number to add to 0 if
389 the operand needs to be inserted (i.e. needs_insert == 1). */
390 int count;
252b5132 391
886a2506
NC		 392 /* Index of the operand to swap with. To be done AFTER applying
393 inc_count. */
394 unsigned swap_operand_idx;
252b5132
RH		 395};
396
886a2506
NC		 397/* Structure for pseudo/alias instructions. */
398struct arc_pseudo_insn
399{
400 /* Mnemonic for pseudo/alias insn. */
401 const char *mnemonic_p;
252b5132 402
886a2506
NC		 403 /* Mnemonic for real instruction. */
404 const char *mnemonic_r;
252b5132 405
886a2506
NC		 406 /* Flag that will have to be added (if any). */
407 const char *flag_r;
252b5132 408
886a2506
NC		 409 /* Amount of operands. */
410 unsigned operand_cnt;
252b5132 411
886a2506
NC		 412 /* Array of operand operations. */
413 struct arc_operand_operation operand[6];
414};
252b5132 415
886a2506
NC		 416extern const struct arc_pseudo_insn arc_pseudo_insns[];
417extern const unsigned arc_num_pseudo_insn;
252b5132 418
886a2506
NC		 419/* Structure for AUXILIARY registers. */
420struct arc_aux_reg
421{
422 /* Register address. */
423 int address;
252b5132 424
f36e33da
CZ		 425 /* One bit flags for the opcode. These are primarily used to
426 indicate specific processors and environments support the
427 instructions. */
428 unsigned cpu;
429
8ddf6b2a
CZ		 430 /* AUX register subclass. */
431 insn_subclass_t subclass;
432
433 /* Register name. */
886a2506
NC		 434 const char *name;
435
436 /* Size of the string. */
437 size_t length;
438};
439
440extern const struct arc_aux_reg arc_aux_regs[];
441extern const unsigned arc_num_aux_regs;
442
4670103e
CZ		 443extern const struct arc_opcode arc_relax_opcodes[];
444extern const unsigned arc_num_relax_opcodes;
445
4b0c052e
AB		 446/* Macro used for generating one class of NPS instructions. */
447#define NPS_CMEM_HIGH_VALUE 0x57f0
448
f2dd8838
CZ		 449/* Macros to help generating regular pattern instructions. */
450#define FIELDA(word) (word & 0x3F)
451#define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
452#define FIELDC(word) ((word & 0x3F) << 6)
453#define FIELDF (0x01 << 15)
454#define FIELDQ (0x1F)
455
456#define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
457#define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
458#define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP))
459
460#define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP))
461#define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62))
462#define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (62))
463#define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
464#define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62))
465#define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
466#define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
467#define INSN3OP_0LL(MOP,SOP) \
468 (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
469#define INSN3OP_ABU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22))
470#define INSN3OP_ALU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
471#define INSN3OP_0BU(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
472#define INSN3OP_0LU(MOP,SOP) \
473 (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
474#define INSN3OP_BBS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22))
475#define INSN3OP_0LS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
476#define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
477#define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
478#define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
479#define INSN3OP_C0LL(MOP,SOP) \
480 (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
481#define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
482#define INSN3OP_C0LU(MOP,SOP) \
483 (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
484
485#define MINSN3OP_ABC (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
486#define MINSN3OP_ALC (~(FIELDF | FIELDA (63) | FIELDC (63)))
487#define MINSN3OP_ABL (~(FIELDF | FIELDA (63) | FIELDB (63)))
488#define MINSN3OP_ALL (~(FIELDF | FIELDA (63)))
489#define MINSN3OP_0BC (~(FIELDF | FIELDB (63) | FIELDC (63)))
490#define MINSN3OP_0LC (~(FIELDF | FIELDC (63)))
491#define MINSN3OP_0BL (~(FIELDF | FIELDB (63)))
492#define MINSN3OP_0LL (~(FIELDF))
493#define MINSN3OP_ABU (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
494#define MINSN3OP_ALU (~(FIELDF | FIELDA (63) | FIELDC (63)))
495#define MINSN3OP_0BU (~(FIELDF | FIELDB (63) | FIELDC (63)))
496#define MINSN3OP_0LU (~(FIELDF | FIELDC (63)))
497#define MINSN3OP_BBS (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
498#define MINSN3OP_0LS (~(FIELDF | FIELDA (63) | FIELDC (63)))
499#define MINSN3OP_CBBC (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
500#define MINSN3OP_CBBL (~(FIELDF | FIELDQ | FIELDB (63)))
501#define MINSN3OP_C0LC (~(FIELDF | FIELDQ | FIELDC (63)))
502#define MINSN3OP_C0LL (~(FIELDF | FIELDQ))
503#define MINSN3OP_CBBU (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
504#define MINSN3OP_C0LU (~(FIELDF | FIELDQ | FIELDC (63)))
505
506#define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
507#define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
508#define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
509#define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
510#define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
511#define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
512
513#define MINSN2OP_BC (~(FIELDF | FIELDB (63) | FIELDC (63)))
514#define MINSN2OP_BL (~(FIELDF | FIELDB (63)))
515#define MINSN2OP_0C (~(FIELDF | FIELDC (63)))
516#define MINSN2OP_0L (~(FIELDF))
517#define MINSN2OP_BU (~(FIELDF | FIELDB (63) | FIELDC (63)))
518#define MINSN2OP_0U (~(FIELDF | FIELDC (63)))
519
b99747ae
CZ		 520/* Various constants used when defining an extension instruction. */
521#define ARC_SYNTAX_3OP (1 << 0)
522#define ARC_SYNTAX_2OP (1 << 1)
945e0f82
CZ		 523#define ARC_SYNTAX_1OP (1 << 2)
524#define ARC_SYNTAX_NOP (1 << 3)
525#define ARC_SYNTAX_MASK (0x0F)
526
527#define ARC_OP1_MUST_BE_IMM (1 << 0)
528#define ARC_OP1_IMM_IMPLIED (1 << 1)
b99747ae
CZ		 529
530#define ARC_SUFFIX_NONE (1 << 0)
531#define ARC_SUFFIX_COND (1 << 1)
532#define ARC_SUFFIX_FLAG (1 << 2)
533
f36e33da
CZ		 534#define ARC_REGISTER_READONLY (1 << 0)
535#define ARC_REGISTER_WRITEONLY (1 << 1)
536#define ARC_REGISTER_NOSHORT_CUT (1 << 2)
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CZ		 537
538/* Constants needed to initialize extension instructions. */
539extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
540extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
541extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
542extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
543
544extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
545extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
546extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
547extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
548extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
549extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
550extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
551extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
552extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
553extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
554extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
555extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
556
557extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
558extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
559extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
560
561extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
562extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
563extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
564
565extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
566extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
567extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
568extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
569extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
570extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
571
572extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
573extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
574extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
575extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
576
945e0f82
CZ		 577extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
578extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
579extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
580
886a2506 581#endif /* OPCODE_ARC_H */
GDB Binutils - Deliverables
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