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[deliverable/binutils-gdb.git] / include / opcode / arc.h
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252b5132 1/* Opcode table for the ARC.
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
252b5132 5
0d2bcfaf
NC		 6 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
7 the GNU Binutils.
252b5132 8
0d2bcfaf
NC		 9 GAS/GDB is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
e4e42b45 11 the Free Software Foundation; either version 3, or (at your option)
0d2bcfaf 12 any later version.
252b5132 13
0d2bcfaf
NC		 14 GAS/GDB is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
886a2506 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0d2bcfaf
NC		 17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
e4e42b45 20 along with GAS or GDB; see the file COPYING3. If not, write to
e172dbf8
NC		 21 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
252b5132 23
886a2506
NC		 24#ifndef OPCODE_ARC_H
25#define OPCODE_ARC_H
26
6b477896
TS		 27#ifdef __cplusplus
28extern "C" {
29#endif
30
4670103e 31#ifndef MAX_INSN_ARGS
4eb6f892 32#define MAX_INSN_ARGS 16
4670103e
CZ		 33#endif
34
35#ifndef MAX_INSN_FLGS
886a2506 36#define MAX_INSN_FLGS 3
4670103e 37#endif
886a2506
NC		 38
39/* Instruction Class. */
40typedef enum
db18dbab
GM		 41{
42 ACL,
43 ARITH,
44 AUXREG,
45 BITOP,
2b848ebd 46 BITSTREAM,
db18dbab
GM		 47 BMU,
48 BRANCH,
49 CONTROL,
abe7c33b 50 DIVREM,
db18dbab
GM		 51 DPI,
52 DSP,
53 FLOAT,
54 INVALID,
55 JUMP,
56 KERNEL,
abe7c33b 57 LOAD,
db18dbab
GM		 58 LOGICAL,
59 MEMORY,
abe7c33b
CZ		 60 MOVE,
61 MPY,
db18dbab 62 NET,
5a736821 63 PROTOCOL_DECODE,
2b848ebd 64 PMU,
abe7c33b 65 STORE,
2b848ebd 66 XY
db18dbab 67} insn_class_t;
886a2506
NC		 68
69/* Instruction Subclass. */
70typedef enum
db18dbab
GM		 71{
72 NONE,
73 CVT,
74 BTSCN,
75 CD1,
76 CD2,
77 COND,
78 DIV,
79 DP,
80 DPA,
81 DPX,
82 MPY1E,
83 MPY6E,
84 MPY7E,
85 MPY8E,
86 MPY9E,
87 NPS400,
88 QUARKSE,
89 SHFT1,
90 SHFT2,
91 SWAP,
92 SP,
93 SPX
94} insn_subclass_t;
886a2506
NC		 95
96/* Flags class. */
97typedef enum
db18dbab
GM		 98{
99 F_CLASS_NONE = 0,
1ae8ab47 100
db18dbab
GM		 101 /* At most one flag from the set of flags can appear in the
102 instruction. */
103 F_CLASS_OPTIONAL = (1 << 0),
1ae8ab47 104
db18dbab
GM		 105 /* Exactly one from from the set of flags must appear in the
106 instruction. */
107 F_CLASS_REQUIRED = (1 << 1),
f36e33da 108
db18dbab
GM		 109 /* The conditional code can be extended over the standard variants
110 via .extCondCode pseudo-op. */
111 F_CLASS_EXTEND = (1 << 2),
d9eca1df 112
db18dbab
GM		 113 /* Condition code flag. */
114 F_CLASS_COND = (1 << 3)
115} flag_class_t;
886a2506
NC		 116
117/* The opcode table is an array of struct arc_opcode. */
118struct arc_opcode
119{
120 /* The opcode name. */
121 const char *name;
122
123 /* The opcode itself. Those bits which will be filled in with
124 operands are zeroes. */
bdfe53e3 125 unsigned long long opcode;
886a2506
NC		 126
127 /* The opcode mask. This is used by the disassembler. This is a
128 mask containing ones indicating those bits which must match the
129 opcode field, and zeroes indicating those bits which need not
130 match (and are presumably filled in by operands). */
bdfe53e3 131 unsigned long long mask;
886a2506
NC		 132
133 /* One bit flags for the opcode. These are primarily used to
134 indicate specific processors and environments support the
135 instructions. The defined values are listed below. */
136 unsigned cpu;
137
138 /* The instruction class. This is used by gdb. */
c810e0b8 139 insn_class_t insn_class;
886a2506
NC		 140
141 /* The instruction subclass. */
142 insn_subclass_t subclass;
143
144 /* An array of operand codes. Each code is an index into the
145 operand table. They appear in the order which the operands must
146 appear in assembly code, and are terminated by a zero. */
147 unsigned char operands[MAX_INSN_ARGS + 1];
148
149 /* An array of flag codes. Each code is an index into the flag
150 table. They appear in the order which the flags must appear in
151 assembly code, and are terminated by a zero. */
152 unsigned char flags[MAX_INSN_FLGS + 1];
153};
252b5132 154
886a2506
NC		 155/* The table itself is sorted by major opcode number, and is otherwise
156 in the order in which the disassembler should consider
157 instructions. */
158extern const struct arc_opcode arc_opcodes[];
886a2506 159
06fe285f
GM		 160/* Return length of an instruction represented by OPCODE, in bytes. */
161extern int arc_opcode_len (const struct arc_opcode *opcode);
162
886a2506 163/* CPU Availability. */
f36e33da 164#define ARC_OPCODE_NONE 0x0000
886a2506
NC		 165#define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
166#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
167#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
168#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
169
f36e33da
CZ		 170/* CPU combi. */
171#define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
172 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
173#define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
e5b06ef0 174#define ARC_OPCODE_ARCV2 (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
f36e33da 175
886a2506
NC		 176/* CPU extensions. */
177#define ARC_EA 0x0001
178#define ARC_CD 0x0001 /* Mutual exclusive with EA. */
179#define ARC_LLOCK 0x0002
180#define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */
181#define ARC_MPY 0x0004
182#define ARC_MULT 0x0004
bdd582db 183#define ARC_NPS400 0x0008
886a2506
NC		 184
185/* Floating point support. */
186#define ARC_DPFP 0x0010
187#define ARC_SPFP 0x0020
188#define ARC_FPU 0x0030
8ddf6b2a 189#define ARC_FPUDA 0x0040
886a2506
NC		 190
191/* NORM & SWAP. */
192#define ARC_SWAP 0x0100
193#define ARC_NORM 0x0200
194#define ARC_BSCAN 0x0200
195
196/* A7 specific. */
197#define ARC_UIX 0x1000
198#define ARC_TSTAMP 0x1000
199
200/* A6 specific. */
201#define ARC_VBFDW 0x1000
202#define ARC_BARREL 0x1000
203#define ARC_DSPA 0x1000
204
205/* EM specific. */
206#define ARC_SHIFT 0x1000
207
208/* V2 specific. */
209#define ARC_INTR 0x1000
210#define ARC_DIV 0x1000
211
212/* V1 specific. */
213#define ARC_XMAC 0x1000
214#define ARC_CRC 0x1000
215
886a2506
NC		 216/* The operands table is an array of struct arc_operand. */
217struct arc_operand
218{
219 /* The number of bits in the operand. */
220 unsigned int bits;
221
222 /* How far the operand is left shifted in the instruction. */
223 unsigned int shift;
224
225 /* The default relocation type for this operand. */
226 signed int default_reloc;
227
228 /* One bit syntax flags. */
229 unsigned int flags;
230
231 /* Insertion function. This is used by the assembler. To insert an
232 operand value into an instruction, check this field.
233
234 If it is NULL, execute
235 i |= (op & ((1 << o->bits) - 1)) << o->shift;
236 (i is the instruction which we are filling in, o is a pointer to
237 this structure, and op is the opcode value; this assumes twos
238 complement arithmetic).
239
240 If this field is not NULL, then simply call it with the
241 instruction and the operand value. It will return the new value
242 of the instruction. If the ERRMSG argument is not NULL, then if
243 the operand value is illegal, *ERRMSG will be set to a warning
244 string (the operand will be inserted in any case). If the
245 operand value is legal, *ERRMSG will be unchanged (most operands
246 can accept any value). */
bdfe53e3
AB		 247 unsigned long long (*insert) (unsigned long long instruction,
248 long long int op,
249 const char **errmsg);
886a2506
NC		 250
251 /* Extraction function. This is used by the disassembler. To
252 extract this operand type from an instruction, check this field.
253
254 If it is NULL, compute
255 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
256 if ((o->flags & ARC_OPERAND_SIGNED) != 0
257 && (op & (1 << (o->bits - 1))) != 0)
258 op -= 1 << o->bits;
259 (i is the instruction, o is a pointer to this structure, and op
260 is the result; this assumes twos complement arithmetic).
261
262 If this field is not NULL, then simply call it with the
263 instruction value. It will return the value of the operand. If
264 the INVALID argument is not NULL, *INVALID will be set to
265 TRUE if this operand type can not actually be extracted from
266 this operand (i.e., the instruction does not match). If the
267 operand is valid, *INVALID will not be changed. */
bdfe53e3
AB		 268 long long int (*extract) (unsigned long long instruction,
269 bfd_boolean *invalid);
886a2506 270};
0d2bcfaf 271
886a2506
NC		 272/* Elements in the table are retrieved by indexing with values from
273 the operands field of the arc_opcodes table. */
274extern const struct arc_operand arc_operands[];
275extern const unsigned arc_num_operands;
276extern const unsigned arc_Toperand;
277extern const unsigned arc_NToperand;
252b5132 278
886a2506 279/* Values defined for the flags field of a struct arc_operand. */
0d2bcfaf 280
886a2506
NC		 281/* This operand does not actually exist in the assembler input. This
282 is used to support extended mnemonics, for which two operands fields
283 are identical. The assembler should call the insert function with
284 any op value. The disassembler should call the extract function,
285 ignore the return value, and check the value placed in the invalid
286 argument. */
287#define ARC_OPERAND_FAKE 0x0001
252b5132 288
886a2506
NC		 289/* This operand names an integer register. */
290#define ARC_OPERAND_IR 0x0002
0d2bcfaf 291
886a2506
NC		 292/* This operand takes signed values. */
293#define ARC_OPERAND_SIGNED 0x0004
252b5132 294
886a2506
NC		 295/* This operand takes unsigned values. This exists primarily so that
296 a flags value of 0 can be treated as end-of-arguments. */
297#define ARC_OPERAND_UNSIGNED 0x0008
252b5132 298
886a2506
NC		 299/* This operand takes long immediate values. */
300#define ARC_OPERAND_LIMM 0x0010
252b5132 301
886a2506
NC		 302/* This operand is identical like the previous one. */
303#define ARC_OPERAND_DUPLICATE 0x0020
0d2bcfaf 304
886a2506
NC		 305/* This operand is PC relative. Used for internal relocs. */
306#define ARC_OPERAND_PCREL 0x0040
0d2bcfaf 307
886a2506
NC		 308/* This operand is truncated. The truncation is done accordingly to
309 operand alignment attribute. */
310#define ARC_OPERAND_TRUNCATE 0x0080
0d2bcfaf 311
886a2506
NC		 312/* This operand is 16bit aligned. */
313#define ARC_OPERAND_ALIGNED16 0x0100
0d2bcfaf 314
886a2506
NC		 315/* This operand is 32bit aligned. */
316#define ARC_OPERAND_ALIGNED32 0x0200
0d2bcfaf 317
886a2506
NC		 318/* This operand can be ignored by matching process if it is not
319 present. */
320#define ARC_OPERAND_IGNORE 0x0400
0d2bcfaf 321
886a2506
NC		 322/* Don't check the range when matching. */
323#define ARC_OPERAND_NCHK 0x0800
0d2bcfaf 324
886a2506
NC		 325/* Mark the braket possition. */
326#define ARC_OPERAND_BRAKET 0x1000
252b5132 327
db18dbab
GM		 328/* Address type operand for NPS400. */
329#define ARC_OPERAND_ADDRTYPE 0x2000
330
331/* Mark the colon position. */
332#define ARC_OPERAND_COLON 0x4000
333
886a2506 334/* Mask for selecting the type for typecheck purposes. */
db18dbab
GM		 335#define ARC_OPERAND_TYPECHECK_MASK \
336 (ARC_OPERAND_IR \
337 | ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED \
338 | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET \
339 | ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON)
340
341/* Macro to determine if an operand is a fake operand. */
342#define ARC_OPERAND_IS_FAKE(op) \
343 ((operand->flags & ARC_OPERAND_FAKE) \
344 && !((operand->flags & ARC_OPERAND_BRAKET) \
345 || (operand->flags & ARC_OPERAND_COLON)))
252b5132 346
886a2506
NC		 347/* The flags structure. */
348struct arc_flag_operand
349{
350 /* The flag name. */
351 const char *name;
0d2bcfaf 352
886a2506
NC		 353 /* The flag code. */
354 unsigned code;
252b5132 355
886a2506
NC		 356 /* The number of bits in the operand. */
357 unsigned int bits;
252b5132 358
886a2506
NC		 359 /* How far the operand is left shifted in the instruction. */
360 unsigned int shift;
252b5132 361
886a2506
NC		 362 /* Available for disassembler. */
363 unsigned char favail;
84037f8c
KD		 364};
365
886a2506
NC		 366/* The flag operands table. */
367extern const struct arc_flag_operand arc_flag_operands[];
368extern const unsigned arc_num_flag_operands;
0d2bcfaf 369
886a2506
NC		 370/* The flag's class structure. */
371struct arc_flag_class
372{
373 /* Flag class. */
c810e0b8 374 flag_class_t flag_class;
252b5132 375
886a2506
NC		 376 /* List of valid flags (codes). */
377 unsigned flags[256];
378};
252b5132 379
886a2506 380extern const struct arc_flag_class arc_flag_classes[];
252b5132 381
886a2506
NC		 382/* Structure for special cases. */
383struct arc_flag_special
384{
385 /* Name of special case instruction. */
386 const char *name;
252b5132 387
886a2506
NC		 388 /* List of flags applicable for special case instruction. */
389 unsigned flags[32];
390};
252b5132 391
886a2506
NC		 392extern const struct arc_flag_special arc_flag_special_cases[];
393extern const unsigned arc_num_flag_special;
394
395/* Relocation equivalence structure. */
396struct arc_reloc_equiv_tab
397{
398 const char * name; /* String to lookup. */
399 const char * mnemonic; /* Extra matching condition. */
24b368f8 400 unsigned flags[32]; /* Extra matching condition. */
886a2506
NC		 401 signed int oldreloc; /* Old relocation. */
402 signed int newreloc; /* New relocation. */
403};
252b5132 404
886a2506
NC		 405extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
406extern const unsigned arc_num_equiv_tab;
252b5132 407
886a2506
NC		 408/* Structure for operand operations for pseudo/alias instructions. */
409struct arc_operand_operation
410{
411 /* The index for operand from operand array. */
412 unsigned operand_idx;
252b5132 413
886a2506
NC		 414 /* Defines if it needs the operand inserted by the assembler or
415 whether this operand comes from the pseudo instruction's
416 operands. */
417 unsigned char needs_insert;
252b5132 418
886a2506
NC		 419 /* Count we have to add to the operand. Use negative number to
420 subtract from the operand. Also use this number to add to 0 if
421 the operand needs to be inserted (i.e. needs_insert == 1). */
422 int count;
252b5132 423
886a2506
NC		 424 /* Index of the operand to swap with. To be done AFTER applying
425 inc_count. */
426 unsigned swap_operand_idx;
252b5132
RH		 427};
428
886a2506
NC		 429/* Structure for pseudo/alias instructions. */
430struct arc_pseudo_insn
431{
432 /* Mnemonic for pseudo/alias insn. */
433 const char *mnemonic_p;
252b5132 434
886a2506
NC		 435 /* Mnemonic for real instruction. */
436 const char *mnemonic_r;
252b5132 437
886a2506
NC		 438 /* Flag that will have to be added (if any). */
439 const char *flag_r;
252b5132 440
886a2506
NC		 441 /* Amount of operands. */
442 unsigned operand_cnt;
252b5132 443
886a2506
NC		 444 /* Array of operand operations. */
445 struct arc_operand_operation operand[6];
446};
252b5132 447
886a2506
NC		 448extern const struct arc_pseudo_insn arc_pseudo_insns[];
449extern const unsigned arc_num_pseudo_insn;
252b5132 450
886a2506
NC		 451/* Structure for AUXILIARY registers. */
452struct arc_aux_reg
453{
454 /* Register address. */
455 int address;
252b5132 456
f36e33da
CZ		 457 /* One bit flags for the opcode. These are primarily used to
458 indicate specific processors and environments support the
459 instructions. */
460 unsigned cpu;
461
8ddf6b2a
CZ		 462 /* AUX register subclass. */
463 insn_subclass_t subclass;
464
465 /* Register name. */
886a2506
NC		 466 const char *name;
467
468 /* Size of the string. */
469 size_t length;
470};
471
472extern const struct arc_aux_reg arc_aux_regs[];
473extern const unsigned arc_num_aux_regs;
474
4670103e
CZ		 475extern const struct arc_opcode arc_relax_opcodes[];
476extern const unsigned arc_num_relax_opcodes;
477
4b0c052e
AB		 478/* Macro used for generating one class of NPS instructions. */
479#define NPS_CMEM_HIGH_VALUE 0x57f0
480
f2dd8838
CZ		 481/* Macros to help generating regular pattern instructions. */
482#define FIELDA(word) (word & 0x3F)
483#define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
484#define FIELDC(word) ((word & 0x3F) << 6)
485#define FIELDF (0x01 << 15)
486#define FIELDQ (0x1F)
487
488#define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
489#define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
490#define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP))
491
492#define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP))
493#define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62))
494#define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (62))
495#define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
496#define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62))
497#define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
498#define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
499#define INSN3OP_0LL(MOP,SOP) \
500 (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
501#define INSN3OP_ABU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22))
502#define INSN3OP_ALU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
503#define INSN3OP_0BU(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
504#define INSN3OP_0LU(MOP,SOP) \
505 (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
506#define INSN3OP_BBS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22))
507#define INSN3OP_0LS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
508#define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
509#define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
510#define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
511#define INSN3OP_C0LL(MOP,SOP) \
512 (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
513#define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
514#define INSN3OP_C0LU(MOP,SOP) \
515 (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
516
2e272202
GM		 517#define MASK_32BIT(VAL) (0xffffffff & (VAL))
518
519#define MINSN3OP_ABC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
520#define MINSN3OP_ALC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
521#define MINSN3OP_ABL (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63))))
522#define MINSN3OP_ALL (MASK_32BIT (~(FIELDF | FIELDA (63))))
523#define MINSN3OP_0BC (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
524#define MINSN3OP_0LC (MASK_32BIT (~(FIELDF | FIELDC (63))))
525#define MINSN3OP_0BL (MASK_32BIT (~(FIELDF | FIELDB (63))))
526#define MINSN3OP_0LL (MASK_32BIT (~(FIELDF)))
527#define MINSN3OP_ABU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
528#define MINSN3OP_ALU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
529#define MINSN3OP_0BU (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
530#define MINSN3OP_0LU (MASK_32BIT (~(FIELDF | FIELDC (63))))
531#define MINSN3OP_BBS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
532#define MINSN3OP_0LS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
533#define MINSN3OP_CBBC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
534#define MINSN3OP_CBBL (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63))))
535#define MINSN3OP_C0LC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
536#define MINSN3OP_C0LL (MASK_32BIT (~(FIELDF | FIELDQ)))
537#define MINSN3OP_CBBU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
538#define MINSN3OP_C0LU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
f2dd8838
CZ		 539
540#define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
541#define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
542#define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
543#define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
544#define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
545#define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
546
2e272202
GM		 547#define MINSN2OP_BC (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
548#define MINSN2OP_BL (MASK_32BIT ((~(FIELDF | FIELDB (63)))))
549#define MINSN2OP_0C (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
550#define MINSN2OP_0L (MASK_32BIT ((~(FIELDF))))
551#define MINSN2OP_BU (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
552#define MINSN2OP_0U (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
f2dd8838 553
b99747ae
CZ		 554/* Various constants used when defining an extension instruction. */
555#define ARC_SYNTAX_3OP (1 << 0)
556#define ARC_SYNTAX_2OP (1 << 1)
945e0f82
CZ		 557#define ARC_SYNTAX_1OP (1 << 2)
558#define ARC_SYNTAX_NOP (1 << 3)
559#define ARC_SYNTAX_MASK (0x0F)
560
561#define ARC_OP1_MUST_BE_IMM (1 << 0)
562#define ARC_OP1_IMM_IMPLIED (1 << 1)
b99747ae
CZ		 563
564#define ARC_SUFFIX_NONE (1 << 0)
565#define ARC_SUFFIX_COND (1 << 1)
566#define ARC_SUFFIX_FLAG (1 << 2)
567
f36e33da
CZ		 568#define ARC_REGISTER_READONLY (1 << 0)
569#define ARC_REGISTER_WRITEONLY (1 << 1)
570#define ARC_REGISTER_NOSHORT_CUT (1 << 2)
b99747ae
CZ		 571
572/* Constants needed to initialize extension instructions. */
573extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
574extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
575extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
576extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
577
578extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
579extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
580extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
581extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
582extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
583extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
584extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
585extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
586extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
587extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
588extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
589extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
590
591extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
592extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
593extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
594
595extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
596extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
597extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
598
599extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
600extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
601extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
602extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
603extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
604extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
605
606extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
607extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
608extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
609extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
610
945e0f82
CZ		 611extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
612extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
613extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
614
db18dbab
GM		 615/* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP
616 Instruction Set Reference Manual v2.4 for a description of address types. */
617
618typedef enum
619{
620 /* Addresses in memory. */
621
622 /* Buffer descriptor. */
623 ARC_NPS400_ADDRTYPE_BD,
624
625 /* Job identifier. */
626 ARC_NPS400_ADDRTYPE_JID,
627
628 /* Linked Buffer Descriptor. */
629 ARC_NPS400_ADDRTYPE_LBD,
630
631 /* Multicast Buffer Descriptor. */
632 ARC_NPS400_ADDRTYPE_MBD,
633
634 /* Summarized Address. */
635 ARC_NPS400_ADDRTYPE_SD,
636
637 /* SMEM Security Context Local Memory. */
638 ARC_NPS400_ADDRTYPE_SM,
639
640 /* Extended Address. */
641 ARC_NPS400_ADDRTYPE_XA,
642
643 /* Extended Summarized Address. */
644 ARC_NPS400_ADDRTYPE_XD,
645
646 /* CMEM offset addresses. */
647
648 /* On-demand Counter Descriptor. */
649 ARC_NPS400_ADDRTYPE_CD,
650
651 /* CMEM Buffer Descriptor. */
652 ARC_NPS400_ADDRTYPE_CBD,
653
654 /* CMEM Job Identifier. */
655 ARC_NPS400_ADDRTYPE_CJID,
656
657 /* CMEM Linked Buffer Descriptor. */
658 ARC_NPS400_ADDRTYPE_CLBD,
659
660 /* CMEM Offset. */
661 ARC_NPS400_ADDRTYPE_CM,
662
663 /* CMEM Summarized Address. */
664 ARC_NPS400_ADDRTYPE_CSD,
665
666 /* CMEM Extended Address. */
667 ARC_NPS400_ADDRTYPE_CXA,
668
669 /* CMEM Extended Summarized Address. */
670 ARC_NPS400_ADDRTYPE_CXD
671
672} arc_nps_address_type;
673
674#define ARC_NUM_ADDRTYPES 16
675
6b477896
TS		 676#ifdef __cplusplus
677}
678#endif
679
886a2506 680#endif /* OPCODE_ARC_H */
GDB Binutils - Deliverables
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